KAUSTUBH PRADEEPSINGH JAMADAR
Course : B.E. (Hons.), Electrical & Electronics, 2026
Email : f20220384@pilani.bits-pilani.ac.in
Mobile : 8830122251
CGPA : 8.67
Digital electronics, Operating System, Control Systems, Microprocessor and Interfacing, Analog
Subjects / Electives
Electronics, Microelectronics circuits, STA
Technical Proficiency Python, C Programming, RTL Design, Xilinx, Linux, LT spice, PyTorch, C++, MATLAB, FPGA, Neural Networks
INTERNSHIPS
CHANAYKA FELLOW, IIT BOMBAY Sep 2024 - Feb 2025
• Project title: Design and Development of a Federated Learning based Smart Object Detection Accelerator for Autonomous Vision
in IoT-enabled systems
• Designed and implemented a 2D convolution accelerator on FPGA (ZedBoard) using FFT algorithms to reduce computational complexity
in convolution operations.
• Leveraged Xilinx IPs (FFT and DMA) for high-throughput data transfer and frequency-domain processing, achieving acceleration suitable
for ML workloads.
• Simulated and synthesized the hardware using Xilinx Vivado, validating the design through testbench verification and resource utilization
analysis.
ML Engineer Intern, Goodmeetings.ai May 2024 - Jul 2024
• Worked on an AI-powered video meeting platform aimed at improving remote team performance, integrating collaborative tools that
boosted user engagement by 30%.
• Contributed to the development of an emotion recognition tool using computer vision to analyze user reactions during meetings in real
time.
• Redesigned the facial emotion detection model, improving its accuracy by 23%, positively impacting 500,000+ users across global
enterprise clients.
PROJECTS
Mitigation of Parasitic Effects in MOSFETs Using Basic Circuit Design In MATLAB - .... May 2024 - Jun 2024
• Designed and simulated a basic power MOSFET switching circuit in MATLAB, incorporating parasitic inductances and capacitances to
evaluate their effects on performance.
• Developed a straightforward mitigation strategy using a snubber circuit to reduce voltage overshoot and ringing caused by parasitic
components.
• Demonstrated a 10% improvement in switching efficiency and a reduction in EMI through simulation, showcasing effective mitigation of
parasitic effects in a fundamental power electronics circuit.
Design and Simulation of a Two-Stage CMOS Operational Amplifier in LT SPICE - ...... Apr 2024 - Jun 2024
• Designed a two-stage CMOS op-amp using a differential pair and active cascode load at a 180 nm node in LTspice, targeting a 3 dB
bandwidth of 100 kHz and an open-loop gain of 7 dB.
• Successfully simulated the design, demonstrating stable performance and meeting all design specifications for low-frequency analog
applications.
Design and Implementation of a 4-Bit Synchronous Up/Down Counter - ..... Aug 2023 - Aug 2023
• Developed a 4-bit synchronous up/down counter using Verilog HDL, capable of incrementing or decrementing based on control input.
• Simulated the design using ModelSim and verified correct behavior through waveform analysis for various input sequences.
• Implemented the counter on Xilinx ZedBoard via Vivado, optimizing for minimal timing delay and accurate clock synchronization.
Design and Simulation of an 8-Bit ALU Using Logic Gates - ..... Apr 2022 - Apr 2022
• Built a functional 8-bit Arithmetic Logic Unit (ALU) from scratch using basic logic gates like AND, OR, XOR, and multiplexers.
• Implemented operations such as addition, subtraction, bitwise AND/OR/XOR, and comparison using combinational and sequential logic.
• Simulated and tested the design using Verilog in ModelSim and synthesized it on Xilinx FPGA, ensuring optimized gate-level performance.
ACHIEVEMENTS
NATIONAL AWARDEE: Indian National Physics OLympaid (IPhO)
Organized by: BARC | Date: Feb 2021
Qualified for the Indian National Physics Olympiad (IPhO) 2021, ranking among the top 35 students nationwide out of thousands of
candidates.
Demonstrated advanced proficiency in theoretical and analytical physics, including mechanics, thermodynamics, and electrodynamics.
Invited to the IPhO Orientation Cum Selection Camp, reflecting a deep aptitude for physics and analytical reasoning.
