Rashi Pandey +91 95699 94226

Roll No.: 2202165 rashipandey0224@gmail.com

Education
• National Institute of Technology Patna Aug 2022 - May 2026
B.Tech in Electrical Engineering CGPA: 8.34
• St. Mary’s Convent School Apr 2019 - Mar 2020
Class XII (CBSE) Percentage: 91.4
• Ram Lakhan Public School Apr 2017 - Mar 2018
Class X (CBSE) Percentage: 90.4

Experience
• IIT Kharagpur May 2025 - July 2025
Summer Research Intern - FPGA-based Underwater Optical Communication.
– Designed an FPGA-based optical data link using UART and ASK modulation for underwater communication at 9600 baud,
achieving <0.5% BER.
• IIIT Hyderabad May 2025 - July 2025
Research Intern - Efficient Hardware Design for Deep Learning Operators, Remote
– Designed an FPGA-based accelerator in Verilog for optimizing 2D convolution tasks, achieving 30% latency reduction and
25% throughput gain using pipelining and parallelism.
– Attained 1.8X execution speed and reduced model size by 45% by implementing pipelining and memory reuse strategies in
Verilog for AI kernels.
• DRDO - Centre for Fire Explosive and Environment Safety May 2024 - July 2024
Summer Intern - Instrumentation in Fire Suit Test Facility, Delhi
– Integrated sensors with DAQ system to monitor high-temperature protective suits, improving data accuracy by 35%.
– Enhanced data analysis speed by 30% and signal conditioning algorithms.
Projects
• Multi-Clock Domain FIFO June 2025 - July 2025
Engineered a dual-clock FIFO in Verilog to interface UART and SPI protocols.
– Tools & Technologies: Verilog, Vivado, UART, SPI, Gray Code logic, Dual Clock FIFO synchronization.
– Ensured reliable multi-clock domain data transfer in Verilog by implementing Gray code pointer synchronization, reducing
metastability risk by more than 95%.
• Traffic Light Controller Mar 2025 - April 2025
Created a finite state machine (FSM)-based traffic signal controller for a 4-way intersection.
– Tools & Technologies: Vivado (simulation), Verilog (using FSM modeling and synthesis)
– Enhanced FSM-based 4-way traffic light controller in Verilog with real-time simulation, achieving 90% timing accuracy for
phase transitions between traffic signal states.
• Electronic Tongue based Tea Sample Classification Feb 2025 - Mar 2025
Benchmarked ML classifiers (PCA, SVM, DT, KNN) tea dataset with 87% accuracy.
– Tools & Technologies: MATLAB (feature extraction, ML pipeline), PCA, SVM, Decision Tree, KNN.
– Improved a PCA-based machine learning model in MATLAB, achieving 95% accuracy in taste classification by extracting
key features and reducing dimension.

Skills
Languages: C, C++, Python, Verilog, MATLAB.
Developer Tools: Vivado, ModelSim, Cadence Virtuoso, LTspice, Synopsys TCAD, Arduino IDE, Git.
Coursework: Digital Electronics, Analog Electronics, Verilog, Static Timing Analysis (STA).
Areas of Interest: Digital and Analog VLSI Design, RTL Design, SoC Architecture, Verilog, Machine Learning, Deep Learning.

Responsibilities
• Web Lead, Robotics Club Jan 2023 - Jan 2025
• Technical Lead, Incubation Club March 2023 - Nov 2023

Achievements
•India Semiconductor Workforce Development Program: Organized by Samsung, Synopsys and IISc Bangalore
•ISRO: Selected among the Top 100 nationwide for Summer Internship at ISRO.

Certifications
• Completed Fundamentals of Digital Design for VLSI Chip Design offered by L&T EduTech.
• Completed NPTEL course titled "The Joy of Computing Using Python" from IIT Ropar.