PALURU SAAKETH
an Under Graduate student at RGUKT RK Valley
palurusaaketh2@gmail.com — +91 7093070626 — Yerraguntla, Kadapa (Dt), Andhra Pradesh - 516309
OBJECTIVE
Aspiring VLSI engineer with a strong foundation in digital and PCB circuit design, RTL coding using Verilog, and
hands-on experience in FPGA-based projects. Passionate about semiconductor technology and eager to contribute
to cutting-edge chip design and verification. Seeking a challenging role in a core VLSI company to apply my skills
in design, simulation, and verification for innovative hardware solutions.
EDUCATION
• B.Tech in Electronics and Communication Engineering, RGUKT RK Valley (2022–Present) — CGPA:
• Pre-University Course, RGUKT RK Valley (2020–2022) — CGPA: 9.0
• Zilla Parishad (boys) High School (ZPHS), Yerraguntla (2020) — SSC CGPA: 10
SKILLS
Digital Design & RTL: Combinational and Sequential Circuits, Verilog and Finite State Machines
Computer Architecture Basics: 32-bit Processor, ALU, Register File, Pipeline Stages (IF, ID, EX, MEM,
WB)
Timing & Logic: Static Timing Analysis (STA), Setup/Hold Time, Clock Skew, Clock Gating
FPGA Design: FPGA Architecture (CLBs, LUTs), Bitstream Generation
EDA Tools and Verification: Xilinx Vivado, SystemVerilog
Soft Skills: Team Collaboration, Problem Solving
RESEARCH & PUBLICATIONS
• Conference Paper: “FPGA-Powered Smart Irrigation: Real-Time Water Optimization for Sustainable Agri-
culture” (submitted)
• Ongoing Research: “AI Based Fault Detection using Verilog in a 32-bit Processor Core”
PROJECTS
• FIFO Implementation: Designed and implemented a parameterized FIFO in Verilog, improving data through-
put by 25% and ensuring reliable buffering under high-speed conditions.
• RISC-V Processor: Implemented a 32-bit RISC-V processor in Verilog with support for RV321 instructions,
achieving 100% functional coverage and successful RTL simulation.
• Digital Clock: Implemented a digital clock with time, reset, and enable features, achieving 100% precise
timing through clock division logic.
• Seven Segment on LCD: Interfaced a seven-segment display on LCD using Verilog, displaying real-time
counter output with 100% clock division and multiplexing logic.
• Battery Management System (BMS) using PCB Design: Designed a BMS PCB in Altium for safe Lithium-ion
cell monitoring, balancing, and over-voltage protection.
PROTOCOLS
• I2C: Integrated I2C Protocol in RTL design to enable reliable master-slave communication between digital
peripherals.
• AXI: Developed and verified AXI4-compliant interface for high-throughput, low-latency data transfer in SoC
designs.
ONLINE COURSES & CERTIFICATIONS
• PCB Design Certificates (Udemy)
• VLSI Design Certificate (Springboard Infosys)
• Astronics 5.0 Workshop
• FPGA Workshop Certificate
INTERNSHIP & EXPERIENCE
• SSIT: Hands-on implementation of digital circuits on FPGA boards
LANGUAGES
English, Telugu
HOBBIES
Exploring Technologies, Playing Games, Listening to Music
SUMMARY
Motivated undergraduate student with a strong foundation in electronics and problem-solving skills. Passionate
about working with core electronics companies.
DECLARATION
I hereby declare that the above information is true to the best of my knowledge.
