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Paluru Saaketh is an undergraduate student at RGUKT RK Valley pursuing a B.Tech in Electronics and Communication Engineering with a strong academic background and a CGPA of 8.5. He has skills in VLSI design, digital circuit design, and FPGA projects, along with research experience and multiple projects including FIFO implementation and RISC-V processor design. Saaketh is seeking a challenging role in a core VLSI company to apply his expertise in innovative hardware solutions.

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5 views1 page

My Resumei

Paluru Saaketh is an undergraduate student at RGUKT RK Valley pursuing a B.Tech in Electronics and Communication Engineering with a strong academic background and a CGPA of 8.5. He has skills in VLSI design, digital circuit design, and FPGA projects, along with research experience and multiple projects including FIFO implementation and RISC-V processor design. Saaketh is seeking a challenging role in a core VLSI company to apply his expertise in innovative hardware solutions.

Uploaded by

kanna.saaketh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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PALURU SAAKETH

an Under Graduate student at RGUKT RK Valley


Ó +91 7093070626 Q palurusaaketh2@gmail.com Yerraguntla, Kadapa (Dt), Andhra Pradesh - 516309

OBJECTIVE

Aspiring VLSI engineer with a strong foundation in digital and PCB circuit design, RTL coding using Verilog, and
hands-on experience in FPGA-based projects. Passionate about semiconductor technology and eager to contribute
to cutting-edge chip design and verification. Seeking a challenging role in a core VLSI company to apply my skills in
design, simulation, and verification for innovative hardware solutions.

EDUCATION

• B.Tech in Electronics and Communication Engineering, RGUKT RK Valley (2022–Present) — CGPA:8.5


• Pre-University Course, RGUKT RK Valley (2020–2022) — CGPA: 9.0
• Zilla Parishad (boys) High School (ZPHS), Yerraguntla (2020) — SSC CGPA: 10

SKILLS

Digital Design & RTL: Combinational and Sequential Circuits, Verilog and Finite State Machines
Computer Architecture Basics: 32-bit Processor, ALU, Register File, Pipeline Stages (IF, ID, EX, MEM, WB)
Timing & Logic: Static Timing Analysis (STA), Setup/Hold Time, Clock Skew, Clock Gating
FPGA Design: FPGA Architecture (CLBs, LUTs), Bitstream Generation
EDA Tools and Verification: Xilinx Vivado, SystemVerilog
Soft Skills: Team Collaboration, Problem Solving

RESEARCH & PUBLICATIONS

• Conference Paper: “FPGA-Powered Smart Irrigation: Real-Time Water Optimization for Sustainable Agricul-
ture” (submitted)
• Ongoing Research: “AI Based Fault Detection using Verilog in a 32-bit Processor Core”

PROJECTS

• FIFO Implementation: Designed and implemented a parameterized FIFO in Verilog, improving data throughput
by 25% and ensuring reliable buffering under high-speed conditions.
• RISC-V Processor: Implemented a 32-bit RISC-V processor in Verilog with support for RV321 instructions,
achieving 100% functional coverage and successful RTL simulation.
• Digital Clock: Implemented a digital clock with time, reset, and enable features, achieving 100% precise timing
through clock division logic.
• Seven Segment on LCD: Interfaced a seven-segment display on LCD using Verilog, displaying real-time counter
output with 100% clock division and multiplexing logic.
• Battery Management System (BMS) using PCB Design: Designed a BMS PCB in Altium for safe Lithium-
ion cell monitoring, balancing, and over-voltage protection.

PROTOCOLS

• I2C: Integrated I2C Protocol in RTL design to enable reliable master-slave communication between digital periph-
erals.
• AXI: Developed and verified AXI4-compliant interface for high-throughput, low-latency data transfer in SoC
designs.

ONLINE COURSES & CERTIFICATIONS

• pcb design certificates (udemy) • Astronics 5.0 Workshop


• vlsi design certificate (springboard infosys) • FPGA workshop certificate

INTERNSHIP & EXPERIENCE

• Sense Semiconductor and IT Solutions PVT.LTD (SSIT)

• Hands-on implementation of digital circuits on FPGA boards

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