PALURU SAAKETH
an Under Graduate student at RGUKT RK Valley
Ó +91 7093070626 Q palurusaaketh2@gmail.com Yerraguntla, Kadapa (Dt), Andhra Pradesh - 516309
EDUCATION
• B.Tech in Electronics and Communication Engineering, RGUKT RK Valley (2022–Present) — CGPA:7.7
• Pre-University Course, RGUKT RK Valley (2020–2022) — CGPA: 9.0
• Zilla Parishad (boys) High School (ZPHS), Yerraguntla (2020) — SSC CGPA: 10
RESEARCH & PUBLICATIONS
• Conference Paper:“FPGA-Powered Smart Irrigation: Real-Time Water Optimization for Sustainable Agriculture”
(submitted).
– Designed and implemented an FPGA-based real-time smart irrigation system for optimized water usage in agricultural fields.
– Developed hardware logic for soil moisture sensing, rain sensor sensing, water level sensor,integrating with led and buzzer
and automated water control using Verilog/VHDL.
– Achieved 100% water savings compared to conventional irrigation methods.
– Synthesized and tested on EDGE Artix7 FPGA board ensuring high reliability.
• Ongoing Research: “AI Based Fault Detection using Verilog in a 32-bit Processor Core”
– Developing error detection and correction logic to identify stuck-at, delay, and bridging faults in real-time.
– in future try to Implementing machine learning-inspired pattern recognition for predicting and isolating faulty modules
within the processor pipeline.
– Aim is to Achieve 100% improvement in fault detection accuracy .
SKILLS
• sensors & actuators : temparature,oxygen,solenoid actuators.
• protocols:LIN communication used in vehicles.
• Digital : Combinational, Sequential Circuits .
• Analog: bjt ,Mosfet.
• embedded: microprocessor,microcontroller.
PROJECTS
• FIFO Implementation:
– Designed and implemented a parameterized synchronous/asynchronous FIFO in Verilog HDL, improving data throughput
by 25% and ensuring reliable buffering under high-speed data transfer conditions.
– Synthesized and verified the design using ModelSim Xilinx Vivado, focusing on timing closure and metastability handling.
– Integrated into SoC/processor pipeline (or communication interface, if applicable) to optimize latency and bandwidth
utilization.
• RISK-v Processor:
– Implemented a 32-bit RISC-V processor core in Verilog HDL with support for RV32I instruction set, achieving 100%
functional coverage through extensive testbench verification.
– Performed RTL simulation and debugging using ModelSim/Vivado, ensuring correct instruction execution and pipeline
functionality.
– Designed with a 5-stage pipeline (IF, ID, EX, MEM, WB) (if applicable) and verified hazard detection, forwarding, and
branch prediction logic for improved performance.
– Achieved cycle-accurate simulation results, validating against RISC-V compliance test suite (if used).
EXPERIENCE
summer Intern - Sense Semiconductor and IT Solutions PVT.LTD (SSIT)
• Gained hands on experience with digital circuits.
• Worked with Artix-7Edge Board and DE10-Nano using tools such as Xilinx viavdo.
