QB (M4, M5)

This document is a question bank for the Digital System Design using Verilog course (BEC302) for the III semester, prepared by Mrs. Meghana M N. It includes questions from Modules 4 and 5, covering topics such as Verilog module structure, data types, logical and relational operators, if and case statements, and loops. Additionally, it contains requests for programming examples in dataflow, behavioral, and structural descriptions.

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QB (M4, M5)

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meghana.ece.mitt

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DEPARTMENT OF

ELECTRONICS AND COMMUNICATION ENGINEERING

DIGITAL SYSTEM DESIGN USING VERILOG

BEC302
III SEMESTER
IA3 QUESTION BANK (MODULE 4,5)
Prepared by,
Mrs. MEGHANA M N
Assistant Professor
Dept. of ECE
MIT Thandavapura

A Unit of Maharaja Education Trust®

MAHARAJA INSTITUTE OF TECHNOLOGY

THANDAVAPURA

NH 766, Nanjangud Taluk, Mysuru- 571 302

(An ISO 9001:2015 and ISO 21001:2018 Certified Institution)
(Affiliated to VTU, Belagavi and approved by AICTE, New Delhi)
MODULE 4

Questions
1. Explain the structure of verilog module with an example.
2. Write a note on data types of Verilog.
3. Give the classification of styles of description with example.
4. Describe the 3 different logical operators used in verilog with an example for each type.
5. Describe the relational operators used in verilog with an example for each type.
6. Programs (dataflow description)

MODULE 5

Questions
7. Explain the functionality of 3 different variations in if statement with an example for each.
8. Explain the functionality of case statement with 2 variations in it.
9. Write a note on loops in verilog. (all 4 loops)
10. Programs (Behavioral description)
11. Programs (Structural description)

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QB (M4, M5)

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QB (M4, M5)

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DEPARTMENT OF

ELECTRONICS AND COMMUNICATION ENGINEERING

DIGITAL SYSTEM DESIGN USING VERILOG

A Unit of Maharaja Education Trust®

MAHARAJA INSTITUTE OF TECHNOLOGY

NH 766, Nanjangud Taluk, Mysuru- 571 302

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