paper-2

1. Discuss the architecture of 8086 microprocessor. Explain EU and BIU with

functional block diagram.

2. Draw and explain the pin diagram of 8086 with respect to various
operating modes of 8086.

3. (a) Write an assembly language program in 8086 and draw the flow chart to
arrange 16-bit numbers in ascending order.
(b) Classify the instructions of 8086. What is the function of the Lock prefix used
with an 8086 instruction ?

4. (a) What are the assembler directives that are related to segment declaration ?
Explain with examples.
(b) What is the function of an interrupt in a microprocessor ? What is the step by
step procedure for processing of interrupts by 8086? What is interrupt vector
table?

5. (a) Explain the instructions ACALL, SJMP, DJNZ, CJNE and JNZ in 8051
microcontroller.
(b) Explain the function of DPTR and SP registers in 8051.

6. (a) Discuss the bit assignments of TMOD special function register in 8051.
(b) Discuss mode 1 and mode 2 of timer operation in 8051. Assuming that XTAL =
11.0592 MHz. Write an assembly language program to generate a square wave of
2 kHz frequency on pin P1.5 using timer 1.

7.(a) Explain the serial port operation in 8051. Distinguish between synchronous
and asynchronous serial communication. How do we set the baud rate ? Name
various modes of serial port operation and briefly explain them.
b) Write a program in 8051 to transfer "A" serially at 4800 baud, continuously
XTAL = 11.0592 MHz.

8.(a) Give the bit details of IE register used for programming with interrupts in
8051.
(b) Write about the number of interrupts in 8051. Explain with example, the steps
to service an interrupt
1. Discuss the architecture of 8086 microprocessor. Explain EU and BIU
with functional block diagram.
The 8086 microprocessor features a segmented memory architecture with two
main units: the Execution Unit (EU) and the Bus Interface Unit (BIU). The BIU
handles all bus operations, including instruction fetching, reading and writing
operands, and address calculation for memory accesses. The EU decodes and
executes instructions fetched by the BIU.
1. Bus Interface Unit (BIU):
>Instruction Fetching:
The BIU is responsible for fetching instructions from memory and storing them in
a 6-byte instruction queue.
>Memory Access:
It handles reading and writing operands from and to memory locations.
>Address Calculation:
The BIU generates physical memory addresses by combining segment register
values and offset values.
>Pipelining:
By pre-fetching instructions and storing them in the instruction queue, the BIU
enables pipelining, allowing the EU to execute instructions while the BIU fetches
the next set of instructions.
>Data Transfer:
The BIU facilitates data transfer between the microprocessor and memory or I/O
devices.
2. Execution Unit (EU):
>Instruction Decoding:
The EU decodes instructions fetched from the instruction queue in the BIU.
>Instruction Execution:
It executes the decoded instructions, performing arithmetic, logical, and control
operations.
>Control:
The EU controls the operations on data, including the use of the ALU and other
functional units.
>No Direct Bus Connection:
The EU does not directly connect to the system buses. It relies on the BIU to
access memory or I/O devices.
>Functional Block Diagram:
Architecture of 8086 Microprocessor - Block Diagram & its Parts
The 8086's architecture can be represented by a functional block diagram
illustrating the interaction between the BIU and EU. The BIU and EU are connected
by an internal bus, allowing them to communicate and share data.
>Key Features:
>Segmented Memory:
The 8086 uses a segmented memory architecture, dividing memory into segments
and using segment registers to address them.
>Instruction Queue:
The BIU uses a 6-byte instruction queue to pre-fetch instructions, enabling
pipelining.
>16-bit Architecture:
The 8086 is a 16-bit microprocessor with 20 address lines and 16 data lines,
allowing it to address up to 1MB of memory.

Diagram:

2. Draw and explain the pin diagram of 8086 with respect to various
operating modes of 8086.
The 8086 microprocessor operates in two modes: Minimum Mode (MIN) and
Maximum Mode (MAX). The pin diagram for each mode differs, primarily in the
signals used for control and status. In MIN mode, the 8086 generates its own
control signals, while in MAX mode, an external bus controller like the 8288 is
used to generate these signals.

Pin Diagram: 8086 in Minimum Mode (MIN)

The MIN mode pin diagram focuses on the control signals generated by the 8086
itself for interfacing with memory and I/O devices.

Key Pins in MIN Mode:

>Vcc (Pin 40): Power Supply, providing +5V.
>GND (Pin 1): Ground, providing the reference voltage.
>CLK (Pin 19): Clock input, providing the timing signal for the 8086.
>RESET (Pin 18): Resets the 8086, initiating the boot sequence.
>READY (Pin 17): Indicates whether memory or I/O is ready for a data transfer.
>INTR (Pin 22): Interrupt request, enabling the 8086 to respond to external events.
>NMI (Pin 17): Non-maskable interrupt, a higher-priority interrupt.
>HLDA (Pin 24): Hold Acknowledge, signals that the 8086 is acknowledging a hold
request.
>HOLD (Pin 23): Hold, a request to temporarily relinquish control of the bus to
another device.
>ALE (Pin 20): Address Latch Enable, enables the address latching circuitry.
>DT/R (Pin 21): Data Transmit/Receive, controls the direction of data flow.
>M/IO (Pin 25): Memory/I/O, distinguishes between memory and I/O access.
>WR (Pin 26): Write, controls the write operation to memory or I/O.
>RD (Pin 39): Read, controls the read operation from memory or I/O.
>BHE/S7 (Pin 34): Bus High Enable/Status 7, enables the upper byte of the data
bus.
>AD0-AD15 (Pins 2-16, 35-38): Address/Data bus, carries both address and data.
>A16-A19 (Pins 28-31): Address bus, carries the higher-order address bits.
>S0-S2 (Pins 28-30): Status signals, indicate the type of memory access or I/O
operation.

Pin Diagram: 8086 in Maximum Mode (MAX)

The MAX mode pin diagram focuses on the status and control signals generated
by the external bus controller (8288).

Key Pins in MAX Mode:

>Vcc (Pin 40): Power Supply, providing +5V.
>GND (Pin 1): Ground, providing the reference voltage.
>CLK (Pin 19): Clock input, providing the timing signal for the 8086.
>RESET (Pin 18): Resets the 8086, initiating the boot sequence.
>READY (Pin 17): Indicates whether memory or I/O is ready for a data transfer.
>INTR (Pin 22): Interrupt request, enabling the 8086 to respond to external events.
Diagram:

3. (a) Write an assembly language program in 8086 and draw the flow chart to
arrange 16-bit numbers in ascending order.
DATA SEGMENT
NUMBERS DW 1000H, 2000H, 3000H, 4000H, 5000H, 6000H, 7000H, 8000H,
9000H, 0A000H ; Sample 16-bit numbers
COUNT DW 10 ; Number of elements
DATA ENDS

STACK SEGMENT
DW 256 DUP(?)
STACK ENDS

CODE SEGMENT
ASSUME CS:CODE, DS:DATA, SS:STACK

START:
MOV AX, DATA
MOV DS, AX
MOV AX, STACK
MOV SS, AX
MOV SP, 256

MOV SI, OFFSET NUMBERS

 MOV CX, COUNT ; Count register holds the number of elements
MOV BX, 0 ; Outer loop counter

UP2:
MOV CX, COUNT ; Reset inner loop counter
MOV BX, 0 ; Outer loop counter
MOV SI, OFFSET NUMBERS ; Reset array pointer

UP1:
MOV AX, [SI] ; Load current element
MOV DX, [SI+2] ; Load next element

CMP AX, DX ; Compare current element with next element

JGE DOWN ; If current element is greater than or equal to next
element, swap

MOV DX, [SI] ; Swap elements

MOV [SI], DX
MOV [SI+2], AX
MOV DX, [SI] ; Swap elements

INC SI ; Point to next element

DEC CX ; Decrement inner loop counter
JNZ UP1 ; If inner loop counter is not zero, continue inner loop

INC SI ; Point to next element

DEC BX ; Decrement outer loop counter
JNZ UP2 ; If outer loop counter is not zero, continue outer loop

DOWN:
INC SI ; Point to next element
DEC BX ; Decrement outer loop counter
JNZ UP2 ; If outer loop counter is not zero, continue outer loop

; Program Termination
MOV AX, 4C00H
INT 21H
CODE ENDS
END START

Flow chart:
graph TD
A[Start] --> B{Initialize DATA, STACK segments};
B --> C{Set DS, SS registers};
C --> D{Initialize Stack Pointer};
D --> E{Set SI (Index to NUMBERS), CX (Count), BX (Loop Counter)};
E --> F{Outer Loop (UP2):};
F --> G{Inner Loop (UP1):};
G --> H{Load AX = [SI] (current element), DX = [SI+2] (next element)};
H --> I{Compare AX and DX (JGE DOWN if AX >= DX)};
I --> J{Swap AX and DX if necessary};
J --> K{INC SI, DEC CX};
K --> L{JNZ UP1 (Continue inner loop)};
L --> M{INC SI, DEC BX};
M --> N{JNZ UP2 (Continue outer loop)};
N --> O{Program Termination (INT 21H)};
O --> A;
I -- No Swap --> K;
(b) Classify the instructions of 8086. What is the function of
the Lock prefix used with an 8086 instruction ? Classification of
8086 Instructions
The **Intel 8086** microprocessor instructions are broadly classified into the
following categories:

1. **Data Transfer Instructions**

These instructions move data from one location to another.
* Examples: `MOV`, `PUSH`, `POP`, `XCHG`, `IN`, `OUT`, `LEA`, `LDS`, `LES`

2. **Arithmetic Instructions**
These perform arithmetic operations like addition, subtraction, etc.
* Examples: `ADD`, `ADC`, `SUB`, `SBB`, `MUL`, `IMUL`, `DIV`, `IDIV`, `INC`, `DEC`,
`NEG`, `CMP`

3. **Logical Instructions**
These perform bitwise operations and logical comparisons.
* Examples: `AND`, `OR`, `XOR`, `NOT`, `TEST`

4. **String Instructions**
These operate on string data.
* Examples: `MOVS`, `CMPS`, `SCAS`, `LODS`, `STOS`

5. **Control Transfer Instructions**

Used for altering the flow of control (jumps, calls, returns).
*Unconditional jumps**: `JMP`
*Conditional jumps**: `JE`, `JNE`, `JG`, `JL`, etc.
*Procedure control**: `CALL`, `RET`, `INT`, `IRET`, `INTO`

6. **Processor Control Instructions**

Used for managing the state of the processor.
* Examples: `CLC`, `STC`, `CLI`, `STI`, `CLD`, `STD`, `HLT`, `WAIT`, `NOP`

7. **Shift and Rotate Instructions**

Used for bit manipulation.
* Examples: `SHL`, `SAL`, `SHR`, `SAR`, `ROL`, `ROR`, `RCL`, `RCR`
 8. **Flag Manipulation Instructions**
Directly affect the flag register.
* Examples: `LAHF`, `SAHF`, `PUSHF`, `POPF`

# Function of the `LOCK` Prefix

The **`LOCK`** prefix is used in **multiprocessor systems** to ensure
**atomicity** of certain instructions that access memory. When the `LOCK` prefix
is used:
* The processor **asserts the bus lock signal** during the execution of the
instruction.
* It prevents other processors or devices from accessing the system bus, thus
ensuring the instruction completes **without interruption**.

#Conditions:

* It can only be used with instructions that **modify memory** and support the
`LOCK` prefix (e.g., `XCHG`, `INC`, `DEC`, `ADD`, `SUB`, etc.).
* It is **ignored** if used with instructions that do not support it.

#Example:
```asm
LOCK INC [BX]

This ensures that the memory location pointed by `BX` is incremented atomically
— useful in critical sections of code in concurrent environments.

Let me know if you'd like examples or a deeper explanation of any category!

4.(a) What are the assembler directives that are related to

segment declaration ? Explain with examples.
Assembler directives related to segment declaration include SEGMENT, ENDS, and
ASSUME. These directives help the assembler understand how to organize code
and data into logical units called segments, which are then mapped to physical
memory segments during program execution.

1. SEGMENT:
Purpose: Marks the beginning of a logical segment.
Example: CODE SEGMENT This statement indicates the start of a logical segment
named "CODE" that will contain instructions.

2. ENDS:
Purpose: Marks the end of a logical segment.
Example: CODE ENDS This statement indicates the end of the "CODE" segment.

3. ASSUME:
Purpose:
Tells the assembler which logical segments should be associated with specific
segment registers (CS, DS, SS, ES). The 8086 processor uses these segment
registers to access memory.
Example:
ASSUME CS:CODE, DS:DATA This statement tells the assembler that the "CODE"
segment should be used with the CS register and the "DATA" segment with the DS
register.

Example of a Segment Declaration:

DATA SEGMENT
my_data DB 10, 20, 30
data_end DW 0 ; reserve space for a word
DATA ENDS

CODE SEGMENT
ASSUME CS:CODE, DS:DATA ; tell the assembler how the code and data
segments relate to the processor
START:
MOV AX, DATA
MOV DS, AX
MOV AX, 0
; Code here

CODE ENDS
END START

Explanation of the Example:

1.DATA SEGMENT: This line defines the start of a logical segment named "DATA".
2.my_data DB 10, 20, 30: This line reserves memory in the "DATA" segment for
three bytes and initializes them with the values 10, 20, and 30.
3.data_end DW 0: Reserves a 2-byte (word) memory location in the data segment
and initializes it to 0.
4.DATA ENDS: This line marks the end of the "DATA" segment.
5.CODE SEGMENT: This line defines the start of a logical segment named "CODE".
6.ASSUME CS:CODE, DS:DATA: This tells the assembler that the "CODE" segment
should be used for code instructions (CS register), and the "DATA" segment for
data (DS register).
7.START:: A label indicating the starting point of the code.
8.MOV AX, DATA: This line moves the segment address of "DATA" into the AX
register.
9.MOV DS, AX: This line moves the segment address from AX into the DS register,
allowing the program to access data in the "DATA" segment.
10.MOV AX, 0: This line initializes the AX register to 0.
11.CODE ENDS: This line marks the end of the "CODE" segment.
12.END START: This line indicates the end of the program and specifies that the
"START" label is the entry point.

(b) What is the function of an interrupt in a microprocessor ? What is

the step by step procedure for processing of interrupts by 8086? What
is interrupt vector table?
An interrupt allows a device or software to request the microprocessor to stop its
current task and attend to a more urgent event. The 8086 uses an interrupt vector
table (IVT) to store addresses of interrupt service routines (ISRs). This allows the
processor to quickly jump to the appropriate routine to handle the interrupt.
Interrupt Function and Purpose:
Interrupts allow a microprocessor to handle asynchronous events, such as a
keyboard input, disk I/O completion, or a hardware error, without having to
continuously poll devices to check for these events. When an interrupt occurs, the
processor temporarily stops its current task and jumps to a dedicated interrupt
service routine (ISR) to handle the event. This improves efficiency and
responsiveness.
8086 Interrupt Processing Procedure:

1. Interrupt Recognition:
The microprocessor continuously checks its interrupt pins (INTR and NMI) and
internal interrupt flags for interrupt requests.

2. Completion of Current Instruction:

If an interrupt is detected, the processor completes the execution of the current
instruction.

3. Saving Context:
The processor pushes the flags, CS, and IP registers onto the stack to save the
current program state.

4. Disabling Further Interrupts:

The processor disables further interrupts by clearing the IF (Interrupt Flag) in the
flag register.

5. Jumping to ISR:
The processor uses the interrupt vector table (IVT) to find the starting address of
the appropriate ISR.

6. Executing ISR:
The processor jumps to the ISR and executes it.

7. Returning to Main Program:

After the ISR finishes, the processor returns to the main program by popping the
saved context from the stack and resuming execution.

Interrupt Vector Table (IVT):

The IVT is a memory area that contains the addresses of the interrupt service
routines (ISRs) for different interrupt types. Each entry in the IVT is 4 bytes long,
containing the segment address (CS) and the offset address (IP) of the ISR. The IVT
starts at memory address 00000H and is 1024 bytes long, providing entries for 256
different interrupt types (00H to FFH). This allows the processor to quickly
determine which ISR to jump to based on the interrupt type.
5. (a) Explain the instructions ACALL, SJMP, DJNZ, CJNE and JNZ in
8051 microcontroller.
In the 8051 microcontroller, the instructions ACALL, SJMP, DJNZ, CJNE, and JNZ are
used for program control and branching. ACALL and SJMP are jump instructions,
DJNZ and CJNE are used for loop control, and JNZ is used for conditional branching
based on the Accumulator value.

1. ACALL (Absolute Call):

>Purpose:
ACALL calls a subroutine at the specified address, pushing the current program
counter (PC) onto the stack before transferring control.
>Addressing:
Uses a 11-bit address, allowing access within 2KB of the program memory.
>Mechanism:
The PC's current value is pushed onto the stack, LSB first, MSB second.
The PC is then loaded with the new address, initiating execution of the subroutine.
>Return:
The subroutine's return instruction, RET, pops the address from the stack,
resuming program execution.

2. SJMP (Short Jump):

>Purpose:
Unconditionally jumps to a location within a limited range of the current PC.
>Addressing:
Uses an 8-bit relative address, allowing jumps within -128 to +127 bytes from the
current PC.
>Mechanism:
The PC is updated with the new address, determined by adding the relative
address to the current PC.
>Example:
If the current PC is 100H and the SJMP instruction has a relative address of 10H,
the new PC becomes 110H.

3. DJNZ (Decrement and Jump if Not Zero):

>Purpose:
Decrements a specified register or memory location, and jumps if the result is not
zero.
>Mechanism:
.The content of the specified register (R0-R7) or memory location (direct address)
is decremented.
.If the result is not zero, the PC is updated to jump to the address specified by the
relative address.
.If the result is zero, the next instruction after DJNZ is executed.

>Use in Loops:
Commonly used to create loops by decrementing a counter and jumping back to
the loop's starting point.

4. CJNE (Compare and Jump if Not Equal):

>Purpose: Compares the values of two operands (memory location or register)
and jumps if they are not equal.
>Addressing: Uses relative addressing, similar to SJMP.
>Mechanism:
.The values of the two operands are compared.
.If the values are not equal, the PC is updated to jump to the address specified by
the relative address.
.If the values are equal, the next instruction after CJNE is executed.

5. JNZ (Jump if Not Zero):

>Purpose: Jumps to a specified address if the Accumulator's value is not zero.
>Addressing: Uses relative addressing, similar to SJMP.
>Mechanism:
.The Accumulator's value is checked.
.If the Accumulator's value is not zero, the PC is updated to jump to the address
specified by the relative address.
.If the Accumulator's value is zero, the next instruction after JNZ is executed.

(b) Explain the function of DPTR and SP registers in 8051

In the 8051 microcontroller, the DPTR (Data Pointer) and SP (Stack Pointer)
registers are both crucial for managing memory and program execution. The DPTR
is a 16-bit register used for addressing external memory and accessing data within
the program segment, while the SP is also a 16-bit register that points to the
current location in the stack, which is used to store information during subroutine
calls and interrupt handling.

DPTR (Data Pointer):

>The DPTR is a 16-bit register that can be accessed as two 8-bit registers, DPH
(high byte) and DPL (low byte).
>It's primarily used to point to memory locations, especially when accessing
external memory.
>The DPTR is used with instructions like MOVX and MOVC to move data to/from
external memory and to access code from external memory, respectively.
>When accessing external memory, the DPTR's value is used as the address.
>The DPTR can also be used for indirect addressing within internal memory.
>It's a key component for accessing external RAM and ROM, allowing the 8051 to
interact with a larger address space beyond its internal memory.

SP (Stack Pointer):
>The SP is a 16-bit register that always points to the next available location in the
stack, which is part of the internal RAM.
>The stack is used to store return addresses when subroutine calls or interrupts
occur.
>When a subroutine is called, the current Program Counter (PC) value is pushed
onto the stack, and the SP is incremented.
>When a subroutine is returned, the SP is decremented, and the return address is
popped from the stack and loaded into the PC.
>The stack is also used to store the values of registers when interrupts occur,
allowing for the preservation of the processor's state.
>The SP is incremented by 1 for each item pushed onto the stack and
decremented by 1 for each item popped off the stack.

6. (a) Discuss the bit assignments of TMOD special function register in

8051.
### (a) **Bit Assignments of TMOD (Timer Mode) Special Function Register in
8051 Microcontroller**

The **TMOD (Timer Mode)** register in the **8051 microcontroller** is an 8-bit

**Special Function Register (SFR)** used to configure the **mode of operation of
Timer 0 and Timer 1**.

Each timer is allocated **4 bits** in the TMOD register:

*Lower 4 bits** (bits 0–3) are for **Timer 0**
*Upper 4 bits** (bits 4–7) are for **Timer 1**

Bit: 7 6 5 4 | 3 2 1 0
GATE C/T M1 M0 | GATE C/T M1 M0
↑ ↑ ↑ ↑ | ↑ ↑ ↑ ↑
Timer 1 settings | Timer 0 settings

# Explanation of Each Bit:

# Example:
TMOD = 0x21 → 0010 0001 (binary)

*Timer 1**: `0010` → `GATE=0, C/T̅=0, M1=1, M0=0` → Mode 2 (8-bit

Auto-reload), internal clock, no external control.
*Timer 0**: `0001` → `GATE=0, C/T̅=0, M1=0, M0=1` → Mode 1 (16-bit Timer),
internal clock.

# Summary Table:

| Mode | M1 M0 | Description |
|0 | 0 0 | 13-bit timer mode |
|1 | 0 1 | 16-bit timer mode |
|2 | 1 0 | 8-bit auto-reload |
|3 | 1 1 | Split mode (Timer 0); Timer 1 halts |

(b) Discuss mode 1 and mode 2 of timer operation in 8051. Assuming

that XTAL = 11.0592 MHz. Write an assembly language program to
generate a square wave of 2 kHz frequency on pin P1.5 using timer 1.
**Timer Operation Modes in 8051: Mode 1 and Mode 2**
# **Mode 1: 16-bit Timer Mode**
* **Description**: Timer is configured as a **16-bit counter**.

*Registers Used**:
* TLx (Timer Low)
* THx (Timer High)
*Operation**:
* The timer counts from the value loaded in `TLx` and `THx` up to **FFFFH
(65535)**.
* After overflowing, it sets the **TFx (Timer Overflow Flag)** and stops (unless
restarted).

*Applications**: Accurate time delays and frequency generation.

# **Mode 2: 8-bit Auto-Reload Mode**

* **Description**: Timer operates as an **8-bit timer with auto-reload**.
*Registers Used**:
* TLx is the actual counter.
* THx holds the reload value.
*Operation**:
* TLx counts up from the reload value.
* When TLx overflows (reaches FFH → 00H), it is **automatically reloaded**
from THx.
* No need to manually reload each time.

*Applications**: Generating repetitive, periodic timing (e.g., baud rate

generation).

# **Assumptions for the Program**

*XTAL = 11.0592 MHz**
* Timer frequency = `XTAL / 12` = **921.6 kHz**
* Each timer tick = **1.085 µs**
* **2 kHz square wave** means:

*Period** = 1 / 2000 = **500 µs**

* So, **ON time** = 250 µs, **OFF time** = 250 µs
We will toggle **P1.5** every **250 µs**.

# **Timer Delay Calculation**

To generate a delay of **250 µs**:
* Required ticks = 250 µs / 1.085 µs ≈ **230 ticks**
* Timer counts from value up to 256 in Mode 2:
* Initial value = 256 - 230 = **26** (1A in hex)

# **Assembly Program to Generate 2 kHz Square Wave on P1.5 Using Timer 1 in

Mode 2**

`assembly
# **Explanation**
* `TMOD = 20H`: Set Timer 1 to Mode 2 (binary `0010 0000`)
* `TH1 = #1AH`: Set reload value for 250 µs
* `TL1 = #1AH`: Start from the same value
* Timer overflows every 250 µs, toggling P1.5, resulting in a full cycle (ON+OFF)
every 500 µs ⇒ **2 kHz square wave**

7.(a) Explain the serial port operation in 8051. Distinguish between

synchronous and asynchronous serial communication. How do we set
the baud rate ? Name various modes of serial port operation and
briefly explain them.
# Serial Port Operation in 8051 Microcontroller
The **8051 microcontroller** includes a built-in serial port (UART - Universal
Asynchronous Receiver/Transmitter) which allows data transmission and
reception through serial communication. It is **full duplex**, meaning it can
transmit and receive data simultaneously.

The serial port operations are controlled by:

*SCON (Serial Control) Register**: Configures the serial port and controls its
operation modes.
*SBUF (Serial Buffer) Register**: Holds data for transmission (write) and reception
(read).
*PCON Register**: Contains a bit (SMOD) that affects baud rate in certain modes.
*TI (Transmit Interrupt)** and **RI (Receive Interrupt)** bits in the SCON register
indicate completion of transmission and reception respectively.

# Synchronous vs. Asynchronous Serial Communication

# Setting Baud Rate in 8051

Baud rate in 8051 is determined by:
1. **Timer 1 (usually in mode 2 – 8-bit auto-reload)** is used to generate baud
rate.
2. **TH1** (Timer 1 high byte) is loaded with a value to determine baud rate.
3. **SMOD bit in PCON register** doubles the baud rate if set.

# Baud Rate Formula:

In Mode 1 or Mode 3:
Baud Rate = (2^SMOD / 32) × (Timer 1 overflow rate)
= (2^SMOD / 32) × (oscillator frequency) / (12 × [256 – TH1])

# Serial Port Modes in 8051

The serial port can operate in **4 modes**, defined by bits **SM0** and
**SM1** in the SCON register.
**Explanation:**
*Mode 0**: Uses RxD for both input/output. TxD outputs the shift clock.
*Mode 1**: Standard UART mode with 10-bit frame (1 start, 8 data, 1 stop).
*Mode 2**: Includes an extra 9th bit (for multiprocessor communication). Baud
rate = fosc/64 or fosc/32 depending on SMOD.
*Mode 3**: Same as Mode 2 but with variable baud rate (using Timer 1).

b) Write a program in 8051 to transfer "A" serially at 4800 baud,

continuously XTAL = 11.0592 MHz.
Here’s how you can write an 8051 Assembly Language Program to continuously
transmit the character 'A' (ASCII 0x41) serially at 4800 baud, with a crystal
frequency of 11.0592 MHz**.

✅ Configuration Details:
*Baud Rate:** 4800
*XTAL:** 11.0592 MHz
*Serial Mode:** Mode 1 (8-bit UART, variable baud rate)
*Timer 1:** Used to generate baud rate (Mode 2 - 8-bit auto-reload)

✅ Baud Rate Calculation for 8051:

Baud Rate = (2^SMOD / 32) × (Timer 1 Overflow Rate)
Timer 1 Overflow Rate = XTAL / (12 × \[256 – TH1])
Assuming SMOD = 0,

So,
 ✅ Assembly Code (8051, Keil-style syntax):

✅ Explanation:
* `TMOD = 0x20` sets Timer 1 in Mode 2 (8-bit auto-reload).
* `TH1 = 0xFA` is calculated to give 4800 baud.
* `SCON = 0x50` sets serial mode 1 and enables receiver.
* `TR1` starts Timer 1.
* Character 'A' is moved to `SBUF`, then waits until transmission is complete (`TI`
set), clears `TI`, and repeats.

8.(a) Give the bit details of IE register used for programming with
interrupts in 8051.
In the **8051 microcontroller**, the **Interrupt Enable (IE) register**
is an **8-bit** register used to enable or disable interrupts. Each bit in
the IE register controls the enabling/disabling of specific interrupts.
IE Register Format (Bit-wise):

# Bit Details:
*EA (Bit 7)**:
Master control bit. If EA = 0, **no interrupt is enabled**, even if
other bits are set.
*EX0 (Bit 0)**:
Enables **External Interrupt 0** (INT0 pin).
*ET0 (Bit 1)**:
Enables **Timer 0 interrupt**.
*EX1 (Bit 2)**:
Enables **External Interrupt 1** (INT1 pin).
*ET1 (Bit 3)**:
Enables **Timer 1 interrupt**.
*ES (Bit 4)**:
Enables **Serial communication interrupt** (RI or TI flags).
*ET2 (Bit 5)**:
Enables **Timer 2 interrupt** (available only in 8052 or some 8051
derivatives).
*Bit 6**:
**Reserved/Unused**. Should be cleared to 0 to ensure
compatibility.

# Example:
If you want to enable only external interrupt 0 and timer 1 interrupt,
the IE register should be:
EA = 1 (global enable)
EX0 = 1
ET1 = 1
Other bits = 0
Binary: 1000 1001
Hex: 0x89

(b) Write about the number of interrupts in 8051. Explain with

example, the steps to service an interrupt.
The 8051 microcontroller handles 5 interrupt sources: two from Timer 0 and
Timer 1, two from external interrupts (INT0 and INT1), and one from serial
communication (RI/TI). Interrupts are signals that cause the 8051 to temporarily
stop its current execution and jump to a specific interrupt service routine (ISR) to
handle the event.
Here's a breakdown of the interrupt sources and the steps involved in servicing an
interrupt:

1. Interrupt Sources:
>Timer 0 (TF0): Generated when Timer 0 overflows (reaches its maximum value).
>Timer 1 (TF1): Generated when Timer 1 overflows.
>External Interrupt 0 (INT0): Triggers when a signal is received on the INT0 pin
(P3.2).
>External Interrupt 1 (INT1): Triggers when a signal is received on the INT1 pin
(P3.3).
>Serial Communication (RI/TI): Generated when the Serial port receive (RI) or
transmit (TI) flags are set.

2. Steps to Service an Interrupt:

1. Interrupt Request:
When an interrupt source generates a signal, the 8051 stops its current execution
and jumps to the interrupt service routine (ISR).

2. Save Context:
The 8051 saves the current state of the CPU, including the program counter (PC),
the status register, and any other relevant registers, onto the stack. This allows
the main program to be resumed later.

3. Jumping to the ISR:

The 8051 jumps to the address of the ISR corresponding to the triggered interrupt.

4. Executing the ISR:

The ISR is executed, which typically contains code to handle the specific interrupt
event. For example, an ISR for Timer 0 might update a counter or trigger a
peripheral action.

5. Return from Interrupt:

After the ISR is finished, the 8051 returns to the point where it was interrupted
using the RETI (Return from Interrupt) instruction.

6. Restore Context:
The CPU restores the saved context from the stack, allowing the main program to
continue execution from where it was interrupted.
Explanation:
>interrupt 0 tells the compiler this is the ISR for External Interrupt 0.
>IE = 0x81: Enables the global interrupt (EA) and EX0 (bit 0).
>IT0 = 1: Configures INT0 as edge-triggered (required for button press detection).