IC61LV2568

Document Title
256K x 8 Hight Speed SRAM with 3.3V

Revision History
Revision No History Draft Date Remark
0A Initial Draft September 12,2001

The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.

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IC61LV2568

256K x 8 HIGH-SPEED CMOS STATIC RAM

FEATURES DESCRIPTION
• High-speed access times: The ICSI IC61LV2568 is a very high-speed, low power,
— 8, 10, 12 and 15 ns 262,144-word by 8-bit COMS static RAM. The IC61LV2568 is
fabricated using ICSI's high-performance CMOS technology.
• High-preformance, lower-power CMOS process This highly reliable process coupled with innovative circuit
• Multiple center power and ground pins for design techniques, yields higher preformance and low power
greater noise immunity consumotion devices.
• Easy memory expansion with CE and OE
When CE is HIGH (deselected), the device assumes a standby
options mode at which the power dissipation can be reduced down to
• CE power-down 36 mW (max.) with CMOS input levels.
• CMOS power: 540 mW @ 10 ns
The IC61LV2568 operates from a single 3.3V power supply and
36 mW standby mode all inputs are TTL-compatible.
• TTL compatible inputs and outputs
• Single 3.3V ± 10% power supply The IC61LV2568 is available in 36-pin, 400mil SOJ and 44-pin
TSOP-2 package.
• Packages available:
— 36-pin 400mil SOJ
— 44-pin TSOP-2

FUNCTIONAL BLOCK DIAGRAM

256K X 8
A0-A17 DECODER MEMORY ARRAY

VCC
GND

I/O
I/O0-I/O7 DATA COLUMN I/O
CIRCUIT

CE
CONTROL
OE CIRCUIT
WE

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution, Inc.

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PIN CONFIGURATION PIN CONFIGURATION

36-Pin SOJ 44-Pin TSOP-2

A4 1 36 NC
NC 1 44 NC
A3 2 35 A5 NC 2 43 NC
A2 3 34 A6 A4 3 42 NC
A3 4 41 A5
A1 4 33 A7
A2 5 40 A6
A0 5 32 A8 A1 6 39 A7
CE 6 31 OE A0 7 38 A8
I/O0 7 30 I/O7 CE 8 37 OE
I/O0 9 36 I/O7
I/O1 8 29 I/O6 I/O1 10 35 I/O6
Vcc 9 28 GND Vcc 11 34 GND
GND 10 27 Vcc GND 12 33 Vcc
I/O2 13 32 I/O5
I/O2 11 26 I/O5
I/O3 14 31 I/O4
I/O3 12 25 I/O4 WE 15 30 A9
WE 13 24 A9 A17 16 29 A10
A17 14 23 A10 A16 17 28 A11
A15 18 27 A12
A16 15 22 A11 A14 19 26 NC
A15 16 21 A12 A13 20 25 NC
A14 17 20 NC NC 21 24 NC
NC 22 23 NC
A13 18 19 NC

PIN DESCRIPTIONS TRUTH TABLE

A0-A17 Address Inputs Mode WE CE OE I/O Operation Vcc Current
CE Chip Enable Input Not Selected X H X High-Z ISB1, ISB2
(Power-down)
OE Output Enable Input
Output Disabled H L H High-Z ICC
WE Write Enable Input Read H L L DOUT ICC
I/O0-I/O7 Input/Output Write L L X DIN ICC
Vcc Power
GND Ground
NC No Connection

ABSOLUTE MAXIMUM RATINGS(1)

Symbol Parameter Value Unit
VCC Power Supply Voltage Relative to GND –0.5 to +4.6 V
VTERM Terminal Voltage with Respect to GND –0.5 to Vcc + 0.5 V
TBIAS Temperature Under Bias Com. –10 to +85 °C
Ind. –45 to +90
TSTG Storage Temperature –65 to +150 °C
PD Power Dissipation 1 W
IOUT DC Output Current ±20 mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.

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OPERATING RANGE
Range Ambient Temperature VCC
Commercial 0°C to +70°C 3.3V ± 10%
Industrial –40°C to +85°C 3.3V ± 10%

DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 — V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA — 0.4 V
VIH Input HIGH Voltage 2.0 VCC + 0.3 V
VIL Input LOW Voltage(1) –0.3 0.8 V
ILI Input Leakage GND ≤ VIN ≤ VCC Com. –1 1 µA
Ind. –5 5
ILO Output Leakage GND ≤ VOUT ≤ VCC, Outputs Disabled Com. –1 1 µA
Ind. –5 5
Notes:
1. VIL (min.) = –0.3V (DC); VIL (min.) = –2.0V (pulse width ≤ 2.0 ns).
VIH (max.) = VCC + 0.3V (DC); VIH (max.) = Vcc + 2.0V (pulse width ≤ 2.0 ns).
2. The Vcc operating range for 8 ns is 3.3V +10%, -5%.

POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)

-8 ns -10 ns -12 ns -15 ns
Sym. Parameter Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit

ICC Vcc Dynamic Operating VCC = Max., CE = VIL Com. — 170 — 150 — 140 — 130 mA
Supply Current IOUT = 0 mA, f = fMAX Ind. — 180 — 160 — 150 — 140
ISB1 TTL Standby Current VCC = Max., Com. — 30 — 30 — 30 — 30 mA
(TTL Inputs) VIN = VIH or VIL Ind. — 40 — 40 — 40 — 40
CE ≥ VIH, f = 0
ISB2 CMOS Standby VCC = Max., Com. — 10 — 10 — 10 — 10 mA
Current (CMOS Inputs) CE ≤ VCC – 0.2V, Ind. — 15 — 15 — 15 — 15
VIN ≥ VCC – 0.2V, or
VIN ≤ 0.2V, f = 0
Notes:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

CAPACITANCE(1,2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Output Capacitance VOUT = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.

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READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-8 ns -10 ns -12 ns -15 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
tRC Read Cycle Time 8 — 10 — 12 — 15 — ns
tAA Address Access Time — 8 — 10 — 12 — 15 ns
tOHA Output Hold Time 3 — 3 — 3 — 3 — ns
tACE CE Access Time — 8 — 10 — 12 — 15 ns
tDOE OE Access Time — 3 — 4 — 5 — 6 ns
tLZOE(2) OE to Low-Z Output 0 — 0 — 0 — 0 — ns
tHZOE (2)
OE to High-Z Output 0 3 0 4 0 5 0 6 ns
tLZCE (2)
CE to Low-Z Output 3 — 3 — 3 — 3 — ns
tHZCE(2) CE to High-Z Output 0 3 0 4 0 5 0 6 ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V,
input pulse levels of 0 to 3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not
100% tested.

AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 3 ns
Input and Output Timing 1.5V
and Reference Levels
Output Load See Figures 1 and 2
Notes:
1. The Vcc operating range for 8 ns is 3.3V +10%, -5%.

AC TEST LOADS

319 Ω 319 Ω
3.3V 3.3V

OUTPUT OUTPUT

30 pF 353 Ω 5 pF 353 Ω
Including Including
jig and jig and
scope scope

Figure 1. Figure 2.

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AC WAVEFORMS

READ CYCLE NO. 1(1,2)

t RC
ADDRESS

t AA
t OHA t OHA

DOUT PREVIOUS DATA VALID DATA VALID

READ CYCLE NO. 2(1,3)

t RC

ADDRESS
t AA t OHA
OE

t DOE t HZOE
CE t LZOE
t ACE
t LZCE t HZCE
HIGH-Z
DOUT DATA VALID

Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.

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WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)

-8 ns -10 ns -12 ns -15 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
tWC Write Cycle Time 8 — 10 — 12 — 15 — ns
tSCE CE to Write End 7 — 8 — 9 — 10 — ns
tAW Address Setup Time 7 — 8 — 9 — 10 — ns
to Write End
tHA Address Hold 0 — 0 — 0 — 0 — ns
from Write End
tSA Address Setup Time 0 — 0 — 0 — 0 — ns
tPWE (4)
WE Pulse Width 7 — 8 — 9 — 10 — ns
tSD Data Setup to Write End 4.5 — 5 — 6 — 7 — ns
tHD Data Hold from Write End 0 — 0 — 0 — 0 — ns
tHZWE(3) WE LOW to High-Z Output — 3 — 4 — 5 — 6 ns
tLZWE (3)
WE HIGH to Low-Z Output 0 — 0 — 0 — 0 — ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse
levels of 0 to 3.0V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing
are referenced to the rising or falling edge of the signal that terminates the Write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100%
tested.
4.Tested with OE Hith.

AC WAVEFORMS
WRITE CYCLE NO. 1 (1,2 )(CE Controlled, OE is HIGH or LOW)

t WC

VALID ADDRESS
ADDRESS
t SA t SCE t HA
CE
t AW
t PWE1
WE t PWE2
t HZWE t LZWE
HIGH-Z
DOUT DATA UNDEFINED

t SD t HD
DIN DATAIN VALID

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WRITE CYCLE NO. 2 (WE Controlled, OE is HIGH During Write Cycle) (1,2)

t WC
ADDRESS VALID ADDRESS

t HA
OE

CE LOW

t AW
t PWE1
WE

t SA t HZWE t LZWE
HIGH-Z
DOUT DATA UNDEFINED

t SD t HD
DIN DATAIN VALID

WRITE CYCLE NO. 3 (WE Controlled, OE is LOW During Write Cycle) (1)

t WC
ADDRESS VALID ADDRESS

t HA
OE LOW

CE LOW
t AW
t PWE2
WE
t SA t HZWE t LZWE
HIGH-Z
DOUT DATA UNDEFINED

t SD t HD
DIN DATAIN VALID

Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE > VIH.

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ORDERING INFORMATION ORDERING INFORMATION

Commercial Range: 0°C to +70°C Industrial Range: –40°C to +85°C
Speed(ns) OrderPartNo. Package Speed(ns) OrderPartNo. Package
8 IC61LV2568-8T 400mil T SOP-2 8 IC61LV2568-8TI 400mil T SOP-2
IC61LV2568-8K 400mil SOJ IC61LV2568-8KI 400mil SOJ
10 IC61LV2568-10T 400mil T SOP-2 10 IC61LV2568-10TI 400mil T SOP-2
IC61LV2568-10K 400mil SOJ IC61LV2568-10KI 400mil SOJ
12 IC61LV2568-12T 400mil T SOP-2 12 IC61LV2568-12TI 400mil T SOP-2
IC61LV2568-12K 400mil SOJ IC61LV2568-12KI 400mil SOJ
15 IC61LV2568-15T 400mil T SOP-2 15 IC61LV2568-15TI 400mil T SOP-2
IC61LV2568-15K 400mil SOJ IC61LV2568-15KI 400mil SOJ

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http://www.icsi.com.tw
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