Evaluate the arithmetic statement X = (A + B)*(C + D)using a general register computer with

three address, two address and one address instruction format a program to evaluate the
expression.

Or

What is General Register Organization

A set of flip-flops forms a register. A register is a unique high-speed storage area in the CPU.
They include combinational circuits that implement data processing. The information is always
defined in a register before processing. The registers speed up the implementation of programs.

Registers implement two important functions in the CPU operation are as follows −

 It can support a temporary storage location for data. This supports the directly
implementing programs to have fast access to the data if required.

 It can save the status of the CPU and data about the directly implementing program.

Example − Address of the next program instruction, signals get from the external devices and
error messages, and including different data is saved in the registers.

If a CPU includes some registers, therefore a common bus can link these registers. A general
organization of seven CPU registers is displayed in the figure.
The CPU bus system is managed by the control unit. The control unit explicit the data flow
through the ALU by choosing the function of the ALU and components of the system.

Consider R1 ← R2 + R3, the following are the functions implemented within the CPU −

MUX A Selector (SELA) − It can place R2 into bus A.

MUX B Selector (SELB) − It can place R3 into bus B.

ALU Operation Selector (OPR) − It can select the arithmetic addition (ADD).

Decoder Destination Selector (SELD) − It can transfers the result into R1.

The multiplexers of 3-state gates are performed with the buses. The state of 14 binary selection
inputs determines the control word. The 14-bit control word defines a micro-operation.

The encoding of register selection fields is specified in the table.

Binary Code SELA SELB SELD

000 Input Input None

001 R1 R1 R1

010 R2 R2 R2

011 R3 R3 R3

100 R4 R4 R4

101 R5 R5 R5

110 R6 R6 R6

111 R7 R7 R7
OPR Select Operation Symbol

00000 Transfer A TSFA

00001 Increment A INCA

00010 Add A + B ADD

00101 Subtract A - B SUB

00110 Decrement A DECA

01000 ADD A and B AND

01010 OR A and B OR

01100 XOR A and B XOR

01110 Complement A COMA

10000 Shift right A SHRA

11000 Shift left A SHLA

Encoding of Register Selection Field

There are several micro-operations are implemented by the ALU. Few of the operations
implemented by the ALU are displayed in the table.

Encoding of ALU Operations

There are some ALU micro-operations are shown in the table.

ALU Micro-Operations

Micro-operation SELA SELB SELD OPR Control Word

R1 ← R2 – R3 R2 R3 R1 SUB 010 011 001 00101

R4 ← R4 ∨ R5 R4 R5 R4 OR 100 101 100 01010

 R6 ← R6 + R1 - R6 R1 INCA 110 000 110 00001

R7 ← R1 R1 - R7 TSFA 001 000 111 00000

Output ← R2 R2 – None TSFA 010 000 000 00000

Output ← Input Input - None TSFA 000 000 000 00000

R4 ← shl R4 R4 - R4 SHLA 100 000 100 11000

R5 ← 0 R5 R5 R5 XOR 101 101 101 01100

Three address instruction :

Two address instruction :

One address instruction :

What is stack ? Give the organization of register stack with all necessary elements and explain
the working of push and pop operations.

A stack is a data structure that follows the Last-In-First-Out (LIFO) principle, meaning the last
element added to the stack is the first one to be removed. Imagine it like a stack of plates,
where you can only add or remove plates from the top of the stack.

In the organization of a register stack you provided, there are four main components:

1. Stack Pointer (SP): This register holds the address of the top of the stack. It’s like a
pointer indicating where the next item will be added or removed.

2. FULL register: This register indicates whether the stack is full or not. If it’s set to 1, the
stack is full.

3. EMPTY register: This register indicates whether the stack is empty or not. If it’s set to 1,
the stack is empty.

4. Data Register (DR): This register holds the data to be pushed onto the stack or the data
popped off from the stack.
Now, let’s explain the PUSH and POP operations:

PUSH Operation:

 First, you check if the stack is not full (i.e., if FULL = 0).

 If the stack is not full, you increment the Stack Pointer (SP) to move it to the next
available position.

 Then, you write the data from the Data Register (DR) into the memory location pointed
to by the Stack Pointer (SP).

 After that, you check if the stack is full now. If the Stack Pointer (SP) reaches its
maximum value (e.g., 63 in this case), you set the FULL register to 1 to mark the stack as
full.

 Finally, you set the EMPTY register to 0 to indicate that the stack is not empty anymore.

POP Operation:

 First, you check if the stack is not empty (i.e., if EMPTY = 0).

 If the stack is not empty, you read the data from the memory location pointed to by the
Stack Pointer (SP) into the Data Register (DR).

 Then, you decrement the Stack Pointer (SP) to move it to the previous position.

 After that, you check if the stack is empty now. If the Stack Pointer (SP) reaches 0, you
set the EMPTY register to 1 to mark the stack as empty.

 Finally, you set the FULL register to 0 to indicate that the stack is not full anymore.

What is the stack organization ? Compare register stackand memory stack.

Stack organization:

Stack Organization: A stack is a data structure that follows the Last In, First Out (LIFO) principle,
meaning the last item added to the stack is the first one to be removed. Stack organization
refers to how data is managed and accessed in a computer’s memory using a stack.

Register Stack: In a register stack, the stack operations are performed using registers, which are
small, fast storage locations within the CPU. These registers are part of the CPU itself and are
 used for storing temporary data and for performing arithmetic and logical operations. Register
stacks are extremely fast because registers are directly accessible by the CPU. However, they
typically have limited capacity since there are only a few registers available.

Memory Stack: In a memory stack, the stack operations are performed using memory locations.
When data is pushed onto the stack, it is stored in the computer’s RAM (Random Access
Memory), and when data is popped off the stack, it is removed from RAM. Memory stacks are
slower compared to register stacks because accessing memory takes more time than accessing
registers. However, memory stacks can hold a larger amount of data since RAM typically has
more storage capacity compared to CPU registers.

Comparison between register stack and memory stack :

Register
Aspect Memory Stack
Stack

Faster
because
registers are
Speed Slower because it involves accessing RAM
located
within the
CPU

Limited
capacity due
Capacity to a few Larger capacity since RAM has more storage space
registers
available

Directly
Accessibility accessible by Involves accessing RAM, which takes more time
the CPU

Used for
storing
Usage Typically used for managing function calls, local variables, and program execution
frequently
accessed data
Write short note on relative addressing mode and indirect addressing mode. OR Explain the
following addressing modes with the help of an example each :i. Direct ii. Register indirect iii.
Implied iv. Immediate v. Indexed

Addressing modes in computer architecture determine how instructions specify the operands
they operate on. Let’s break down each addressing mode with simpler explanations and
examples:

1. Direct Addressing:

 Explanation: In direct addressing, the operand’s address is directly specified in

the instruction.

 Example: LOAD 500 means load the value from memory address 500 into a
register.

2. Register Indirect Addressing:

 Explanation: The instruction contains the address of a register whose content is
the effective address of the operand.
 Example: LOAD (R1) means load the value from the memory address stored in
register R1 into a register.
3. Implied Addressing:
 Explanation: Operand is implied by the instruction itself, often used for
operations where operands are known.
 Example: INCREMENT without specifying any operand directly implies to
increment the value in a specific register.
4. Immediate Addressing:
 Explanation: The operand’s value is directly specified within the
instruction.
 Example: ADD #10 means add the immediate value 10 to the
content of a register.

5. Indexed Addressing:
 Explanation: The effective address is generated by adding a
constant value to the contents of a register (index).
 Example: LOAD 600(R2) means load the value from memory
address calculated by adding 600 to the content of register R2.
Write a short note on RISC. OR What is RISC ? Explain its various characteristics.
RISC, which stands for Reduced Instruction Set Computer, is a type of processor architecture
that emphasizes simplicity and efficiency in instruction execution.RISC architectures use a set of
simple and basic instructions. These instructions are designed to perform specific operations,
making the processor’s instruction set straightforward and easy to understand.RISC processors
typically support a few simple data types. Instead of dealing with a wide variety of complex data
types, RISC focuses on efficiently handling basic data types and allows for the synthesis of more
complex data types through simple instructions.
Characteristics:
1. Simplicity: RISC processors use a small and straightforward set of instructions, making
the architecture simple and easy to understand.
2. Single Clock Cycle Execution: Each instruction in RISC typically executes in a single clock
cycle, leading to faster overall performance.
3. Limited Instruction Set: RISC architectures focus on reducing the number of instructions,
emphasizing the execution of simple and specific operations.
4. Fixed-Length Instructions: Instructions in RISC have a fixed length, aiding in efficient
pipelining and simplifying the decoding process.
5. Register Emphasis: RISC processors often have a large number of general-purpose
registers, allowing for efficient data access and manipulation.
6. Load/Store Architecture: RISC commonly follows a load/store model, where data is
loaded from memory into registers for processing and then stored back in memory.
7. Compiler-Friendly: RISC architectures are designed to be compiler-friendly, enabling
compilers to easily optimize and schedule instructions for efficient execution.
8. Focus on Performance: RISC architectures aim to achieve high performance by reducing
instruction complexity, enabling faster clock rates, and emphasizing parallelism.
 Differentiate between RISC & CISC based microprocessor. OR Differentiate between complex
instruction set computer and reduced instruction set computer.
RISC (Reduced Instruction Set
Feature CISC (Complex Instruction Set Computer)
Computer)

Instruction Set
Fewer instructions, simpler operations More instructions, complex operations
Complexity

Instruction Length Fixed length Variable length

Pipeline Architecture Typically deeper pipelines Shallower pipelines

Clock Cycle Short, uniform clock cycles Variable length clock cycles

Registers More general-purpose registers Fewer general-purpose registers

Memory Access Emphasis on load/store architecture Instructions may operate on memory directly

Code Size Larger code size due to simplicity Smaller code size due to complex instructions

Execution Speed Faster for specific tasks Variable, as some instructions may take multiple cycles

Hardware Complexity Simpler hardware design More complex hardware design

Power Consumption Generally lower power consumption Can have higher power consumption

Example Architectures ARM, MIPS x86, x86-64 (Intel and AMD architectures)
 What is difference between implied and immediate addressing modes ? Explain with an
example.
Immediate
Aspect Implied Addressing Mode
Addressing Mode

Operand value is directly specified

Definition Operand or operation is implied by the instruction itself.
within the instruction.

Operand is a constant or an immediate

Operand No explicit operand is required; the instruction itself dictates the operation.
value.

LDA #10 loads the accumulator with the

Example CLC clears the carry flag.
immediate value 10.

Suitable for instructions where the

Usage operand is known beforehand or is a Typically used for instructions that perform operations without needing additional
constant value.

Operand Operand value is included within the

No additional operand storage is needed; instruction itself defines the operation.
Storage instruction.

Memory Operand value doesn’t require fetching

No memory access needed for operand retrieval.
Access from memory.

Explain general-purpose register based organization.

1. Registers: Imagine registers as small storage spaces inside the computer’s processor,
similar to tiny drawers where it can keep some information handy. In this setup, we have
seven of these registers named R1, R2, R3, and so on up to R7.
2. Communication: These registers don’t just sit idle; they talk to each other. They can pass
information back and forth, kind of like passing notes in class. But they also talk to other
parts of the processor.
3. ALU (Arithmetic Logic Unit): Think of this as the brain of the processor. It’s responsible
for doing all the math and logic operations. It’s like the part of your brain that solves
puzzles and does calculations.
4. Multiplexers (MUXs): These are like traffic directors. They help in selecting which
register’s information should go where. They make sure data goes where it’s needed at
the right time.
5. Select Lines: These are like remote controls for the registers. They decide which
register’s data should be sent to the ALU for processing.
6. Buses A and B: These are like highways that connect different parts of the processor.
They allow data to flow between the registers and the ALU.
7. Operation Selection: This is where you tell the ALU what kind of math or logic to do. It’s
like choosing whether you want to add, subtract, or compare two numbers.
8. Micro-Operation Result: After the ALU does its work, it produces a result. This result can
be sent back to the registers to be stored or used elsewhere.
 9. Destination Register: Finally, the result needs to go somewhere. A decoder helps decide
which register should receive the result.

What is pipelining ? How the idea of pipelining used ina computer ?OR Write a short
note on pipelining.

1.Pipelining is a technique of decomposing a sequential process into sub-operations, with each

sub-process being executed in a special
dedicated segment that operates concurrently with all other segments.
2. The processor executes a program by fetching and executing instructions, one after the other.
3.Let Fi and Ei refer to the fetch and execute steps for instruction Ii.
4.Execution of a program consists of a sequence of fetch and execute steps as shows is Fig. (A)

The instruction fetched by the fetch unit is deposited in an intermediated storage buffer Bi.
The results of execution are deposited in the destination location specified by the instructions.

For these purposes, we assume that both the source and destination of the data operated in by
the instructions are inside the block labelled “Execution unit”.

The computer is controlled by a clock whose period is such that the fetch and execute steps of
any instruction can be completed in one clock cycle.
 Operation of the computer proceeds as in Fig. (C).

In the first clock cycle, the fetch unit fetches an instruction I 1(step F1) and stores it in buffer Bi at
the end of the clock cycle.
In the second clock cycle, the instruction fetch unit proceeds with the fetch operation for
instruction I2 (Step F2). Meanwhile, the execution unit performs the operation specified by the
instruction I1, which is available to it in buffer Bi(Step E1). By the end of the second clock cycle,
the execution of instruction I1 is completed and instruction I2 is available.
Instruction I2 is stored in Bi by replacing I1, which is no longer needed. Step E2 is performed by
the execution unit during the third clock cycle, while instruction I 3 is being fetched by the fetch
unit. In this manner, both fetch and execute units are kept busy all the time.

Differentiate between linear and non-linear pipeline.

Feature Linear Pipeline Non-linear Pipeline

Flow of Sequential flow, step-by-step

Parallel or branching flow, multiple paths.
Execution progression.

Dependency Each step depends on the previous one. Steps may be independent or have dependencies.

Flexibility Less flexible, fixed order of execution. More flexible, allows for dynamic sequencing.

Parallelism Limited parallelism, one step at a time. Enables parallel execution of multiple steps.

Generally simpler and easier to

Complexity Can be more complex due to diverse paths.
understand.
Feature Linear Pipeline Non-linear Pipeline

Well-suited for straightforward

Use Cases Suitable for complex, interconnected tasks.
processes.

Examples Linear data processing, assembly line. Software development, decision trees.