SESHAM RAMAKRISHNA www.siliconsys.
in
Email id: ramakrishna.sesham1@gmail.com
Mobile no: 9052891288
OBJECTIVE
My objective is to acquire a good and challenging position in professional organization in
the field of Electronics. So that I can enhance my practical knowledge and offer an effective
support for the development of the organization. Therefore I foresee to work for an
organization that mentors and enhances my skills to become a good and strong professional.
PROFESSIONAL TRAINING
An Industry Oriented Trainee in VLSI PHYSICAL DESIGN from Institute of Silicon Systems Pvt Ltd.,
Hyderabad since December 2017 to till May 2018
Course outline:
VLSI Fundamentals, CMOS Basics, Digital Design Floor Planning, Power Planning, Placement and
Routing, clock tree synthesis, static timing analysis timing optimization, cross talk analysis, IR
Drop Analysis and Physical Verification.
Tools:
Experience in physical design of 130nm and 90nm technologies using Cadence tool
Cadence SOC Encounter –Floor Planning, Place & Route, and clock tree synthesis
Encounter Timing System –Static Timing Analysis and Crosstalk Analysis
RTL Compiler- Logic Synthesis
Assura – Physical Verification
Cadence Virtuoso–Analog Layout
ACADEMIC EDUCATION
B. Tech in Electrical and Electronics Eng. From Brilliant Group Of Technical Institutions,
Hyderabad, affiliated to JNTU Hyderabad with 66.8% in 2015.
Diploma in EEE from C.R Polytechnic College, affiliated to State Board of Technical
Education and Training, A.P with 75.08% in 2012.
S.S.C from Z. P High School, Telukutla affiliated to Board of Secondary Education, A.P
with 64.33% in 2008.
SOFTWARE EXPOSURE
Operating system : Windows, Linux, UNIX
Languages : C, VHDL.
Scripting Languages : TCL (Basics)
SESHAM RAMAKRISHNA www.siliconsys.in
Email id: ramakrishna.sesham1@gmail.com
Mobile no: 9052891288
PROJECTS
Project1
Name: ISS_WRAPPER
Objective : Timing Driven Layout
Tools : SOC Encounter, ETS.
Gate count/Area : 2, 95,935/ 1062025.81 um^2
Macros /STD Cells : 12/27096
No. of Clocks : 17
Frequency : 200MHz
Technology/Layers : TSMC 0.13 micron/5 Metal Layers
Role: Performing sanity check, Design import , Floor Plan , Power Plan , Placement , Trail Route,
Power Analysis, RC Extract, Timing Analysis, IPO, CTS, Adding filler cells, Timing Analysis.
Project2
Name: PCI_DATA
Objective : Timing Driven Layout
Tools : SOC Encounter, ETS.
Gate count : 1, 18,676
Blocks /Cells /IOs : 12/24450/120
No. of Clocks : 4
Frequency : 150 MHz
Technology : TSMC 0.18 micron
Role: Performing sanity check , Design import , Floor Plan , Power Plan , Placement , Trail
Route , Power Analysis, RC Extract , Timing analysis , IPO , CTS , Adding Filler Cells , Timing
analysis.
Project 3
Name: COUNTER_32
Tools : SOC Encounter & ETS
Gate count : 508
No. of Clocks : 1
Frequency : 200 MHz
Technology : TSMC 0.18 micron
Role: Performing sanity check , Design import , Floor Plan , Power Plan , Placement , Trail Route
Power Analysis, RC Extract , Timing analysis , IPO , CTS , Adding Filler Cells , Timing analysis.
SESHAM RAMAKRISHNA www.siliconsys.in
Email id: ramakrishna.sesham1@gmail.com
Mobile no: 9052891288
Logic Synthesis
Project1
Name: COUNTER_16
Objective : Running Zero and Force Wire Load Model Synthesis by
meeting Timing, optimizing Area and Power
Tools : Cadence Encounter RTL Compiler
No. of Clocks : 2
Frequency : 200MHz
Technology : TSMC 0.18 micron
Role : Writing SDC, TCL Scripts, Extracting Timing, Optimizing
Area, Timing and Power
Project2
Name: COUNTER_32
Objective : Running Zero and Force Wire Load Model Synthesis by
meeting Timing, optimizing Area and Power
Tools : Cadence Encounter RTL Compiler
No. of Clocks : 1
Frequency : 645MHz (RVT), 322MHz (HVT), 645MHz (MVT)
Technology : TSMC 0.18 micron
Role : Writing SDC, TCL Scripts, Extracting Timing, Optimizing
Area, Timing and Power
STANDARD CELLS LAYOUT DESIGN
Tools Used : Virtuoso Layout Editor (Designing Layouts), Assura
(Physical Verification)
Cells Designed : INVERTER, NAND, NOR, AND, OR, EX-OR, EX-NOR, MUX
Technology : TSMC 0.18 micron
Role : Designing Layouts and Verifying DRC and LVS checks.
Challenges : Routing with single metal layer by given metal pitch and
Half DRC rule
B-TECH PROJECT
Excitation Of Synchronous Wind Power Generators With Maximum Power Tracking Schme
DESCRIPTION : This excitation synchronous wind power generator (ESWPG) with a maximum
power tracking scheme. The excitation synchronous generator and servo motor rotor speed
tracks the gridfrequency and phase using the proposed coaxial configuration and phase
tracking technologies. The proposed maximum power tracking scheme governs the exciter
current to achieve stable
SESHAM RAMAKRISHNA www.siliconsys.in
Email id: ramakrishna.sesham1@gmail.com
Mobile no: 9052891288
PERSONAL STRENGTHS
Ability to rapidly build relationship and set up trust.
Confident and Determined
Ability to cope up with different situations.
PERSONAL DETAILS
Father’s Name : Mr. S. Narasimha Rao
Date of Birth : 10-06-1993
Languages Known : English and Telugu
Ph. no : 91-9052891288
DECLARATION:
I S. Rma krishna do hereby confirm that the information given above is true to
the best of my knowledge.
Date :
Place : Hyderabad (S. Rama Krishna)
