=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : M_8bit_Four_Alphabet_MAN.ngr
Top Level Output File Name : M_8bit_Four_Alphabet_MAN
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : No
Design Statistics
# IOs : 50
Cell Usage :
# BELS : 365
# GND :1
# LUT2 : 24
# LUT3 : 62
# LUT4 : 89
# MUXCY : 81
# MUXF5 : 19
# VCC :1
# XORCY : 88
# IO Buffers : 50
# IBUF : 18
# OBUF : 32
# MULTs :2
# MULT18X18 :2
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s5000fg1156-4
Number of Slices: 101 out of 33280 0%
Number of 4 input LUTs: 175 out of 66560 0%
Number of IOs: 50
Number of bonded IOBs: 50 out of 784 6%
Number of MULT18X18s: 2 out of 104 1%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
No clock signals found in this design
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 30.069ns
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 3585711 / 20
-------------------------------------------------------------------------
Delay: 30.069ns (Levels of Logic = 26)
Source: X<0> (PAD)
Destination: Yn_Out<19> (PAD)
Data Path: X<0> to Yn_Out<19>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 7 0.821 1.405 X_0_IBUF (X_0_IBUF)
LUT3:I0->O 3 0.551 1.102 M0/Mmult_Out2_mult0000_Madd_xor<3>111 (N3)
LUT4:I1->O 4 0.551 1.256 M0/Mmult_Out2_mult0000_Madd_xor<5>12 (N4)
LUT3:I0->O 1 0.551 0.869 M0/Mmux_Out821_SW1 (N22)
LUT4:I2->O 1 0.551 0.000 M0/Mmux_Out859_SW02 (M0/Mmux_Out859_SW01)
MUXF5:I0->O 1 0.360 0.996 M0/Mmux_Out859_SW0_f5 (N18)
LUT4:I1->O 12 0.551 1.457 M0/Mmux_Out859 (XX<9>)
LUT3:I0->O 1 0.551 0.000 M1/Madd_old_P_2_addsub0000_lut<10>
(M1/Madd_old_P_2_addsub0000_lut<10>)
MUXCY:S->O 1 0.500 0.000 M1/Madd_old_P_2_addsub0000_cy<10>
(M1/Madd_old_P_2_addsub0000_cy<10>)
XORCY:CI->O 3 0.904 0.975 M1/Madd_old_P_2_addsub0000_xor<11>
(M1/old_P_2_addsub0000<11>)
LUT3:I2->O 1 0.551 0.000 M1/Madd_old_P_3_addsub0000_lut<11>
(M1/Madd_old_P_3_addsub0000_lut<11>)
MUXCY:S->O 1 0.500 0.000 M1/Madd_old_P_3_addsub0000_cy<11>
(M1/Madd_old_P_3_addsub0000_cy<11>)
XORCY:CI->O 2 0.904 1.072 M1/Madd_old_P_3_addsub0000_xor<12>
(M1/old_P_3_addsub0000<12>)
LUT4:I1->O 1 0.551 0.000 M1/Madd_P_addsub0000_lut<12>
(M1/Madd_P_addsub0000_lut<12>)
MUXCY:S->O 1 0.500 0.000 M1/Madd_P_addsub0000_cy<12>
(M1/Madd_P_addsub0000_cy<12>)
MUXCY:CI->O 0 0.064 0.000 M1/Madd_P_addsub0000_cy<13>
(M1/Madd_P_addsub0000_cy<13>)
XORCY:CI->O 1 0.904 0.996 M1/Madd_P_addsub0000_xor<14> (M1/P_addsub0000<14>)
LUT2:I1->O 1 0.551 0.869 M1/P<14>1 (P1<14>)
LUT4:I2->O 1 0.551 0.000 Madd_Yn_Out_lut<14> (Madd_Yn_Out_lut<14>)
MUXCY:S->O 1 0.500 0.000 Madd_Yn_Out_cy<14> (Madd_Yn_Out_cy<14>)
MUXCY:CI->O 1 0.064 0.000 Madd_Yn_Out_cy<15> (Madd_Yn_Out_cy<15>)
MUXCY:CI->O 1 0.064 0.000 Madd_Yn_Out_cy<16> (Madd_Yn_Out_cy<16>)
MUXCY:CI->O 1 0.064 0.000 Madd_Yn_Out_cy<17> (Madd_Yn_Out_cy<17>)
MUXCY:CI->O 0 0.064 0.000 Madd_Yn_Out_cy<18> (Madd_Yn_Out_cy<18>)
XORCY:CI->O 1 0.904 0.801 Madd_Yn_Out_xor<19> (Yn_Out_19_OBUF)
OBUF:I->O 5.644 Yn_Out_19_OBUF (Yn_Out<19>)
----------------------------------------
Total 30.069ns (18.271ns logic, 11.798ns route)
(60.8% logic, 39.2% route)
=========================================================================
Total REAL time to Xst completion: 3.00 secs
Total CPU time to Xst completion: 3.61 secs
-->
Total memory usage is 241896 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 1 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
