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SystemVerilog Language and

Application
SystemVerilog for Verification
Version 9.2
Lecture Manual November 6, 2009
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Table of Contents SystemVerilog for Verification

Table of Contents

SystemVerilog Language and Application: SystemVerilog for Verification

___________________________________________________________________________

Chapter 1 SystemVerilog Verification Overview .............................................................. 8

SystemVerilog Introduction ....................................................................................................................... 9

SystemVerilog Language Extensions ....................................................................................................... 10

SystemVerilog Segmentation .................................................................................................................... 11

SystemVerilog Verification Building Blocks ........................................................................................... 12

Key Verification Features ......................................................................................................................... 13

Chapter 2 Simple Verification Features .......................................................................... 19

Strings ........................................................................................................................................................ 21

String Operators ....................................................................................................................................... 22

String Methods .......................................................................................................................................... 23

Time Literals ............................................................................................................................................. 25

Immediate Assertions ............................................................................................................................... 27

Action Blocks ............................................................................................................................................. 28

Severity Levels ........................................................................................................................................... 29

Immediate and Concurrent Assertions ................................................................................................... 31

Parallel Block Enhancements: join_any, join_none ............................................................................... 32

Process Control: disable fork, wait fork ................................................................................................. 33

Fine-Grain Process Control ..................................................................................................................... 34

Design Features in Verification ................................................................................................................ 35

Unions ........................................................................................................................................................ 36

Chapter 3 Verification Blocks .......................................................................................... 40

Verilog Event Scheduler ........................................................................................................................... 42

SystemVerilog Event Scheduler ............................................................................................................... 43

Programs: program .................................................................................................................................. 44

Final Blocks: final ...................................................................................................................................... 45

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Clocking Blocks: clocking.......................................................................................................................... 46

Clocking Block Syntax .............................................................................................................................. 47

Input and Output Skews ........................................................................................................................... 48

Multiple and Default Clocking Blocks ..................................................................................................... 51

Accessing a Clocking Block Signal ........................................................................................................... 52

Cycle Delay and Synchronous Drive ........................................................................................................ 53

Hierarchical Expressions .......................................................................................................................... 54

Chapter 4 Transaction Level Modeling (TLM) ................................................................ 58

What is a Transaction? ............................................................................................................................. 60

What is Transaction Based Verification? ................................................................................................ 61

Transactor Structure ................................................................................................................................ 62

Simple Transactor Using Interfaces ........................................................................................................ 63

Driving Transactor from Program Block ............................................................................................... 64

Utilizing a Modport ................................................................................................................................... 65

Utilizing a Clocking Block ........................................................................................................................ 66

Virtual Interfaces ...................................................................................................................................... 67

Benefits of TBV .......................................................................................................................................... 69

Chapter 5 Classes ............................................................................................................ 73

Class Overview .......................................................................................................................................... 75

Variables of the Class Type ...................................................................................................................... 76

Class Handles are “Safe” Pointers ........................................................................................................... 77

Class Properties and Methods .................................................................................................................. 78

Class versus Structure ............................................................................................................................... 79

External Method Definition ...................................................................................................................... 80

Class Constructor ...................................................................................................................................... 81

Static Properties ........................................................................................................................................ 83

Static Methods ........................................................................................................................................... 84

Current Object Handle: this .................................................................................................................... 85

Properties of a Class Type ........................................................................................................................ 86

Aggregation and Inheritance .................................................................................................................... 87

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Table of Contents SystemVerilog for Verification

Data Encapsulation (Hiding) .................................................................................................................... 91

Virtual Classes and Virtual Methods ...................................................................................................... 92

Virtual Methods and Polymorphism ....................................................................................................... 93

Class Parameters ....................................................................................................................................... 94

Chapter 6 Random Stimulus ........................................................................................... 98

CPU Coverage Testcase .......................................................................................................................... 100

CPU Instruction Stimulus ...................................................................................................................... 101

Looped CPU Instruction Stimulus ......................................................................................................... 102

Looped Stimulus Coverage Analysis ..................................................................................................... 103

Randomization and Constraints ............................................................................................................ 104

Pseudo-Random Number Generators ................................................................................................... 105

Unsigned Random Numbers .................................................................................................................. 106

Randomizing Scope Variables ............................................................................................................... 107

Random Stability ..................................................................................................................................... 108

Setting the Random Seed ........................................................................................................................ 109

Constraint Blocks .................................................................................................................................... 111

Random Weighted Case: randcase ........................................................................................................ 113

Random Sequence Generation: randsequence ..................................................................................... 114

Random Production Weights ................................................................................................................. 115

Production Statements: case, if-else, repeat .......................................................................................... 116

Aborting Productions: break, return .................................................................................................... 117

Passing Values Between Productions .................................................................................................... 118

Chapter 7 Class-Based Random Stimulus ................................................................... 122

Random Class Properties ....................................................................................................................... 124

Randomizing Class Objects: randomize() ............................................................................................. 125

pre_randomize() and post_randomize() ................................................................................................ 126

In-Line Random Variable Control ........................................................................................................ 128

Controlling Randomization: rand_mode() ........................................................................................... 129

Constraint Blocks .................................................................................................................................... 131

Constraint Block Inheritance ................................................................................................................. 133

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SystemVerilog for Verification Table of Contents

Constraint Expressions: Set Membership ............................................................................................. 133

Constraint Expressions: Weighted Distributions ................................................................................. 134

Constraint Expressions: Conditional Constraints ................................................................................ 135

Constraint Expressions: Iterative Constraints ..................................................................................... 136

Ordering the Constraint Solution .......................................................................................................... 137

Controlling Constraints: constraint_mode() ......................................................................................... 138

Setting the Random Seed: srandom() .................................................................................................... 140

Chapter 8 Covergroup Coverage .................................................................................. 144

Structural and Functional Coverage ..................................................................................................... 146

Two Kinds of Functional Coverage ....................................................................................................... 147

Data-Oriented Functional Coverage ...................................................................................................... 148

Defining a Coverage Model .................................................................................................................... 149

Automatic Bins ........................................................................................................................................ 150

Explicit Bins ............................................................................................................................................. 151

Explicit Scalar and Vector Bins ............................................................................................................. 152

Cross Coverage ........................................................................................................................................ 155

Automatic Cross Bins .............................................................................................................................. 156

Explicit Cross Bins and Selections ......................................................................................................... 157

Illegal and Ignored Cross Bins ............................................................................................................... 158

Covergroup Options ................................................................................................................................ 159

Reference: Type-Specific type_option ................................................................................................... 160

Reference: Instance-Specific option ....................................................................................................... 161

Reference: Covergroup Methods ........................................................................................................... 162

Reference: Covergroup System Tasks & Functions ............................................................................. 163

Chapter 9 Queues and Dynamic and Associative Arrays ........................................... 167

Dynamic Arrays ....................................................................................................................................... 169

Associative Arrays ................................................................................................................................... 171

Associative Array Methods ..................................................................................................................... 172

Queues ...................................................................................................................................................... 175

Queue Methods ........................................................................................................................................ 176

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Table of Contents SystemVerilog for Verification

Array Manipulation Methods ................................................................................................................ 179

Reference: Array Locator Methods ....................................................................................................... 180

Reference: Array Ordering Methods .................................................................................................... 181

Reference: Array Reduction Methods ................................................................................................... 182

Chapter10 Interprocess Synchronization ..................................................................... 186

Non-Blocking Event Trigger: ->> ............................................................................................................ 188

Persistent Event Trigger: triggered ....................................................................................................... 190

Event Sequencing: wait_order ............................................................................................................... 191

Event Variables ....................................................................................................................................... 192

Merging Events ....................................................................................................................................... 193

Reclaiming Events ................................................................................................................................... 194

Mailboxes ................................................................................................................................................. 195

Mailbox Methods .................................................................................................................................... 196

Process Synchronization with a Mailbox .............................................................................................. 197

Typeless Mailbox ..................................................................................................................................... 198

Mailbox Parameters ................................................................................................................................ 199

Semaphores .............................................................................................................................................. 200

Semaphore Methods ............................................................................................................................... 201

Process Synchronization with a Semaphore ......................................................................................... 202

Chapter11 Direct Programming Interface (DPI) ............................................................ 206

The Verilog PLI ....................................................................................................................................... 208

The SystemVerilog DPI .......................................................................................................................... 209

DPI Characteristics ................................................................................................................................. 210

Data Type Mapping ................................................................................................................................ 211

Importing Tasks and Functions ............................................................................................................. 213

Warning: Data Type Compatibility ....................................................................................................... 214

Import Linkage Name ............................................................................................................................ 215

Aspects of Task and Function Import ................................................................................................... 216

Context Tasks and Functions ................................................................................................................. 217

Pure Functions ........................................................................................................................................ 218

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Exporting Tasks and Functions ............................................................................................................. 219

Export Linkage Name ............................................................................................................................. 220

Aspects of Task and Function Export ................................................................................................... 221

The Disable Handshake .......................................................................................................................... 223

Compilation ............................................................................................................................................. 226

Chapter12 Introduction to Assertion Based Verification ............................................. 230

What is an Assertion? ............................................................................................................................. 232

What is Assertion Based Verification (ABV)? ...................................................................................... 233

Who Writes Assertions and Why? ......................................................................................................... 237

Why Use Assertions? ............................................................................................................................... 238

Issues with Assertions ............................................................................................................................. 239

Chapter13 Introduction to SystemVerilog Assertions ................................................. 242

Concurrent Assertions ............................................................................................................................ 244

Concurrent Assertion Structure ............................................................................................................ 245

Creating a Simple Property .................................................................................................................... 246

Naming and Asserting the Property ...................................................................................................... 247

Clocking the Property ............................................................................................................................. 248

Input Sampling and Property Evaluation ............................................................................................. 249

Assertion Placement ................................................................................................................................ 251

Sequences ................................................................................................................................................. 252

Same Cycle Sequence Implication: |-> ................................................................................................... 253

Next Cycle Sequence Implication: |=> ................................................................................................... 254

Sequence Property Analysis ................................................................................................................... 255

Cycle Delay Repetition ............................................................................................................................ 256

Consecutive Sequence Repetition ........................................................................................................... 257

Consecutive Repetition with Ranges ...................................................................................................... 258

Further SVA Features ............................................................................................................................. 259

Chapter14 Conclusions and Next Steps ....................................................................... 262

What This Module Covered ................................................................................................................... 263

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What's Next? ........................................................................................................................................... 264

Additional Resources .............................................................................................................................. 265

Appx M2A Quiz Solutions ............................................................................................... 266

3. Verification Blocks .............................................................................................................................. 267

4. Transaction-Level Modeling .............................................................................................................. 268

5. Classes .................................................................................................................................................. 269

6. Random Stimulus ................................................................................................................................ 270

7. Class-Based Random Stimulus .......................................................................................................... 271

8. Coverage (question) ............................................................................................................................ 272

8. Coverage .............................................................................................................................................. 273

9. Arrays and Queues .............................................................................................................................. 274

10. Interprocess Synchronization .......................................................................................................... 275

11. Direct Programming Interface ......................................................................................................... 276

12. Assertion Based Verification ............................................................................................................ 277

13. SystemVerilog Assertions .................................................................................................................. 278

Index .............................................................................................................................. i

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SystemVerilog for Verification

Version 9.2

November 6, 2009

Welcome to the “SystemVerilog for Verification” module of the “SystemVerilog Language and
Application” training course. This is the second module of the three-part training course. This
module focuses on the SystemVerilog features that increase the productivity of verification
personnel.

SystemVerilog Language and Application 1

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Verification Module Introduction

November 6, 2009

This first chapter introduces the training materials: The topics, agenda, and some training materials
conventions.

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What’s Coming...

Training Objectives
 Introduce the SystemVerilog verification features

 Understand uses, advantages and any issues

Chapter Format
 Intro – Slides – Summary – Quiz – Lab

 Some earlier chapters do not have labs

Timing Options
 Real classroom: Coffee ... Breaks … Labs … Lunch …
 “Virtual” classroom: On your own – but don’t forget!
11/6/2009 SystemVerilog for Verification 3

This training module focuses on the SystemVerilog features that increase the productivity of
verification personnel. It covers the “nuts and bolts” of the features, and also contains helpful hints,
and warnings about potential support and usage issues.
At the end of all but the earliest chapters is a quiz. The quiz is not interactive. Please try to work
the quiz yourself before referring to solutions in the appendix. There is a lab associated with all but
the earliest chapters. Lab practice reinforces the features presented in the slides.
In a real classroom, the instructor and students to some extent negotiate the class timing. In a
“virtual” classroom you have a lot more control over this timing. For an optimal learning
experience, you should study each chapter and do its associated quiz and lab in one session without
significant interruption.

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Setting Your Expectations…

Focus is on the SystemVerilog constructs that target design verification
 Data Types
 Classes and object-oriented design
 Dynamic and associative arrays and queues

 New constructs and interfaces

 Programs and final and clocking blocks
 Interfaces used as transactors and virtual interfaces
 Direct Programming Interface (DPI)

 Features enabling advanced verification techniques

 Constrained randomization of scope and class variables
 Functional coverage with covergroups and property covers
 Introduction to SystemVerilog Assertions
 Interprocess synchronization with events, mailboxes and semaphores

Following the course...

 Several months “hands-on” work to become experienced
11/6/2009 SystemVerilog for Verification 4

This module focuses on the SystemVerilog features that increase the productivity of verification
personnel. Those features include:
 Dynamic data types, such as classes and various kinds of arrays;
 Programming constructs, such as programs and final blocks and clocking blocks;
 Advanced use of interfaces for transaction-based verification (TBV);
 The direct programming interface (DPI); and
 Advanced verification methodologies, such as constrained randomization, coverage, assertions
and interprocess synchronization.

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Stand-Alone Verification Module Agenda

Prerequisite Module: SystemVerilog for Design
Day 1 Day 3
1. SystemVerilog Overview 10. Interprocess Synchronization
2. Simple Verification Features 11. Direct Programming Interface (DPI)
3. Verification Blocks 12. Assertion Based Verification
4. Transaction Level Modeling 13. Introduction to SystemVerilog
Assertions (SVA)
5. SystemVerilog Classes
14. What Next?
Day 2 Appendix A
6. Random Stimulus Quiz Solutions
7. Class-based Randomization
8. Covergroup Coverage
9. Arrays and Queues

11/6/2009 SystemVerilog for Verification 5

The instructor-led version if this module follows the agenda you see here. For self-paced learning,
the agenda is an estimate of how much time you will need to complete the training.

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Condensed Five-Day Classroom Agenda

— SystemVerilog Language and Application —
Design Verification Module Assertion
Module Module
Day 1 Day 2 Day 3 Day 4 Day 5
Overview Overview Random Interprocess Introduction to Assertion Based
Stimulus Synchronization Verification (ABV)
Data Types Verification
Features Class-Based Direct Immediate Assertions
Procedures
Randomization Programming
Verification Simple Boolean Assertions
Operators Interface (DPI)
Blocks Coverage
Sequences
User-Defined Assertion-Based
Transaction- Arrays and
Data Types Verification Sequence Composition
Based Queues
Hierarchy & Verification SystemVerilog Advanced Features
Connectivity Assertions
Classes Coding Guidelines
Subroutines
Functional Coverage
Interfaces
Practical Application
Static Verification

11/6/2009 SystemVerilog for Verification 6

The “Design” module only briefly introduces the subroutine enhancements and interfaces. Those
features are more applicable to verification, so the “Verification” module explores them in greater
detail.
As the “Design” and “Assertions” modules each contain more material than you can comfortably
absorb in a day, your instructor can and should tailor this agenda to meet your actual needs.

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SystemVerilog Verification Overview

Chapter 1

November 6, 2009

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Aims and Topics

Aims
 To introduce the scope and purpose of SystemVerilog Verification
features

Topics
 What is SystemVerilog?

 Segmentation of the language

 Key features of the language for verification

11/6/2009 SystemVerilog for Verification 8

This chapter introduces the SystemVerilog scope, purpose, and features. It briefly describes what
SystemVerilog is, explains why it exists, and segments the language into easily adopted subsets. It
then briefly separately highlights some of the major features.

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SystemVerilog Introduction
Aim:
Unified hardware design, specification, and verification language

Realization:
Extends and adds to Verilog-2001 constructs …
 Extended data types  Random constraints

 Extended hierarchical constructs  Interprocess synchronization

 Extended operators  Cycle-based functionality (clocking)

 Extended procedural statements  Assertions

 Extended scheduling semantics  Interfaces

 Enhanced process control  Functional coverage

 Enhanced tasks and functions  Direct Programming Interface (DPI)

 OOP features (classes etc)  More …

11/6/2009 SystemVerilog for Verification 9

SystemVerilog is the IEEE Std 1800-2005 “IEEE Standard for SystemVerilog — Unified
Hardware Design, Specification, and Verification Language”.
SystemVerilog includes the IEEE Std 1364-2001 “IEEE Standard Verilog® Hardware Description
Language” by reference.
SystemVerilog makes it practical to more productively write readable and reusable code. For the
design engineer, SystemVerilog provides constructs with which to more concisely and correctly
describe hardware. For the verification engineer, SystemVerilog provides constructs with which to
use transaction, randomization, assertion and coverage methodologies.

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SystemVerilog Language Extensions

SystemVerilog IEEE 1800
Literals Arrays Classes Scheduling Processes Random Clocking Coverage Interfaces
integer packed method Observed always_comb rand/randc ##delay covergroup interface
logic unpacked constructor Re-active always_latch constraint coverpoint virtual
time slices static Re-inactive always_ff randomize() Programs cross modport
string dynamic this join_any solve before wildcard export
pattern associativeextends Statements always_latch dist with Assertions sequence import
queue super unique always_ff rand_mode assert bins
Types cast priority join_any constraint_mode assume illegal_bins DPI
logic Declarations local do while join_none $urandom cover export
bit const foreach wait fork $urandom_range property Hierarchy import
byte alias Operators return randcase sequence package context
shortint type assignment break Subroutines randsequence intersect import pure
int var wild equality continue static first_match nesting
longint tagged final automatic Synchronization throughout
shortreal overloading iff const ref semaphore within
void streaming void mailbox bind
Verilog-2001
ANSI C style ports standard file I/O (* attributes *) multi dimensional arrays
generate $value$plusargs configurations signed types
localparam `ifndef `elsif `line memory part selects automatic
constant functions @* variable part select ** (power operator)
Verilog-1995
modules $finish $fopen $fclose initial wire reg
parameters $display $write disable integer real +=*/
function/tasks $monitor events time %
always @ `define `ifdef `else wait # @ packed arrays >> <<
assign `include `timescale fork–join 2D memory

11/6/2009 SystemVerilog for Verification 10

The IEEE Std. 1364 standardized in 1995 what was previously the proprietary Verilog hardware
description language.
The 2001 update to the Verilog standard added several convenience features, still primarily
targeted at hardware design.
Accellera proposed an update to the Verilog standard that added many design convenience features
and more than tripled the verification features. This slide illustrates just how much SystemVerilog
adds to Verilog. To hopefully minimize confusion, Accellera requested and obtained the new IEEE
standard number 1800 for these new features. The SystemVerilog standard incorporates the Verilog
standard by reference – there is no such thing as “stand-alone” SystemVerilog.

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SystemVerilog Segmentation

C-Interfaces Object Oriented Verification Ext.

Direct Programming Interface Classes, inheritance, data hiding and encapsulation,
C Modules polymorphism, parameterized classes

Dynamic data and processes

Primary Verification Extensions
SystemVerilog Assertions Increase Verification Efficiency!
Randomization and Constraints
Coverage
Design Subset
Language Constructs
Static Data Types Express more with less code!
Port Interfaces Increase synthesis quality!
Clocking Domains
Verilog-2001
ANSI C style ports standard file I/O (* attributes *) multi dimensional arrays
generate $value$plusargs configurations signed types
localparam `ifndef `elsif `line memory part selects automatic
constant functions @* variable part select ** (power operator)
Verilog-1995
modules $finish $fopen $fclose initial wire reg
parameters $display $write disable integer real +=*/
function/tasks $monitor events time %
always @ `define `ifdef `else wait # @ packed arrays >> <<
assign `include `timescale fork–join 2D memory

11/6/2009 SystemVerilog for Verification 11

The SystemVerilog standard incorporates the Verilog standard by reference, rather than repeating it
and thus potentially diverging from the Verilog standard. You can easily segment SystemVerilog
into just those parts you need to know for your product development role.
The training materials focus first on the designer subset. This subset adds constructs with which
you can more clearly and concisely code your RTL design.
In the design verification role, you can take advantage of most of the new verification features,
without getting involved with …
 The C++-like object oriented features, or
 Importing or exporting C routines.
Of course, for advanced verification, you will want to take advantage of the object oriented
features, such as overloaded operators, classes, polymorphism, and more …
and you may even want to map SystemVerilog functions and tasks to C routines to reuse existing
IP written in C.

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SystemVerilog Verification Building Blocks

The SystemVerilog verification methodology relies on three building blocks.
You can use these blocks separately or together.

Measure the functional coverage

metrics to provide feedback to the
generation and analyze progress of
verification.

Functional
Coverage

Generation Checking
Constrained Random Assertions, Scoreboard

Stimulate the design using Check the behavior of the

automatically generated design (assertions) and the
random test generation. output data to verify
correctness of operation.

11/6/2009 SystemVerilog for Verification 12

The SystemVerilog verification methodology relies on three building blocks that you can use
separately or together:
 You want to stimulate the design with random, yet meaningful combinations of address, data
and other variables;
 During simulation, you want to automatically verify that your defined design properties do not
fail to be true; and
 After simulation, or potentially during simulation, you want to measure how completely the test
verifies the design functionality, and use those results to direct future test efforts.

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Key Verification Features

 Abstract modeling

 Data Abstraction
 2-state, enumerated, structured and user-defined types

 Improved control of processes

 Programs, final blocks, clocking blocks, fork/join extensions

 Dynamic data structures

 Dynamic and associative arrays, and queues
 Class-based objects similar to SystemC and C/C++ capabilities

 Interfaces for Transaction-Level Modeling (TLM)

 Testbench features to support advanced verification methodologies:

 Constrained randomization and coverage

 Design property assertions and covers

 Direct Programming Interface

 Process synchronization with enhanced events, mailboxes and semaphores

11/6/2009 SystemVerilog for Verification 13

SystemVerilog offers features to raise the level of abstraction, to do transaction-based modeling

and verification, and to make your testbench more sophisticated, with constrained randomization
and data and property coverage.

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SystemVerilog Randomization
 Automatic random generation of
stimulus ok
ok == randomize(data)
randomize(data) with
with
 Range and probability of values can {mode
{mode == small -> data
== small -> data << 100;
100;
be controlled via constraints mode == large -> data
mode == large -> data >> 200;};
200;};
 Conditional
 Distributed ok
ok == point.randomize()
point.randomize()
 Weighted
 SystemVerilog supports randcase
randcase
randomization of simple variables or 20
20 :: gen_atm;
gen_atm;
complex object-oriented data 30
30 :: gen_ethernet;
gen_ethernet;
 Also additional constructs for 10
10 :: gen_ipv4;
gen_ipv4;
randomization of events and 55 :: gen_crc_error;
gen_crc_error;
sequence of data endcase
endcase
randsequence
randsequence (( main
main ))
main
main :: inc | dec;
inc | dec;
inc
inc :: {{ do_inc();
do_inc(); };
};
dec
dec : { do_dec(); };
: { do_dec(); };
endsequence
endsequence

11/6/2009 SystemVerilog for Verification 14

You can randomize a scope variable, and you can at once randomize selected properties of a class
instance, optionally using constraint blocks. Constraint blocks can include constraint expressions,
that may involve conditional, distributed, and weighted constraints, and may also specify an order
in which to solve the constraints. SystemVerilog also offers the randcase construct for randomly
selecting branches of a case statement, and the randsequence construct, for generating a random
sequence of statements.

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SystemVerilog Assertions (SVA)

SystemVerilog Assertions (SVA)
always
always @(negedge
@(negedge clock)
clock)
 Used to specify and verify assert
assert !(wr_en && rd_en)
!(wr_en && rd_en)
behavior of a design else
else
begin
begin
 Can be added anywhere in a $display("read/write
$display("read/write fail");
fail");
design hierarchy err_count++;
err_count++;
end
end
 Ignored by synthesis tools
 Checked during simulation
//
// concurrent
concurrent assertion
assertion
 Can also be used to provide property abcd;
property abcd;
functional coverage @(posedge
@(posedge clk)
clk)
 Can also be used as an input aa ##1
##1 b |=> cc ##1
b |=> ##1 d;
d;
to formal verification tools endproperty
endproperty

A1:
A1: assert
assert property
property (abcd);
(abcd);

11/6/2009 SystemVerilog for Verification 15

An assertion “asserts” that a property of the design holds. You use assertions mainly to verify
design properties. You can also use “covers” to measure how completely the test environment
exercises the properties, and for static formal verification, you can use “assumptions” to generate
setup sequences on design inputs. These are all part of SystemVerilog Assertions.

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SystemVerilog Functional Coverage

Coverage allows the user to tell how well a design has been tested.
SystemVerilog has two types of functional coverage:
 Data-oriented coverage  Sequence-oriented coverage
 Coverage groups, coverage  Using SystemVerilog Assertions
points and cross products (SVA)
 Checks combinations of data  Checks whether sequences of
values have occurred behaviors have occurred

//
// SV
SV coverage
coverage group:
group: //
// SVA
SVA functional
functional coverage
coverage
covergroup
covergroup cg1
cg1 @(posedge
@(posedge clk);
clk); property
property full2empty;
full2empty;
Addr:
Addr: coverpoint
coverpoint addr
addr @(posedge
@(posedge clk)
clk)
{{ bins
bins low
low == {{ [0:’h0F],
[0:’h0F], 19
19 };
}; fifo_full
fifo_full ##[1:$]
##[1:$] fifo_empty;
fifo_empty;
bins
bins mid[]
mid[] == {{ 16,
16, 17,
17, 18
18 };
}; endproperty
endproperty
bins
bins high
high == {{ [’h14:’hFF]
[’h14:’hFF] };
}; }} C1
C1 :: cover
cover property
property (full2empty);
(full2empty);
AddrXvalid
AddrXvalid :: cross
cross Addr,
Addr, valid;
valid;
endgroup
endgroup
cg1
cg1 cover_inst
cover_inst == new;
new;

11/6/2009 SystemVerilog for Verification 16

Coverage is a measure of the percentage of verification objectives that have been met. You use this
metric to evaluate the progress of your verification efforts, in order to redirect further efforts
toward areas of the design that are less well tested.
Coverage is in two general categories: tool-instrumented code coverage, that is, of lines,
statements, blocks and expressions; and user-defined functional coverage, that is, of design
behavior. All coverage described by the SystemVerilog standard refers to functional coverage.
Functional coverage measures how well the test environment exercises user-defined design
behavior. Functional coverage requires a structured approach to verification, and, often
painstaking, manual effort.

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SystemVerilog Direct Programming Interface

The Direct Programming Interface (DPI)
 Is a new lightweight C-programming interface
 Maps between SystemVerilog subroutines and C routines

 Without the overhead associated with the PLI:

 SystemVerilog can call subroutines implemented in C
 C can call routines implemented in SystemVerilog

SystemVerilog C
module
module top;
top; #include
#include <stdio.h>
<stdio.h>
...
... #include
#include <svdpi.h>
<svdpi.h>
import
import "DPI-C"
"DPI-C" context
context c_imp
c_imp ==
function int imp_func(...);
function int imp_func(...); int
int c_imp
c_imp (...)
(...)
{{
res
res == imp_func(...);
imp_func(...); ...
...
...
... }}
endfunction
endfunction ...
...

11/6/2009 SystemVerilog for Verification 17

The Direct Programming Interface (DPI) is an interface between SystemVerilog and a foreign
programming language that maps subroutine calls in either language to subroutine implementations
in the other language. The standard defines the SystemVerilog layer and the foreign language layer
separately: SystemVerilog does not know or care that its subroutines are called or implemented in
some other language. The standard currently defines only a C foreign layer.

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SystemVerilog Overview Summary

 SystemVerilog is a substantial enhancement to Verilog

 Based heavily on Verilog-2001

 SystemVerilog has a lot of new content

 97 new keywords

 31 different sections of the Language Reference Manual

 584 pages of all new content

 Huge learning curve for both designers and tool vendors

 Tools may not support some language constructs

 Most users will adopt SystemVerilog incrementally

 The SystemVerilog course modules cover the most useful, most
frequently used and most widely supported features of the language

11/6/2009 SystemVerilog for Verification 18

Many design teams have not yet fully adopted the Verilog-2001 standard. As SystemVerilog is
based on Verilog-2001, such teams will need to learn about Verilog-2001 as well as
SystemVerilog.
Having 97 new keywords means that existing Verilog designs may not compile with
SystemVerilog compilers. For example, if you have a signal named “do”, then your code will not
compile in SystemVerilog because “do” is a SystemVerilog keyword.
However, SystemVerilog does not take features away from Verilog users. Verilog-2001 features
are still available and work the same as before.

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Simple Verification Features

Chapter 2

November 6, 2009

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Aims and Topics

Aims
 To introduce the simple verification features of SystemVerilog

Topics
 Strings

 Time literals

 Immediate assertions

 fork…join enhancements
 Design features useful for verification

11/6/2009 SystemVerilog for Verification 20

This chapter introduces some of the simpler verification features:

 A new string type that is a dynamically resized array of characters and that also offers methods
for manipulating the string.
 Time literals, that include the time unit, so that you unambiguously specify a delay without
referring to the current module timescale.
 Immediate assertions, for specifying actions the simulator should take when the check of a
boolean condition reveals it to be true or to be false.
 Enhancements to the Verilog fork…join construct, to continue executing statements past the
construct after waiting for either none of the forked statements to complete or for the earliest of
the statements to complete.
 And finally, a very brief review of some design features that may also be useful for verification
purposes.

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Strings
 New data type string

 Dynamic array of bytes

string
string message
message == "test
"test ";
";
 Grows/shrinks automatically to
hold contents if
if (pass)
(pass)
message
message == {message,
{message, "passed"};
"passed"};
 Indexed as a normal array else
else
message
message == {message,
{message, "failed"};
"failed"};
 Can be concatenated, replicated and $display("%s", message);
$display("%s", message);
compared
 Can be assigned a string literal

 Some additional special string

string repstr;
repstr;
characters
repstr
repstr == {2{"go
{2{"go "}};
 \f – form feed "}};

 \v – vertical tab
 \a – bell
 \xdd – hex ASCII

11/6/2009 SystemVerilog for Verification 21

For Verilog, you can assign a character string literal to a reg vector.
SystemVerilog provides a string type, which is essentially a dynamic array of byte elements with
some methods defined to manipulate it as a character string. You can still do the operations you
would expect to do on a vector reg that happens to hold the ASCII representation of a character
string. Just remember that indexing a string is selecting a byte instead of a single bit.
Verilog provides escaped character sequences for including newline (\n), tab (\t), backslash (\\) and
quote (\") characters, and any octal representation of a character, within a string literal.
To these, SystemVerilog adds the form feed, vertical tab and bell characters, and any hexadecimal
representation of a character.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 4.7

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String Operators

Operator Usage Function Description

== s1 == s1 Equality Returns 1 if strings are equal

!= s1 != s2 Inequality Logical negation of ==

< s1 < s2 Comparison Return 1 if condition is true.

<= s1 <= s2
> s1 > s2
=> s1 >= s2

{Str,Str} s = {s1,s2,s3} Concatenation Returns concatenated string

{N{Str} s = {5{s1}} Replication Returns string replicated N times

[] b = s1[index] Indexing Returns the byte at index

11/6/2009 SystemVerilog for Verification 22

All of these string operators are just Verilog operators, so they should look familiar to you.

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String Methods

Method Description Syntax & Usage

len() Returns length of the string (length excludes any function int len()
terminating character) str.len();

putc() Replaces ith character of the string with the integral task putc(int i, byte c)
value c
str.putc(i, c);
getc() Returns ASCII code of the ith character in the string function byte getc(int i)
x = str.getc(i);
compare() Compares strings with regard to lexical ordering function int compare(string s)
str.compare(s); // compares str to s
icompare() Compares strings with regards to lexical ordering function int icompare( string s)
and is insensitive to character case str.icompare(s); // compares str to s

substr() Returns new string that is a substring formed by function string substr(int i, int j)
characters in position i through j of str.
str.substr(i,j);

11/6/2009 SystemVerilog for Verification 23

 The “length” ( len() ) method returns the length of the string. This length does not include any
terminating character.
 The “put character” ( putc() ) method replaces the character at the specified location with the
specified ASCII value of a character.
 The “get character” ( getc() ) method returns the ASCII value of the character in the string at
the specified location.
 The “compare” ( compare() ) method compares the string with the specified string argument in
exactly the same manner as the “string compare” (strcmp) function of the ANSI C string
library, that is, negative if less, zero if equal, and positive if greater.
 The “insensitive compare” ( icompare() ) method is like the “compare” method but is not
sensitive to character case.
 The “substring” ( substr() ) method returns a new string identical to the substring that starts at
the first specified location and ends at the second specified location.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 4.7

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String Methods (continued)

Method Description Syntax & Usage

toupper() Returns the upper/lower case of the specified string. function string toupper ()
tolower() String is unchanged. x = str.topper();
atobin() Returns integer value corresponding to ASCII binary / function int atobin()
atooct() octal / decimal / hexadecimal representation. Scans
atoi() all leading digits and underscore (_) characters and str = “21334”;
atohex() stops when any other characters are encountered. int i = str.atoi(); // i = 21334;
atoreal() Returns real value corresponding to ASCII decimal function real atoreal()
representation of a number
str = “3.1416”;
real r = str.atoreal(); // r = 3.1416;
bintoa() Stores the ASCII representation of a binary / octal / task hextoa (int i)
octtoa() decimal / hexadecimal number into a string
itoa() i = 16’h5356;
hextoa() str.hextoa(i); // str = "5356";
realtoa() Stores the ASCII representation of a real number task realtoa (real r)
into the string
r = 3.1416;
str.realtoa(r); // str = "3.1416";

11/6/2009 SystemVerilog for Verification 24

 The “to upper” ( toupper() ) and “to lower” ( tolower() ) methods return the same string with all
characters converted to upper or lower case, respectively. They do not modify the original
string.
 The “ASCII to binary, octal, decimal and hexadecimal” methods return the value of a string
representation of the value. The conversion scans leading digit and underscore characters and
stops the scan at any other character. It does not accept other Verilog literal syntax. It returns 0
if it finds no valid integer literal.
 The “ASCII to real” ( atoreal() ) method does accept all Verilog syntax that constructs a real
literal, and stops at any other character. It returns 0 if it finds no valid real literal.
 The “binary, octal, decimal, hexadecimal and real to ASCII” methods construct a string
representation of the argument value.

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Time Literals
SystemVerilog provides a time literal construct 100ns
100ns
 Explicitly specifies time values 3.55ps
3.55ps
1step
1step
 Integer or fixed point value

 Immediately followed by time unit

 No space between the value and unit
 Units of (fs ps ns us ms s)

 Scaled to the current time unit

 Rounded to the current precision

1step is a delay
 Also a 1step delay value value but no step
time unit exists –
 One simulation precision unit
never 2step etc.

11/6/2009 SystemVerilog for Verification 25

You write a time literal as an integer or fixed-point number, followed immediately by a time unit
(fs ps ns us ms s step) without an intervening space character. The new step time unit refers to the
simulation step, that is, the simulation precision. SystemVerilog scales the time literal to the
current time unit and rounds it to the current time precision. This implies that you must have a
current time unit and precision specified for the interface, module or program in which the time
literal appears.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 3.5

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Time Units in Assignments

You can use a time literal anywhere you would use a unitless integer or real
number to represent time.
 #1step advances simulation 100ps in this example

`timescale
`timescale 1ns
1ns // 100ps
100ps
module testmodule;
module testmodule;
reg
reg a,
a, sel,
sel, y,
y, z,
z, clk;
clk;

initial
initial
begin
begin
#20ns
#20ns sel
sel == 0;
0; //
// blocking
blocking assign
assign
#5.18ns
#5.18ns sel
sel == 1;
1; //
// rounded
rounded to
to 5.2ns
5.2ns in
in this
this example
example
YY == #1step
#1step z;
z; //
// blocking
blocking assign
assign using
using "step"
"step"
end
end

always
always @(posedge
@(posedge clk)
clk)
#5.1ns
#5.1ns aa <=
<= aa ++ 1;
1; //
// non-blocking
non-blocking assign
assign
endmodule
endmodule

11/6/2009 SystemVerilog for Verification 26

You can use a time literal anywhere you would use a unitless integer or real number to represent
time.
This example uses time literals to specify procedural and intra-assignment delays.

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Immediate Assertions
 A procedural assert statement
 Similar to an if statement
always
always @(negedge
@(negedge clock)
clock)
 Ignored by synthesis A1:
A1: assert !(wr_en &&
assert !(wr_en && rd_en);
rd_en);
 May be labeled
immediate assertion
 Access label via %m formatter

 When executed, verifies a boolean

expression
always
always @(negedge
@(negedge clock)
clock)
 Success if evaluates to 1 if (wr_en && rd_en)
if (wr_en && rd_en)
 Failure if evaluates to 0, Z, X $display("error");
$display("error");

 Reports error message by default upon similar Verilog

assertion failure
 You can change this behavior

27 CADENCE CONFIDENTIAL
11/6/2009 SystemVerilog for Verification 27

Immediate assertions are similar to if statements. The assertion succeeds if the asserted expression
in unambiguously true, and fails if the assertion expression is false or unknown. Upon assertion
failure, the tool must display the following minimum information:
 The file name and line number of the assertion;
 The assertion label, or if unlabelled, the scope of the assertion;
 The severity level of the assertion; and
 The simulation time at which the assertion failed.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 17.2

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Action Blocks
You can provide an “action”
block to execute upon success, always
always @(negedge
@(negedge clock)
clock)
rw_chk:
rw_chk: assert
assert !(wr_en
!(wr_en &&
&& rd_en)
failure or both $display ("%m:
rd_en)
success");
$display ("%m: success");
else
 else branch executes on else
begin
begin
assertion failure $display("read/write
$display("read/write fail");
fail");
err_count++;
err_count++;
->
-> rw_err_event;
rw_err_event;
end
end

always
always @(negedge
@(negedge clock)
clock)
assert
assert (valid)
(valid)
//
// pass
pass block
block omitted
omitted
else
else $display("valid inactive");
$display("valid inactive");

always
always @(posedge
@(posedge clock)
clock)
limit_check:
limit_check: assert
assert (err_count
(err_count << 14)
14)
else
else $display("errors >=
$display("errors >= 15");
15");

28 CADENCE CONFIDENTIAL
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You can associate an action block with the assertion. In the action block, you place code to execute
on either the success or the failure of an assertion. The pass block executes if the assertion
succeeds. The fail block executes if the assertion fails. You have the option to include neither,
either or both. It is very common to omit the pass block and just include the fail block.

Note in this example the use of the “percent m” (%m) formatter to display the assertion label.

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Severity Levels
 The action block may override the
default reporting behavior
 $info always
always @(negedge
@(negedge enable)
enable)
assert
assert (valid)
(valid)
 $warning else
else
begin
begin
 $error $warning("invalid
$warning("invalid enable");
enable");
 Default err_count++;
err_count++;
end
end
 $fatal
 Terminates simulation

 Severity level is reported.

always
always @(negedge
@(negedge clock)
clock)
 You can append additional rw_chk
rw_chk :: assert
assert !(wr_en
!(wr_en &&
&& rd_en)
rd_en)
information, using syntax identical to else
else
that for $display $error("wr_en
$error("wr_en &&&& rd_en");
rd_en");

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Assertion severity is error by default. The simulator reports assertion failure as an error and
“should” return from execution with a non-zero error code. You can override the default severity
by using these system tasks in the action block. You may use these system tasks only in an action
block. The fatal severity has the effect of terminating the simulation. These system tasks accept the
same arguments you would use with the $display system task. Just remember that prior to your
own output you will also see all the other assertion failure information.

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Simple Protocol Check: Immediate

SPI SINGLE BYTE WRITE always
always @(posedge
@(posedge CLKCLK iff
iff CE)
CE)
CLK begin : CHECK
begin : CHECK
repeat
repeat (16)
(16)
CE
begin
begin
SCLK assert
assert (( CECE &&
&& SCLK
SCLK ))
SDI A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
else // short pulse
else // short pulse
SD0 HIGHZ
begin
begin
$error("short
$error("short CE CE pulse");
pulse");
disable
disable CHECK;
CHECK;
Verify 16 SCLK’s within CE pulse end
end
@(posedge
@(posedge CLK);
CLK);
Immediate assertions provide only a assert
assert (( CE
else
CE &&
&& !SCLK
!SCLK ))
else // // short
short pulse
non-temporal boolean check begin
begin
pulse

$error("short
$error("short CE CE pulse");
Extra code required – as if we had disable CHECK;
disable CHECK;
pulse");

used if end
end
@(posedge
@(posedge CLK);
CLK);
 Timing controls end
end
assert
assert (( !CE!CE &&
&& !SCLK
!SCLK ))
 Loops else // long
else // long pulsepulse
$error("long
$error("long CE CE pulse");
pulse");
end : CHECK
end : CHECK

11/6/2009 SystemVerilog for Verification 30

The procedural block continually does the following:

 It synchronizes to the rising edge of “chip-enable” (CE), which indicates the start of a frame.
 For 16 iterations, it verifies that CE remains high while “serial-clock” (SCLK) toggles high and
low.
• If it subsequently during any iteration finds CE low, then the assertion fail block reports a
short pulse and terminates the current check.
• If CE remains high for the 16 iterations, the block then verifies that CE is low on the
following CLK. If it finds CE high, then the assertion fail block reports a long pulse.
Note that the code only performs a very basic check that the CE signal stays high for 16 clocks. In
practice you would have to write much more SystemVerilog code to check, for example, correct
address and data combinations, burst transfers, and so forth.

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Immediate and Concurrent Assertions

An immediate assertion is an SystemVerilog also has concurrent
instantaneous boolean check assertions
 Single-cycle  Can span multiple cycles

always
always @(posedge
@(posedge CLK
CLK iff
iff CE)
CE) sequence
sequence SCYC;
SCYC;
begin : CHECK
begin : CHECK (CE
(CE &&
&& SCLK)
SCLK) ##1
##1 (CE
(CE &&
&& !SCLK);
!SCLK);
repeat
repeat (16)
(16) endsequence
endsequence
begin
begin
assert
assert (( CE
CE &&
&& SCLK
SCLK )) SPI1
SPI1 :: assert
assert property
property (( @(posedge
@(posedge CLK)
CLK)
else // short pulse
else // short pulse !CE
!CE ##1 CE |-> SCYC[*16]
##1 CE |-> SCYC[*16] ##1
##1 !CE
!CE );
);
...
...
@(posedge
@(posedge CLK);
CLK);
assert
assert (( CE
CE &&
&& !SCLK
!SCLK ))
else // short pulse
else // short pulse
...
...
@(posedge
@(posedge CLK);
CLK);
end
end
assert
assert (( !CE
!CE &&
&& !SCLK
!SCLK ))
else
else //// long
long pulse
pulse
$error("long
$error("long CECE pulse");
pulse");
end
end :: CHECK
CHECK

11/6/2009 SystemVerilog for Verification 31

Immediate assertions have limited functionality. They perform only an instantaneous boolean
check, and so require extra code for complex or temporal checks. This extra code can be
substantial, even for a simple protocol. The complexity of the assertion code can be comparable to
that of the design, and require as much debugging.
SystemVerilog also has concurrent assertions. They provide a syntax with which to concisely state
complex multi-cycle design properties. This training module will further discuss only concurrent
assertions.

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Parallel Block Enhancements: join_any, join_none

join Verilog

 Parent process blocks until all fork a b c

fork
a;b;c;
spawned blocks complete a;b;c;
join
join
d;
d;
d
join_any
SystemVerilog
 Parent process blocks until any
spawned block completes fork
fork a b c
a;b;c;
a;b;c;
 Other blocks left running join_any
join_any d
d;
d;

SystemVerilog
join_none
fork a b c d
fork
 Parent process does not block a;b;c;
a;b;c;
join_none
 All blocks left running join_none
d;
d;

11/6/2009 SystemVerilog for Verification 32

With the conventional Verilog fork-join, all forked processes must complete before the procedure
can continue.
SystemVerilog adds the join_any and join_none variants:
 With join_any, the parent procedure continues when any forked process completes.
 With join_none, the parent procedure continues without waiting for any forked processes to
complete. As join_none allows the parent procedure to continue while forked processes are still
running, SystemVerilog adds statements to control forked processes from outside the
fork…join_none statement.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 11.6

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Process Control: disable fork, wait fork

The disable fork statement
terminates all active descendents
of the current process fork
fork
a;b;c; a b c
a;b;c;
 Use after join_any to
ensure only one forked block
join_any
join_any
disable
disable fork;
d;
d;
fork; x x d

completes

fork
fork
The wait fork statement stops a;b;c;
a;b;c;
further execution until all forked join_any
join_any a b c
blocks complete fork d e
fork
d;
 Affects all forks in current d;
join_none
join_none
scope wait
fork
e;
e;
f
wait
wait fork;
fork;
f;
f;

11/6/2009 SystemVerilog for Verification 33

The disable fork statement terminates all sub-processes of the procedure that executes the
statement.
Using a fork...join_any with a later disable fork allows a SystemVerilog testbench to spawn several
concurrent processes to wait for separate events, for example separate system interrupts, and as
soon as one event is received, terminate the other outstanding processes to handle the received
event.
The wait fork statement causes the executing procedure to wait until all of its sub-processes have
completed.
With the combination of join_any, join_none, and wait fork, you can model complex concurrent
and serial behavior. The lower example illustrates this. The parent procedure spawns three
subprocesses, and upon the earliest to complete, spawns another subprocess and continues with its
own execution. Note that without timing controls, no statement execution order between the parent
and spawned processes is implied. At a later point where the parent needs the results from all
subprocesses, it waits for all to complete before continuing its own execution.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 11.8

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Fine-Grain Process Control

SystemVerilog processes provide query and control methods:

Method Description
static function process self() Return handle of calling process
function state status() Return state of process
enum state { FINISHED, RUNNING, WAITING, SUSPENDED, KILLED };
task await() Wait for a process to terminate
Note: Illegal to wait for self
function void suspend() Suspend a process
function void resume() Resume a suspended process
function void kill() Forcibly terminate a process

11/6/2009 SystemVerilog for Verification 34

A process is a built-in class. As we have not yet discussed classes, you may want to review these
notes after you have studied the chapter about classes. Briefly, a class describes data and methods
that every object of that class has. Class methods typically manipulate the data that belongs to the
class object for which the method is called.
SystemVerilog creates the process object either statically, for example for initial and always
blocks, or dynamically, for fork blocks. A variable of the process type is a handle for one of these
process class objects. You obtain a process’s handle value by calling its self() method from within
the process. The process can then store that handle value somewhere accessible to other processes,
that can then manipulate the state of that process.

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Design Features in Verification

Many design features are package
package mytypes;
mytypes;
also useful in verification:
typedef
typedef struct
struct {{
bit[2:0]
bit[2:0] stim;
stim;
bit[5:0]
bit[5:0] resp;
resp;
 Packages module
module LUTtest;
LUTtest;
parameter
string
string mess;
mess;
parameter size_of_array
size_of_array == 20;
20; }} stimresp;
import stimresp;
import mytypes::*;
 Structures logic
mytypes::*;
logic ip1,
ip1, ip2,
ip2, ip3;
ip3; //
// DUT
DUT inputs
inputs
endpackage
endpackage
logic
logic op1, op2, op3, op4, op5,
op1, op2, op3, op4, op5, op6;
op6; //
// DUT
DUT outputs
outputs
 2-state data types ...
... //
// instantiate
instantiate DUT
DUT
stimresp
stimresp test_data[(size_of_array-1):0];
test_data[(size_of_array-1):0];
 Arrays wire
wire [5:0]
[5:0] resp;
resp; //
// expected
expected results
results
assign
assign resp = {op1, op2, op3,
resp = {op1, op2, op3, op4,
op4, op5,
op5, op6};
op6};
 Assignment patterns initial
initial //
// Stimulus
Stimulus Response
Response Message
Message
test_data
test_data = { {3’b000, 6’b100000, "init
= { {3’b000, 6’b100000, "init error"},
 Local variables
error"},
{3’b001,
{3’b001, 6’b000010, "t1 failed"},
6’b000010, "t1 failed"},
...
... };
};
initial
initial begin
begin
@(negedge
@(negedge clk);
clk);
for
for (int
(int ii == (size_of_array-1);
(size_of_array-1); i>=
i>= 0;
0; i--)
i--) begin
begin
{ip1,
{ip1, ip2,
ip2, ip3}
ip3} <=
<= test_data[i].stim;
test_data[i].stim;
@(negedge
@(negedge clk);
clk);
assert
assert (resp
(resp ==== test_data[i].resp)
test_data[i].resp)
else $error(test_data[i].mess);
else $error(test_data[i].mess);
end
end
...
...

11/6/2009 SystemVerilog for Verification 35

This example uses some typical SystemVerilog design features in a testbench.

It declares a structure type in a package. The structure has a 3-bit stimulus field, a 6-bit response
field, and a string for an error message.
The testbench module implicitly imports the package contents and declares an array of the
structure type. In the first initial block, it preloads the array with stimulus, expected response and
error messages. The error messages can be different lengths.
The testbench assigns a concatenation of design outputs to a response vector.
The testbench loops through the array, applying stimulus, waiting one clock cycle, and checking
the response. It checks the response by using an immediate assertion, which upon failure, displays
the message associated with that stimulus and response pair.

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Unions
You use a union to store different data types at the same memory location.
The union size is the size of its largest field. Fields of a packed
union must be all
union the same size.
union {{
logic
logic [31:0]
[31:0] udata;
udata; //
// unsigned
unsigned data
data
integer sdata;
integer sdata; //
// signed data
signed data
}} inbus,
inbus, outbus;
outbus; //
// 32-bit
32-bit variables
variables

inbus.udata
inbus.udata == 32’h00f3;
32’h00f3;
outbus.sdata
outbus.sdata = -44;
= -44;

typedef
typedef union
union {{
int
int i;
i;
shortreal
shortreal f;f;
}} num;
num; //
// named
named union
union type
type

num
num n1,
n1, n2;
n2; //
// instances
instances of
of union
union type
type

n1.f
n1.f == 0.0;
0.0; //
// set
set n1
n1 in
in floating
floating point
point format
format
n2.i = -44; // set n2 in integer
n2.i = -44; // set n2 in integer format format

11/6/2009 SystemVerilog for Verification 36

The union construct provides a way to view the same memory location as different data types
without the need to cast the data types. The SystemVerilog union is identical to the C union, with
two exceptions:
 First: You cannot provide a tag name for a SystemVerilog structure or union. You can
alternatively use the typedef keyword to declare a type name for the structure or union.
 Second: You can further qualify the SystemVerilog union as “tagged”. A SystemVerilog tagged
union is type-checked. The next slide has an example of a tagged union.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 4.11

The IEEE draft standard P1800/D9 proposes to allow fields of a packed union to be different sizes
if the union is also tagged so as to specify what size field is currently in use.

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Union Example
Structures can contain unions and unions can contain structures.

typedef
typedef struct
struct {{
union
union {{
int
int i;
i;
shortreal
shortreal f;f;
}} n;
n; //
// anonymous
anonymous union
union type
type
bit
bit isfloat;
isfloat;
}} tagged_s;
tagged_s; //// named
named struct
struct type
type

tagged_s
tagged_s a[9:0];
a[9:0]; //array
//array of
of structure
structure containing
containing union
union

typedef
typedef union
union tagged
tagged {{
int
int i;
i;
shortreal
shortreal f;
f;
}} tagged_u;
tagged_u;
tagged_u value; int j; shortreal
tagged_u value; int j; shortreal g;
g;
value
value == tagged
tagged ff 3.14156;
3.14156;
gg == value.f;
value.f; //
// legal
legal
jj == value.i;
value.i; //
// illegal
illegal

11/6/2009 SystemVerilog for Verification 37

The top example declares an array of a named structure type that contains a field that is a union.
The other structure field is a bit that indicates whether the structure union field is currently being
used as an int type or as a float type.
SystemVerilog provides the tagged union qualifier to serve exactly that purpose. A tagged union
stores both its current value and its current tag. Subsequent expressions accessing the tagged value
must be of the current tag type. This type checking is generally done during run time.

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Summary
 With the string type, you can create and manipulate messages
without having to worry about string sizes
 With time literals, you explicitly specify the time unit, which makes your
code more robust and more readable
 Immediate assertions simplify verification and error checking
Concurrent assertions provide more capability, as you will see …

 With the fork…join enhancements, you can better control complex

testbench behavior
 Several of the design features are also useful in verification

packages, structures, array enhancements and more …

11/6/2009 SystemVerilog for Verification 38

Pause here for a moment, and review what you have learned about the simple SystemVerilog
verification features.

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About Lab 1
For this lab you debug a 8X32 synchronous memory design.
The lab introduces the design you will use for several subsequent labs.
It uses no new verification features – you can do this lab any time.

TOP top_m : top_m (top_m.sv)

5 addr
TEST read MEMORY
memory_test : write memory :
memory_test_m memory_m
8 data_in
(memory_test_m.sv) (memory_m.sv)
8 data_out

clk

11/6/2009 SystemVerilog for Verification 39

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Verification Blocks

Chapter 3

November 6, 2009

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Aims and Topics

Aims
 To introduce the new SystemVerilog verification blocks

Topics
 Event scheduler

 Programs

 Final blocks

 Clocking blocks

11/6/2009 SystemVerilog for Verification 41

This chapter introduces the new SystemVerilog verification blocks. As a foundation to

understanding these blocks, we need to first look at how the SystemVerilog scheduler divides a
timeslot into separate regions, and the actions it performs in each region. We can then look at
programs, somewhat like modules, but meant to hold testbench code, thus clearly separating
testbench from design. Then we can look at a new kind of block, somewhat like an initial block,
but that executes at the end of the simulation rather than at the beginning of the simulation. And
finally, we will look at clocking blocks, a way to clearly separate testbench timing from testbench
functionality.

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Verilog Event Scheduler

Does not show regions
previous time slot used only by PLI

Execute module process statements

Active Evaluate continuous assignments and primitives

Inactive #0 Blocking assignments

NBA Non-blocking assignments

Monitor $monitor, $strobe, PLI/VPI calls

to next time slot

11/6/2009 SystemVerilog for Verification 42

A simulation timeslot is divided into ordered regions to provide a predictable interaction between
design constructs.
The Verilog event schedule has four regions for each simulation time:
 The Active region is for executing process statements.
 The Inactive region is for executing process statements postponed with a “pound zero” (#0)
procedural delay.
 The NBA region is for updating non-blocking assignments.
 The Monitor region is for executing $monitor and $strobe and for calling user routines
registered for execution during this read-only region. You cannot within this region create
additional events.
The first three of these regions are iterative – they can schedule events that require return to the
Active region. When no more events exist for the current simulation time, the simulator executes
Monitor statements and then advances simulation time to the next time for which events are
scheduled. The simulation terminates when no such future events exist.

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SystemVerilog Event Scheduler

previous time slot Does not show regions
Preponed Sample stable values
used only by PLI

Execute module process statements

Active Evaluate continuous assignments and primitives

Inactive Execute #0 delayed statements

NBA Non-blocking assignments

Observed Evaluate assertions

Re-Active Execute action blocks and programs

Re-Inactive Execute #0 delayed statements

$monitor, $strobe, PLI/VPI calls

Postponed
to next time slot

11/6/2009 SystemVerilog for Verification 43

SystemVerilog adds regions to provide a predictable interaction between assertions, design code
and testbench code. It adds the Observed region in which to evaluate assertions, and the Re-Active
and Re-Inactive regions in which to execute assertion action blocks and testbench programs.
The SystemVerilog event schedule has 13 regions for each simulation time. Some regions used
only by the PLI are not shown on the slide and not described here:
 The Preponed region is for sampling signal values before anything in the time slice changes
their values.
 The Active region is for executing interface and module process statements. It is the same as
for Verilog.
 The Inactive region is for executing interface and module process statements postponed with a
“pound zero” (#0) procedural delay. It is the same as for Verilog.
 The NBA region is for updating non-blocking assignments. It is the same as for Verilog.
 The Observed region is for assertion evaluation.
 The Reactive region is for executing program process statements and assertion action blocks.
 The Re-inactive region is for executing program process statements postponed with a “pound
zero” (#0) procedural delay.
 The Postponed region is for system tasks that record signal values at the end of the time slice.
The Active through Re-inactive regions are iterative. Most of these regions can schedule events
that require return to the Active region.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 9.3

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Programs: program
A new separately-compilable unit similar to a module
module top;
top;
module: clkgen
clkgen cgen(clk);
cgen(clk);
mem_interface
mem_interface intfc(clk);
intfc(clk);
 Intended to separate test and design mem_design
mem_design dut (intfc);
dut (intfc);
 Cannot instance or embed other units mem_test
mem_test tb
tb (intfc);
(intfc);
endmodule
endmodule :: top
 Cannot have always, specify, etc. top

 Intended to reduce user-induced races

program
program mem_test
mem_test ((
 Executes in the Reactive region of the time interface
interface intfc;
intfc;
slot instead of the Active region );
);
 Program assignments to program variables ...
...
are always blocking initial
initial begin
begin
...
...
 Program assignments to non-program
end
end
variables are always non-blocking endprogram
endprogram :: mem_test
mem_test
 Non-programs cannot access program
variables
 Can use new $exit system task to
terminate program

11/6/2009 SystemVerilog for Verification 44

A program cannot contain hierarchy and cannot have an always block, but is otherwise similar to a
module, with some additional restrictions. It is intended to remove testbench stimulus from the
module construct and instead execute those statements in the Reactive region separately from the
execution and update of design code. To further reduce the potential for user-induced clock/data
races, the program construct requires the user to make only blocking assignments to program
variables and only non-blocking assignments to module and interface variables.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 16

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Final Blocks: final

Procedural blocks that execute once at the end of simulation:
 After explicit or implicit call to $finish

 Cannot invoke scheduler (no scheduled assignments or delays)

 Can be used to calculate and display simulation statistics

final
final begin
begin
if (timeout_error)
if (timeout_error)
$display
$display ("ERROR:
("ERROR: %0t:
%0t: Test
Test Timed
Timed Out",
Out", $time);
$time);
else
else
$display
$display ("INFO:
("INFO: %0t:
%0t: Test
Test Complete",
Complete", $time);
$time);
$display("Error
$display("Error Count:
Count: %d",
%d", error_count);
error_count);
$display("Fifo
$display("Fifo Overflow
Overflow Count:
Count: %d",
%d", fifo_overflow);
fifo_overflow);
end
end

11/6/2009 SystemVerilog for Verification 45

A final block cannot consume simulation time, but is otherwise similar to an initial block. You can
place a final block anywhere you can place an initial block. SystemVerilog executes all final
blocks exactly once at the end of simulation, in an unspecified but repeatable order.
SystemVerilog executes the final blocks upon encountering $finish or upon running out of events
to process. Any final block that itself calls $finish or calls a user-defined system task or function
that terminates the simulation (invokes tf_dofinish() or vpi_control(vpi_finish…)), aborts
execution of the final blocks. After SystemVerilog completes or terminates execution of the final
blocks, it calls any PLI routines you have scheduled for execution at the end of the simulation.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 10.7

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Clocking Blocks: clocking

 Specifies timing relative to a specific clock for a set of signals

 Sample skew and drive skew

 Specifies timing – does not declare signals

 Separates signal timing from signal function

 Helps avoid user-induced clock/data races

 You can write tests in terms of cycles and transactions

clocking
clocking cb
cb @(posedge
@(posedge clk);
clk);
input
input dout;
dout;
output
output reset,
reset, enable,
enable, data;
data;
endclocking
endclocking

11/6/2009 SystemVerilog for Verification 46

A clocking block defines a set of timing, relative to a specified clock, for a set of signals. Any
number of signals may appear in any number of clocking blocks. You declare a clocking block as
an interface, module or program item. You can declare one clocking block in any scope to be the
default clocking block for that scope. You apply the timing by referencing the signal hierarchically
through the clocking block name.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 15

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Clocking Block Syntax

 Inputs sampled skew units before clocking event

 Outputs driven skew units after clocking event

 Directions simple restrict whether you can sample (inputs and inouts) or
drive (outputs and inouts) signals using this this set of timing
clocking event
identifier

clocking
clocking cb
cb @(posedge
@(posedge clk);
clk);
default timing skew
default
default input
input #1step
#1step for inputs/outputs
output
output #3;
#3;
input to
clocking block input
input dout;
dout;
output
output reset,
reset, data;
data;
output
output negedge enable;
negedge enable;
outputs from SystemVerilog
clocking block endclocking
endclocking explicit keywords in bold
timing skew

11/6/2009 SystemVerilog for Verification 47

A clocking block is both a declaration and instance of that declaration. You do not instantiate a
clocking block.
Pause here for a moment, and examine the clocking block syntax.
--------
clocking_declaration ::=
[ default ] clocking [ clocking_identifier ] clocking_event ;
{ clocking_item }
endclocking [ : clocking_identifier ]

IEEE Std. 1800-2005 SystemVerilog LRM, Section 15.2

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Input and Output Skews

 Input skew designates sample time for
signal relative to the clocking event
 #n – Postponed region before clock
clocking
clocking cb
cb @(posedge
@(posedge clk);
clk);
 Defaults to #1step
default
default input
input #1step
#1step
 #0 – Observed region after clock output
output #3;
#3;
 Output skew designates driving time for input dout;
input dout;
signal after the clocking event output
output reset,
reset, data;
data;
output
output negedge
negedge enable;
 Defaults to #0 (always NBA) enable;
endclocking
endclocking
 You can specify skew:
 As a default for inputs
 As a default for outputs
 Explicitly with the signal identifier,
overriding the default
 As an edge, number or time literal
 Number uses current timescale

11/6/2009 SystemVerilog for Verification 48

A skew must be a constant expression, which may be a parameter.

An input skew specifies the sampling time before the clock event. The default input skew is #1step,
which samples the input during the preceding Postponed region. An explicit #0 skew samples the
input during the Observed region.
An output skew specifies the drive time after the clock event. The default output skew is #0, which
drives the output during the NBA region. The year 2005 standard does not explicitly specify the
clock from which the output skew shall be referenced. Most vendors make that the current clock if
simulation time has not advanced since the active clock edge, and otherwise the next clock.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 15.3

The IEEE draft standard P1800/D9 proposes to move output transitions to a new “Re-NBA” region
after the Re-Inactive region.

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Clocking Skew Example

clocking
clocking cb
cb @(posedge
@(posedge clk);
clk);
default input #1step
default input #1step
output
output #3;
#3;
clk input
input dout;
dout;
output
output reset,
reset, data;
0 5 10 data;
output
output negedge enable;
negedge enable;
dout reset enable endclocking
endclocking
data

Assume clock period of 10ns, timescale of 1ns and timeprecision of 10fs

dout sampled #1step before (posedge clk) = 10fs before 5ns

reset, data driven #3 after (posedge clk) = 8ns
enable driven on (negedge clk) = 10ns

11/6/2009 SystemVerilog for Verification 49

For this example:

 The positive edge of the clock occurs at 5ns.
 Inputs are sampled one simulation time step, in this case 10fs, before the clock event.
 Most outputs are driven 3ns after the clock event, in this case, at 8ns.
 The “enable” signal is driven on the negative edge of the clock after the clock event, in this
case, at 10ns.

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More Output Skews

clk

@(cb) // timing control var

var bit
bit def=0,two=0,neg=0;
def=0,two=0,neg=0;

def clocking
clocking cb
cb @(posedge
@(posedge clk);
clk);
two output
output def;
def;
output
output #2
#2 two;
two;
neq
output negedge neg;
output negedge neg;
@(cb) #1 // same result as endclocking
endclocking
@(cb) @(negedge clk)
initial
initial
def begin
begin
...
... //
// timing
timing control
control
two
cb.def<=1;
cb.def<=1;
neq cb.two<=1;
cb.two<=1;
cb.neg<=1;
cb.neg<=1;
@(cb) @(negedge clk) #1
end
end
def
two
neq
11/6/2009 SystemVerilog for Verification 50

The year 2005 standard neglects to specify the clock from which the output skew is referenced.
Most vendors drive outputs with reference to the current clock for assignments made in the same
time slice in which the clock edge occurs.
For this example, an output with the default “pound zero” (#0) skew is driven in the next NBA
region of the current time slice if the assignment is scheduled in the same time slice in which the
positive edge of the clock occurred. The first set of waveforms illustrates this. Likewise, an output
with the “negedge” skew is driven in the next NBA region of the current time slice if the
assignment is scheduled in the same time slice in which the negative edge of the clock occurred.
The second set of waveforms illustrates this.

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Multiple and Default Clocking Blocks

You can define multiple
clocking blocks in a scope clocking
clocking cb1
cb1 @(posedge
@(posedge clk1);
clk1);
default
default input #2
input #2 output
output #3;
#3;
 For multiple clocks, input
input cdout;
cdout;
different signals, or simply output
output reset,
reset, data;
endclocking
data;
endclocking
different timing
clocking
clocking si1
si1 @(posedge
@(posedge clk2);
clk2);
 Only one block in a scope input #2 ip1;
input #2 ip1;
output
output #2
#2 op1;
op1;
can be the default clocking endclocking
endclocking
block default
default clocking
clocking si2
si2 @(posedge
@(posedge clk2);
clk2);
 Add default to the input #2 ip2;
input #2 ip2;
output
output #5
#5 op2;
beginning of the clocking endclocking
op2;
endclocking
block declaration
 Or use a default clocking
clocking si2
si2 @(posedge
@(posedge clk2);
clk2);
statement separate from input #2 ip2;
input #2 ip2;
output
output #5
#5 op2;
the declaration endclocking
op2;
endclocking
default
default clocking
clocking si2;
si2;

11/6/2009 SystemVerilog for Verification 51

You can use either of two methods to declare a clocking block to be the default clocking block of
the scope:
 You can directly declare a default clocking block; or
 You can declare an already declared clocking block to be the default clocking block.
Only one default clocking block can exist in a module, interface or program.
A default clocking block is valid only in the scope declaring it and any nested declarations.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 15.11

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Accessing a Clocking Block Signal

To apply timing, access the signal
through the clocking block bit reset, enable;
clocking cb @(posedge clk);
 dreg <= cb.dout; default input #1step output #3;
input dout;
 Gets sampled value output reset, data;
output negedge enable;
 cb.enable <= 1;
endclocking
 Schedules assign for drive skew
initial begin
 Must use non-blocking assignment @(cb);
cb.reset <= 1’b1;
 @(cb)
cb.enable <= 1’b1;
 @(posedge clk) @(cb.dout);

 @(cb.dout) 5 8 10
 @(posedge clk iff cb.dout) clk

Timing applies reset

only when signal
accessed through
clocking block. enable

11/6/2009 SystemVerilog for Verification 52

To apply the timing of a clocking block, you hierarchically reference the signal through the
clocking block name.
To synchronize a process to a clocking block, you can either:
 Directly use the clocking block name in a sensitivity list. This triggers the sensitive process on
the clocking block clock event.
 Use clocking block signal inputs, or slices of them, in a sensitivity list. This triggers the
sensitive process on the clocking block signal event.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Sections 15.9, 15.13

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Cycle Delay and Synchronous Drive

You can insert clocking event delays
default
default clocking
clocking cb;
cb; //
// as
as previous
previous
##(expr)
 You can omit the parentheses if
clocking
clocking cb4
cb4 @(negedge
@(negedge clk);
clk);
input
input #1step dout;
#1step
expr is a number or identifier output
output #3
dout;
#3 reset,
reset, data,
data, enable;
enable;
endclocking
 The expr value must be positive endclocking

 ##0 means wait for a clocking //

// Wait
Wait 22 default
default clocking
clocking cycles
cycles
// remember dreg value
event in this time step and do not // remember dreg value
//
// drive
drive data
data 33 cb4
cb4 cycles
cycles later
later
wait if it already occurred //
// Error if no default clocking
Error if no default clocking
##2;
##2; cb4.data
cb4.data <=<= ##3
##3 dreg;
 Procedural delay always refers to dreg;

default clocking (must be defined) //

// Same
Same --
-- procedural
procedural delays
delays
//
// always
always use
use default
default clocking
clocking
 Synchronous drive always refers to ##2
##2 cb4.data
cb4.data <=
<= ##3
##3 dreg;
dreg;
target variable’s clocking
 Note – is not an intra-assignment
delay (illegal to clocked signals)

11/6/2009 SystemVerilog for Verification 53

The semantics of the cycle delay (##N) operator differ depending upon how you use it:
 When used as a procedural or intra-assignment delay in an assignment to a clocking block
signal, it refers to the clock event of the specified clocking block. These assignments must use
the non-blocking operator.
 When not used as a procedural or intra-assignment delay in an assignment to a clocking block
signal, it refers to the default clocking block. For this situation, the compiler shall issue an error
if no default clocking block has been declared.
--------
clocking_drive ::=
clockvar_expression <= [ cycle_delay ] expression
| cycle_delay clockvar_expression <= expression

IEEE Std. 1800-2005 SystemVerilog LRM, Sections 15.10, 15.14

The IEEE draft standard P1800/D9 proposes to make the use of cycle delay timing controls illegal
for intra-assignment delays.

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Hierarchical Expressions
A clocking block signal cannot be a hierarchical expression
You can associate a clocking block signal with a hierarchical expression

clocking
clocking cb
cb @(posedge
@(posedge clk);
clk);
default input #1step
default input #1step
output
output #3;
#3;
input
input dout;
dout;
//data
//data associated
associated with
with hierarchical
hierarchical expression
expression
output reset, data = top.dut.data;
output reset, data = top.dut.data; //
// Valid
Valid
//
// output
output top.dut.data;
top.dut.data; // Invalid
// Invalid
output
output negedge
negedge enable;
enable;
endclocking
endclocking

11/6/2009 SystemVerilog for Verification 54

You cannot within a clocking block directly declare a hierarchical signal. You must instead declare
a clocking block virtual signal and associate it with an expression that references the hierarchical
signal. The semantics of this association are much like those for a port connection – you can use
any expression, including slices, concatenations and part selects, that you can legally connect to a
port of that direction.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 15.4

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Summary
What can you do with new verification blocks
 Clearly separate verification from design code with a program
 For potentially reducing user-induced races

 Summarize simulation statistics with a final block

 For “wrapping up” the simulation session just prior to its termination

 Clearly separate functionality and timing with a clocking block

 For controlling drive and sample time with respect to a clock
 Cycle delays and centralized timing simplify testbench creation

11/6/2009 SystemVerilog for Verification 55

Pause here for a moment and review what you have learned about SystemVerilog programs, final
blocks, and clocking blocks.

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Quiz
1. What do the input, inout, and output clocking directions signify?
2. How is a specific clocking block defined as the default?
3. Given the clocking blocks, what do these delays represent?

clocking
clocking cb1
cb1 @(negedge
@(negedge clk);
clk); @(cb1);
@(cb1);
output
output posedge
posedge drive;
drive; ##2;
##2;
endclocking
endclocking cb1.drive
cb1.drive <=
<= ##3
##3 1;
1;
clocking
clocking cb2
cb2 @(negedge
@(negedge clk);
clk); ##3;
##3; cb1.drive <=
cb1.drive <= 2’b10;
2’b10;
endclocking ##(j-2)
##(j-2) cb1.drive
cb1.drive <=
<= 1;
1;
endclocking
default
default clocking
clocking cb2;
cb2;
int j = 3;
int j = 3;

Solutions in Appendix A

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About Lab 2
For this lab you define a clocking block for the memory testbench and use
the clocking block timing while testing the memory.

TOP top_m : top_m (top_m.sv)

5 addr
TEST read MEMORY
memory_test : write memory :
memory_test_m memory_m
8 data_in
(memory_test_m.sv) (memory_m.sv)
8 data_out

clk

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Transaction Level Modeling (TLM)

Chapter 4

November 6, 2009

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Aims and Topics

Aims
 To introduce Transaction Based Verification (TBV) and how
SystemVerilog interfaces promote that methodology

Topics
 What is a Transaction?

 Transaction Based Verification (TBV)

 Transactors

 Transaction structure

 Interface review
 Interface transactors

11/6/2009 SystemVerilog for Verification 59

This chapter introduces transaction-based verification and discusses how you can use a
SystemVerilog interface as a transactor.

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What is a Transaction?
 A transaction is a transfer of data between
design blocks
 A transfer may be composed of many
A B
signal transitions over several cycles
 Working with data at the transaction level signal representation
raises our abstraction level
ADDR
 Transfers are easier to create, debug, AS
maintain and manage
RW
 Transactions may have parameters DS

 address, data, etc DATA

 Transactions are nothing new DA

 Used in script-driven testbenches transaction

do_read_mem
address = ff000
data = ??

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Using transactions allow you to design and debug at a higher level of abstraction. That is, you
develop and analyze your system-level design and test environment using transactions, rather than
wading through a sea of signal waveforms.
Transactions are most useful when you have well-defined interfaces for your design and test
environment. Interface methods implement the transactions.
The use of transactions is not a new concept. Transaction-based verification has been used for
many years. Many HDL verification environments already do transaction-based verification.

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What is Transaction Based Verification?

A testbench is in two layers
 Stimulus Generator
 Generates high level commands (transactions)

 Transaction Verification Model (TVM, also called a “transactor”)

 Translates between transactions and signal transitions

Stimulus
Generator Transactor or TVM
do_burst_write
...
proc.do_read Transactions address =
ff001000
proc.do_write data = 00112233
00 11 22 33
... Signals
Design or DUV
Design

ff*

00 11 22 33

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A Transaction-Based Verification (TBV) environment contains two layers:

 The transaction producer generates a stream of data and operations to be performed on the data.
 The Transaction Verification Model (TVM), also called a transactor, converts between the test
environment transactions and the low-level signal transitions at the Design Under Verification
(DUV). This conversion can go both ways, in which case the test environment also consumes
transactions.

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Transactor Structure
A transactor has three parts
 Transaction interface
 Stimulus generator Transactions do_read
(transaction producer) Transaction
Interface do_write
 Response checker
(transaction consumer)
do_rmw
 Signal interface Transactor
 DUV ports Functional
Code
 Transactor functionality
Signal
 Create data sequences
to drive signal interface Transactor Interface
or TVM
 Checks signal interface Signals
sequences for correct
operation

11/6/2009 SystemVerilog for Verification 62

A transactor converts between transactions and signal transitions:

 If on the transaction producer side, it converts incoming transactions from the producer into
signal-level handshake with the RTL design.
 If on the transaction consumer side, it converts signal-level handshake with the RTL design
into transactions for the consumer.
 The transactor internally contains state machines to interact properly with the design. The
transactor is also likely instrumented with assertions and coverage.

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Simple Transactor Using Interfaces

An interface can implement most interface
interface spi_if
spi_if (input
(input clk);
clk);
of the transactor functionality logic sdi,
logic sdi, sdo;
sdo;
Here is a simple interface:
logic
logic ce;
ce;
task
task init
init ();
();
 It has a clock port begin
begin
ce
ce == 0;
0;
 It declares design signals sdi
sdi == 0;
0;
@(posedge
@(posedge clk);
clk);
 Interface tasks (methods) end
end
endtask
control the design signals
endtask
task
task send(input
send(input [7:0]
[7:0] waddr,
waddr,
 Hence “transactor” input
input [7:0]
[7:0] wdata
wdata );
);
begin
begin
sdi
sdi == 0;
0;
ce
ce == 1;
1;
SPI SINGLE BYTE WRITE @(posedge
@(posedge clk);
clk);
CE for
for (int
(int ii == 15;
15; i>0;
i>0; i--)
i--)
SCLK ... // write serializer
... // write serializer
end
end
SDI A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
endtask
endtask
SD0 HIGHZ
endinterface
endinterface

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SystemVerilog interfaces can implement most of the features of a transactor.

This example interface declares a clock input port to synchronize the interface methods with the
test environment, input, output and enable signals shared by users of the interface, and tasks to
initialize those signals and implement a transaction.

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The Testbench Drives the Transactor

This testbench directly accesses some interface
interface spi_if(input
spi_if(input clk);
clk);
interface signals logic
logic sdi,
logic
sdi, sdo;
sdo;
logic ce;
ce;
 This works better for complex
task
task init
init ();
();
...
...
transactions – the testbench can task
task send
send (...);
(...);
do non-routine things ...
...
endinterface
endinterface
module
module spi_test
spi_test (spi_if
(spi_if spi);
spi);
...
...
initial
initial begin
begin
spi.init;
spi.init;
spi_top spi.send(add,
spi.send(add, data);
data);
spi.ce
spi.ce <=
<= 0;
0;
spi ...
main duv1 ...
end
end
init endmodule
endmodule
P P module
send module spi_top;
spi_top;
logic
logic clock;
clock;
spi_if
spi_if spi(clk);
spi(clk); //
// interface
interface
spi_test
spi_test main(spi);
main(spi); //
// testbench
testbench
testbench interface design duv
duv duv1
duv1 (spi);
(spi); //
// design
design
ports methods ports endmodule
endmodule

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For this example, a higher level wrapper module instantiates the testbench, interface, and design
under verification.
For more complex interfaces and transactions, you may find it easier to verify the design with
direct access to the interface signals rather than relying solely upon interface methods. This permits
more control over the design stimulus, for example, you can craft fork-join blocks “on-the-fly” that
probably do not exist in the regular reusable interface methods.
Most SystemVerilog testbenches utilize this flexible approach, using a combination of interface
methods and testbench functionality.

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Utilizing a Modport
You can define a modport to interface
interface spi_if(input
spi_if(input clk);
clk);
prevent the DUV from accessing logic
logic sdi,
sdi, sdo;
the transaction interface logic
logic ce;
ce;
sdo;

A modport defines a module’s //

// interface
interface modports
modports
“view” of the interface modport
modport tb
tb (( output
output sdi,
sdi, ce,
ce, clk,
clk,
input
input sdo,
sdo,
 A module using the tb modport import
import init,
init, send
send );
);
sees sdi, ce and clk as modport
modport duv
duv (( input
input sdi,
sdi, ce,
ce, clk,
clk,
outputs and sdo as an input output
output sdo
sdo );
);
and imports the init and task
task init
init ();
();
send tasks from the interface ...
...
module
module spi_test
endtask spi_test (spi_if.tb
(spi_if.tb spi);
spi);
endtask
 A module using the duv ...
...
initial begin
modport sees sdi, ce and clk
task send
initial
task (...);
sendbegin
(...);
spi.init;
...
spi.init;
as inputs and sdo as an output
...
spi.send(add,
spi.send(add, data);
endtask data);
endtask
and cannot access the init or ...
...
endinterface
send tasks
module
module duv
endinterface duv (spi_if.duv
(spi_if.duv main);
main);
...
...
always
always @@ (( posedge
posedge main.clk)
main.clk)
...
...

11/6/2009 SystemVerilog for Verification 65

You would ideally like to define different views of the interface, to restrict what contents each user
can access, and how that user can access that contents. For an interface, such a view is called a
modport.
This example interface defines one modport for the testbench, that treats the data input signal as an
output and has access to the interface methods, and defines another modport for the design under
verification, that treats the input signal as an input and has no access to the interface methods.

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Utilizing a Clocking Block

You can place a clocking block in interface
interface spi_if(input
spi_if(input clk);
clk);
an interface logic
logic sdi,
sdi, sdo;
sdo;
logic ce;
 Interface methods can drive
logic ce;

signals via the clocking block default

default clocking
default
clocking cb1
cb1 @(posedge
@(posedge clk);
clk);
default input #1 output #3;
input #1 output #3;
input
input sdo;
 The clocking block can specify output
sdo;
output ce,
ce, sdi;
sdi;
the modport signal directions endclocking
endclocking

 Use clocking keyword in //

// interface
interface modports
modports
modport modport
modport tb
tb (clocking
(clocking cb1,
import
cb1,
import init,
init, send);
send);
 Directions are from perspective
modport
modport duv
duv (input
(input sdi,
sdi, ce,
ce, clk,
of module utilizing the modport output
clk,
output sdo);
sdo);
task
task init
init ();
();
begin
begin
cb1.ce
cb1.ce <=
<= 0;
0;
cb1.sdi
cb1.sdi <=
<= 0;
0;
##1;
##1;
end
end
endtask
endtask

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You can define clocking blocks within an interface, and interface methods can then access design
signals using the timing of the clocking block. Testbench modules can use the clocking block
through a modport. The specified direction of the clocking block signals is from the perspective of
the module connected to the modport that uses the clocking block. You would be more likely to use
a clocking block for a module that represents testbench than for a module that represents design
behavior.

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Virtual Interfaces
virtual [interface] interface_type identifier;
identifier = interface_instance;
A virtual interface is a variable that represents an interface instance
 Your test code assigns actual interface instances to the interface
variable at various time throughout the test
 assignment (=) of interface instance, interface variable, or null
 comparison (==,!=) to interface instance, interface variable, or null

 You test code can pass interface variables to tasks and functions

 Your test code procedurally accesses methods and variables (but not
nets) of that interface instance through the interface variable
 Each interface instance drives its own nets, through clocking blocks or
continuous assignments, that can reflect variable changes made by test
 Use of virtual interfaces promotes code reuse (write once, use often)

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A virtual interface is an interface variable that at various times throughout the test can represent
different interface instances. By iterating through an array of interface variables and passing each
element in turn to a test task, your one testbench task can test multiple instances of similar design
blocks, each through its own interface instance.
You can declare virtual interfaces in modules, programs, classes and packages. You can pass
virtual interfaces by value, but not be reference, to tasks and functions.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 20.8

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Virtual Interface Example

//
// Interface
Interface module
module top;
top;
interface
interface inv_if;
inv_if; inv_if
inv_if intfc1(),
intfc1(), intfc2();
intfc2();
var
var logic
logic in_var,
in_var, out_var;
out_var; inv inv1(.intfc(intfc1));
inv inv1(.intfc(intfc1));
endinterface
endinterface inv
inv inv2(.intfc(intfc2));
inv2(.intfc(intfc2));
virtual
virtual inv_if
inv_if intfc;
intfc;
task
task check (exp);
check (exp);
//
// Inverter
Inverter ...
...
module
module inv(interface
inv(interface intfc);
intfc); endtask
endtask
assign
assign intfc.out_var
intfc.out_var == !intfc.in_var;
!intfc.in_var; task
task do_test;
do_test;
endmodule
endmodule intfc.in_var
intfc.in_var == 0;0;
#1
#1 check(1);
check(1);
intfc.in_var
intfc.in_var == 1;1;
#1
#1 check(0);
check(0);
endtask
endtask
initial
initial begin
begin
intfc
intfc == intfc1;
intfc1; do_test;
do_test;
intfc
intfc == intfc2;
intfc2; do_test;
do_test;
$display("TEST
$display("TEST DONE");
DONE");
$finish(0);
$finish(0);
end
end
endmodule
endmodule

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This example defines an inverter interface and an inverter module and a test module. The test
module declares two interface instances and two inverter instances and connects each inverter to its
respective interface. It declares an interface variable and defines a test task to test the inverter
connected to the interface that the interface variable currently represents. The test block, in turn,
assigns each interface to the interface variable, and calls the test task to test the inverter connected
to that interface.

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Benefits of TBV
 You can verify designs at transaction level instead of signal level

 Allowing you to think and debug at a higher level of abstraction

 thus more quickly develop and analyze the test environment
 Rather than wading through a “sea of waveforms” at signal level

 You can partition test development into stimulus and transactors

 This isolates the test development from the design development

 Stimulus changes do not necessarily require design changes
 Design changes do not necessarily require stimulus changes

 This methodology is most effective for designs with well-defined

interfaces

11/6/2009 SystemVerilog for Verification 69

Transaction based verification is all about doing your system-level development and verification
with abstract transactions, without getting involved with an ocean of individual signal transitions.
You can partition test development into stimulus, which deals solely with transactions, and the
transactors, which do have to know about the design implementation. Personnel involved with
stimulus development can be reasonably confident that they can reuse tomorrow, their work done
yesterday, while the block designers continually refine their own designs.
This methodology works only as well as your design team adheres to a top-down design flow,
where the design specification is defined before it is implemented.
Transaction-based verification (TBV) has been used for many years. What is relatively new is the
increasing tool support, in simulators and waveform viewers, for the creation, recording and
analysis of transactions, and recently developed high-level verification languages such as e,
SystemC and SystemVerilog, that support more sophisticated transaction-based verification by
borrowing from the software world, powerful proven concepts such as object-oriented design and
dynamic resource generation.

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Summary
 Transaction Level Modelling raises abstraction level of the test

 Most of the test is not involved with low level signal transitions
 SystemVerilog interfaces are ideal for modelling transactors

 Interface methods translate between transactions and signals

 Separating testbench and design promotes portability and reuse

 Many different architectures are possible:

 Applying stimulus purely through interfaces methods is good for

simple designs and transactions
 Directly accessing interface signals may be better for complex
designs and transactions

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Pause here for a moment and review what you have learned about how SystemVerilog interfaces
support a transaction based verification methodology.

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Quiz
1. What is a transaction?

2. What components produce and consume transactions?

A] RTL Design. B] System-level Design. C] Testbench. D] B & C.

3. True of False: A transactor converts between a transaction interface and

a signal interface.

4. What features of SystemVerilog interfaces most prominently support

transaction-based verification?

Solutions in Appendix A

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About Lab 3
For this lab you use a program block, an interface and a clocking block to
test a memory design. You move the write_mem() and read_mem()
subroutines into the interface, thus making it a transactor.

TOP top_m : top_m (top_m.sv)

TEST INTERFACE MEMORY
memory_test : intfc : memory :
memory_test_p memory_if memory_m
(memory_test_p.sv) (memory_if.sv) (memory_m.sv)
write_mem()

read_mem()

clk

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Classes

Chapter 5

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Aims and Topics

Aims
 To explore classes and class-based features of SystemVerilog

Topics
 Class overview

 Properties and instances

 Constructors and methods

 Static properties and methods

 Aggregates and Inheritance

 Information hiding
 Virtual classes
 Polymorphism
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This chapter introduces the SystemVerilog Object-Oriented Programming (OOP) features, that is,
classes and their associated features. A class is a dynamic data type, declaring data variables, but
not nets, and methods to manipulate the data, that you can create and delete during run time. A
class is an excellent type for representing such things as ATM cells and ethernet packets, things for
which there might during simulation be an undetermined number of instances.
This section describes SystemVerilog's implementation of classes and only very briefly mentions
Object-Oriented Programming.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 7.

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Class Overview
 A class is a user-defined data type

 Classes define data, and methods

class
class myClass;
myClass;
(tasks/functions) to operate on the data
int
int number;
number;
 You can dynamically create and delete class endclass
endclass
objects during simulation
 You use SystemVerilog classes for temporary
class
class frame;
frame;
objects, such as transactions logic
logic [4:0]
[4:0] addr;
addr;
 SystemVerilog classes support a subset of logic [7:0] payload;
logic [7:0] payload;
Object-Oriented (OO) features: bit
bit parity;
parity;
endclass
endclass
 Abstract data modeling

 Inheritance

 Data hiding and encapsulation

 Polymorphism

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A class is a user-defined type, that declares data variables, and methods to manipulate the data, and
that you can dynamically create and delete during the simulation. You use classes for such things
as transactions, where during simulation, an undetermined number may come into being and then
disappear.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 7.3

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Variables of the Class Type

 An object is an instance of a class
class
class myClass;
myClass;
 Declare it as a variable (handle) int
int number;
number;
 “Points” to the memory endclass
endclass
representing the instance (initial
value null) myClass
myClass c1;
c1; //
// handle
handle only
only
myClass
myClass c2
c2 == new;
new; //
// handle
handle && obj
obj
 Create it using function new myClass
myClass c3
c3 == new
new c2;
c2; //
// shallow copy
shallow copy
 In the declaration or procedurally
initial
initial begin
begin
 Object persists until either: c1
c1 == new;
new; //
// object
object created
created
 Handle assigned null ...
...
c1
c1 == null;
null; //
// object
object reclaimed
reclaimed
 Handle not accessible end
end
 Goes “out of scope”
memory
 Automatic “garbage collection”
handle --
c1: number: int
F89CD7 --

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A class is a user data type. To use a class, you declare a variable of the class type. The variable is a
handle that “points” to a location in memory that holds the class properties. An uninitialized handle
has a null value. You create a class instance by calling a special class method called “new”. The
“new” method is a function that allocates an area of memory for the class properties and places a
pointer to that area in the class object handle variable.
Unlike C++, SystemVerilog automatically deletes the dynamically created object, when either you
explicitly assign the null value to the handle, or that handle “goes out of scope”, for example, when
a subroutine that declares the handle locally, returns.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 7.4

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Class Handles are “Safe” Pointers

SystemVerilog restricts what you can do with object handles
 to reduce the likelihood of user error
Note that SystemVerilog performs automatic memory management!

Operation C++ Pointer SystemVerilog

Object Handle
Arithmetic operations, e.g. incrementing allowed not allowed

For arbitrary data types allowed not allowed

Assignment to an address of a data type allowed not allowed

Dereferencing allowed not allowed

Casting unlimited limited

Default value 0 null

Memory management manual automatic

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A SystemVerilog class handle is only somewhat like a C++ pointer. SystemVerilog, for ease of
use, restricts what you can do with a class handle. Things you cannot do include:
 Arithmetic operations, for example incrementing and decrementing.
 Using with any arbitrary data type.
 Assigning the address of a variable.
 Dereferencing.
 Casting to any arbitrary pointer type.
On the other hand, SystemVerilog automatically deletes class objects that your code can no longer
access, thus helping you to prevent “memory leaks”, where you repeatedly create dynamic objects
and forget to delete them when you no longer need them.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Sections 7.5, 7.26

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Class Properties and Methods

The class type declaration also declares
class members: class
class myClass;
myClass;
int
int number;
number;
 Properties – class data
task
task set
set (input
(input int
int i);
i);
 Methods – subroutines, presumably number
number == i;
i;
to manipulate class properties endtask
endtask

 Access either using the “dot” (.) function

function int
int get;
get;
notation return
return number;
endfunction
number;
endfunction
endclass
endclass

direct access method access

myClass
myClass c1
c1 == new;
new; myClass
myClass c2
c2 == new;
new;
initial
initial initial
initial
begin
begin begin
begin
c1.number
c1.number == 4;
4; c2.set(3);
c2.set(3);
$display("c1:
$display("c1: %d",
%d", c1.number);
c1.number); $display("c2:
$display("c2: %d",
%d", c2.get());
c2.get());
end
end end
end

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The class type declaration also declares class members. The members can be variables, called
“properties”, and they can also be tasks or functions, called “methods”, to manipulate the class
properties. You reference the members of a class object by using the “dot” (.) notation.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 7.5, 7.6

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Class Versus Structure

So why not just use a struct ? struct
struct {{
logic
logic l;l;
int
int i;
i;
real
real r;
r;
}} structA;
structA;
A class provides much more:
virtual
virtual class
class Child
Child
 Dynamicism – construct / utilize / delete #(parameter
#(parameter type T=int)
type T=int)
extends
extends Parent;
Parent;
 Methods, not just variables logic
logic l;
l;
protected
protected TT t;
t;
 Data encapsulation (hiding) local
local real
real r;
r;
static
static int
int unsigned
unsigned u;
u;
 Type extension through inheritance virtual
virtual task
task doit;
doit;
endtask
endtask
 Type parameterization (generic classes) function
function new;
new;
++u;
 Polymorphism – abstract classes / virtual
++u;
endfunction
endfunction
methods / dynamic casting endclass
endclass

See following slides …

11/6/2009 SystemVerilog for Verification 79

A structure is a user-defined type, representing a collection of data. Structures offer only this
simple data grouping mechanism. You declare nets and variables of the structure type.
A class is a user-defined type, representing a collection of data and methods to manipulate the data.
Classes offer Object Oriented features, such as dynamicism, data encapsulation, class inheritance,
polymorphism, abstract classes and dynamic casting. You declare variables of the class type,
whose value is a “handle” (pointer) to a class object. The handle is initially null. You assign to the
variable the value returned by calling the class’ new() constructor method, which allocates memory
for, and constructs, a class object.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 7.5, 7.6

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External Method Definition

Purely for convenience, you can implement the class
class myClass;
myClass;
methods outside the class declaration int number;
int number;
 First, prototype the method in the class
task
task set
set (input
(input int
int i);
declaration i);
number
number == i;
i;
 extern method_prototype ; endtask
endtask
 type, name, arguments
extern
extern function
function int
int get;
 Implement the method outside the class get;
declaration, but in same scope. endclass
endclass
 Implementation must exactly match prototype
 Link using scope resolution operator (::) function
function int
int myClass::get;
myClass::get;
 <class_name>::<method_name> return number;
return number;
endfunction
endfunction

myClass
myClass c2
c2 == new;
new;
initial
initial
begin
begin
c2.set(3);
c2.set(3);
$display("c2:
$display("c2: %d",
%d", c2.get());
c2.get());
end
end
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You can implement a class method outside of the class declaration. To do this, you must first
prototype the method within the class declaration. A prototype is the extern keyword followed by
the entire method header, exactly as if you were implementing the method, but without the method
code body. You then implement the method, including the code body, outside the class declaration,
exactly as if you were implementing it within the class declaration, but with one difference. As the
method is not a member of the outside scope, but is a class member, you must declare its type as a
type of the class. You do this by prefixing the method name with the class name and the scope
resolution operator.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 7.22

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Class Constructor
Method new is a special class method called a constructor
 Defined by default for all classes
 You can reimplement it to do initialize your class properties
 No return type – otherwise like any other class method

default constructor explicit constructor explicit constructor with arguments

class
class defcon;
defcon; class
class expcon;
expcon; class
class parcon;
parcon;
int
int number;
number; int
int number;
number; int
int number;
number;
endclass
endclass
function
function new();
new(); function
function new(input
new(input int
int init);
init);
defcon
defcon c1
c1 == new;
new; number
number = 5;
= 5; number = init;
number = init;
//
// c1.number == 00
c1.number endfunction
endfunction endfunction
endfunction
endclass
endclass endclass
endclass

expcon
expcon c2
c2 == new;
new; parcon
parcon c3
c3 == new(5);
new(5);
//
// c2.number
c2.number == 55 //
// c3.number == 55
c3.number

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Properties of 2-state types initially take on the 0 value and 4-state types take on the unknown value.
You can initialize them to some other value as you declare them. To initialize properties on a per-
instance basis requires you to reimplement the constructor. The constructor is like any other
function, except that it does not have a return type, not even void.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 7.7

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Class Example
Note the following:
class
class frame;
frame;  Initial property value
logic
logic [4:0]
[4:0] addr;
addr;
logic  Constructor arguments
logic [7:0] payload;
[7:0] payload;
bit assigned to properties
bit parity
parity == 0;
0;
 Constructor calls method to
function
function new
new (input
(input int
int add,
add, dat);
dat); get updated parity value
addr = add;
addr = add;
payload
payload == dat;
dat;  Application repeatedly calls
parity
parity == par({addr,
par({addr, payload});
payload}); method to serialize frame
endfunction
endfunction
function
function bit
bit par
par (input
(input logic[12:0]
logic[12:0] ip);
ip);
return (^ip);
return (^ip);
endfunction
endfunction frame
frame one
one == new(add1,
new(add1, data1);
data1);
frame
frame two
two == new(3,
new(3, 4);
4);
function
function logic
logic [13:0]
[13:0] getframe();
getframe();
return({addr,
return({addr, payload, parity});
payload, parity}); for
for (int
(int i=0;
i=0; i<14;
i<14; i++)
i++) begin
begin
endfunction
endfunction @(negedge clk);
@(negedge clk);
endclass
endclass serial
serial == one.getframe()[i];
one.getframe()[i];
end
end

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You can initialize class properties, and the constructor can then also update those values, usually
using passed-in argument values. As SystemVerilog does not support method overloading, there
can be only one implementation of each class type’s constructor.
The frame serialization method depicted here is inefficient. A more efficient implementation would
call the getframe method once and save the value in a local variable.

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Static Properties
class
class frame;
frame; Exactly one instance of a static
static
static int
int frmcount=0;
frmcount=0; property always exists, not
int
int tag;
tag;
logic
associated with any objects
logic [4:0]
[4:0] addr;
addr;
logic
logic [7:0]
[7:0] payload;
payload; This example uses a static property
bit parity;
bit parity; to provide a unique identifier for each
new frame
function
function new(input
new(input int
int add,
add, dat);
dat);
addr = add;
addr = add;  Initially 0
payload
payload == dat;
dat;
parity
parity = par({addr, payload});
= par({addr, payload});  Incremented by constructor
tag
tag == ++frmcount;
++frmcount; one
endfunction
endfunction tag 1
frame
frame one
one == new(1,
new(1, 0);
0); addr 1
...
... payload 0
endclass
endclass frame
frame two
two == new(3,
new(3, 2);
2); parity 1 frmcount: 1

two
tag 2
addr 3
payload 2
parity 1 frmcount: 2

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Each class instance has its own unique copy of a “normal” property. Only one copy of a static
property exists, and all class instances access that same copy, in fact, you can access that copy
through the class name without having any instances of the class.
<class_name>::<static_member>
This example utilizes a static property so that it can assign a unique identity to each instance of the
class. The constructor increments the frame count and assigns the new value to each instance’s tag.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 7.8

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Static Methods
A static method knows nothing about the current object – so can access
only static properties.
class
class frame;
frame;
static
static int
int frmcount;
frmcount;
int tag; Access static members in two ways:
int tag;
logic
logic [4:0]
[4:0] addr;
addr;  Through any handle of the class
logic [7:0] payload;
logic [7:0] payload; type using the dot operator (.)
bit
bit parity;
parity;
 Through the class type name
function
function new(input
new(input int
int add,
add, dat);
dat); using the scope resolution
addr
addr == add;
add; operator (::)
payload
payload == dat;
dat;
parity
parity == par({addr,
par({addr, payload});
payload}); frame
frame one
one == new(add1,
new(add1, data1);
data1);
tag
tag == ++frmcount;
++frmcount; frame
frame two = new(3, 4);
two = new(3, 4);
endfunction int
int frames;
frames;
endfunction
initial
initial begin
begin
two
two == null;
null;
static
static function
function int
int getcount();
getcount(); frames
frames == one.getcount();
one.getcount(); //
// 22
return (frmcount);
return (frmcount); frames
frames = two.getcount(); // 22
= two.getcount(); //
endfunction
endfunction frames
frames == frame::getcount();
frame::getcount(); //
// 22
...
... end
end
endclass
endclass
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Only static methods can manipulate static properties, and they cannot manipulate anything other
than static properties. You can access static methods through any handle of the class, or through the
class name.
<class_name>::<static_member>
This example uses a static function to return the current frame count, which is a static property.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 7.9

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Current Object Handle: this

The this keyword is a handle to class
class frame;
frame;
the current class object static
static int
int frmcount;
frmcount;
int tag;
int tag;
 You can use it to reference logic
logic [4:0]
[4:0] addr;
addr;
class identifiers redeclared logic
logic [7:0] payload;
[7:0] payload;
within a local scope bit
bit parity;
parity;
 Meaningful only for non-static function
function new(input
new(input int
int addr,
addr, dat);
dat);
members this.addr
this.addr == addr;
addr;
payload
payload == dat;
This example uses the fully parity
dat;
parity == par({addr,
par({addr, payload});
payload});
qualified class property “this.addr” tag = ++frmcount;
tag = ++frmcount;
in a function that redeclares the endfunction
endfunction
“addr” identifier
endclass
endclass

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You can use the “this” keyword as a handle to the current object. Within SystemVerilog, the only
practical application is to access class identifiers that have been locally redeclared.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 7.10

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Properties of a Class Type

class
class frame;
frame; A class property can be a class instance.
logic
logic [4:0]
[4:0] addr;
addr;
logic
logic [7:0]
[7:0] payload;
payload; This example declares the “frame” class
bit
bit parity;
parity; type to represent a “pure” frame and
function
function new(input
new(input int
int add,
add, dat);
dat); instantiates it in a “tagframe” class type that
addr = add;
addr = add; also contains other data.
payload
payload == dat;
dat;
parity
parity == par({addr,
par({addr, payload});
payload}); The “tagframe” constructor must call the
endfunction
endfunction
... “frame” constructor to initialize the
...
endclass
endclass instance.
class
class tagframe;
tagframe;
frame
frame f1;
f1;
static
static int
int frmcount;
frmcount;
int tag;
int tag;
function
function new(input
new(input int
int add,
add, dat);
dat);
f1 = new (add,dat);
f1 = new (add,dat);
tag
tag == ++frmcount;
++frmcount; tagframe
tagframe one
one == new(add1,
new(add1, dat1);
dat1);
endfunction tagframe
endfunction tagframe two = new(3, 4);
two = new(3, 4);
...
...
endclass
endclass one.f1.addr = 0;
one.f1.addr = 0;

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Your class type declaration can itself declare handle variables of other class types. This is known
as an aggregate class type.
In this example, the tagframe class type declaration declares a handle variable of the frame class
type. The tagframe constructor calls the frame constructor to initialize the frame object within the
tagframe object. You can say that the tagframe object “has” a frame object, much as a truck “has”
an engine.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 7.11

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Aggregation and Inheritance

Aggregation tagframe frame
frame addr
 A class type instantiates the frmcount payload
handles of other class types – tag parity
new() new()
relationship “has a” getcount() getframe()
 Containing class constructor
initializes handles tagframe

Inheritance base class

data / methods
 A class type inherits the addr
members of another class type payload
parity
– relationship “is a” new()
getframe()
 Subclass type extends
incremental
superclass type data / methods
 SystemVerilog supports single frmcount
inheritance (one super) tag
new()
getcount()

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Your class type declaration can extend the declaration of another class type. This is known as class
inheritance. The parent class type declaration is known as the superclass or base class, and the
extended child type declaration is known as the subclass or derived class. SystemVerilog supports
inheritance of only a single parent class type.
In this example, the tagframe class type declaration extends the frame class type declaration. The
tagframe constructor calls the frame constructor to initialize the parent class’ part of its variable
set. You can say that the tagframe object “is” a frame object, much as a truck “is” a vehicle, albeit
one with additional properties.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Sections 7.11, 7.12

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Simple Inheritance
super class  Subclass inherits superclass members:
class
class frame;
frame;
logic
logic [4:0]
[4:0] addr;
addr;  Can add more members
logic
logic [7:0]
[7:0] payload;
payload;
bit
bit parity;
parity;  Can redeclare superclass methods
function
function new(input
new(input int
int add,
add, dat);
addr = add;
dat);  A subclass type is the superclass type –
addr = add;
payload
payload == dat;
dat; syntax to access members is identical
parity
parity == par({addr,
par({addr, payload});
payload});
endfunction
endfunction
 e.g. a truck is a vehicle
...
 Subclass constructor automatically calls
...
endclass
endclass
superclass constructor
sub- class  For this example, entry into
tagframe.new() immediately
class
class tagframe
tagframe extends
extends frame;
static
static int
int frmcount;
frmcount;
frame;
implicitly calls frame.new()
int
int tag;
 Why is this a problem?
tag;

function
function new;
tag
new;
tag == ++frmcount;
++frmcount;  Error tagframe
tagframe one
one == new;
new; //???
//???
endfunction
endfunction
...
...
endclass one.addr
one.addr == 0;
0;
endclass
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An object of the subclass can by default access all the members of the superclass as if they were
members of the subclass. The subclass can redeclare superclass methods and variables, and objects
of the subclass will by default access their own versions of those members. The subclass can also
declare additional property and method members.
Implicit subclass constructors, upon entry, immediately first call the constructors of their
superclass. These implicit constructor calls do not know anything about your constructor
arguments. If you reimplement the superclass constructor to accept arguments, then you must also
reimplement the subclass constructor to provide those arguments to the superclass constructor.
--------
This example illustrates the failure to do that.

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Inheritance and Constructors

super class
class
class frame;
frame; The superclass (frame) constructor
logic
logic [4:0]
[4:0] addr;
addr; takes arguments.
logic
logic [7:0]
[7:0] payload;
payload;
bit
bit parity;
parity; The subclass (tagframe) constructor
function
function new(input
new(input int
int add,
add, dat);
dat);
must on the first line pass these
addr
addr == add;
add; arguments to its super class.
payload
payload == dat;
dat;
parity
parity == par({addr,
par({addr, payload});
payload});  Use super keyword to access
endfunction
endfunction super’s version of redeclared
...
...
endclass
member methods
endclass

sub- class
class
class tagframe
tagframe extends
extends frame;
frame;
static int frmcount;
static int frmcount;
int
int tag;
tag;
tagframe
tagframe one
one == new(add1,
new(add1, data1);
data1);
tagframe two = new(3, 4);
tagframe two = new(3, 4);
function
function new(input
new(input int
int add,
add, dat);
dat);
super.new(add, dat); one.addr
super.new(add, dat); one.addr == 0;
0;
tag
tag == ++frmcount;
++frmcount;
endfunction
endfunction
...
...

11/6/2009 SystemVerilog for Verification 89

In this example, the reimplemented subclass constructor, upon entry, immediately explicitly calls
its superclass constructor to pass “up” the initialization arguments. Use the super keyword within a
subclass to reference the superclass version of the member methods that the subclass has
redeclared.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 7.16

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Multi-Layer Inheritance
You can layer inheritance to frame class
class frame;
frame;
base class

multiple generations: addr

logic
logic [4:0]
logic
[4:0] addr;
addr;
logic [7:0]
[7:0] payload;
payload;
payload bit
bit parity;
 All frame objects have
parity;
parity
address, payload and parity new() function
function new(int
...
new(int add,
add, int
int dat);
dat);
getframe() ...
endfunction sub-class
 A tagframe object is a
endfunction
...
...
class tagframe
class tagframe extends
extends frame;
frame;
frame object that also has a
endclass
endclass
static
static int
int frmcount;
frmcount;
tagframe int
int tag;
tag and a frame count
tag;
frmcount
function
function new(input
new(input int
int add,
add, dat);
dat);
tag
 A errframe object is a new()
super.new(add,dat);
super.new(add,dat);
...
... sub-class
tagframe object that has an getcount() ...
...
endclass
error count and provides a class
class errframe
static
errframe extends
endclass
int
extends tagframe;
errcount;
static int errcount;
tagframe;

corrupt frame errframe

function
function new(input
new(input int
int add,
add, dat);
dat);
errcount
 Each subclass constructor
super.new(add,dat);
super.new(add,dat);
new() endfunction
endfunction
explicitly calls its superclass getframe()
function
function logic
logic [13:0]
[13:0] getframe;
getframe;
constructor to pass //return
//return frame
frame with
with error
error
arguments “up”
endfunction
endfunction
...
...
endclass
endclass

11/6/2009 SystemVerilog for Verification 90

You can layer inheritance to an undetermined number of levels. Each subclass constructor must,
upon entry, immediately call the constructor of its superclass, using the “super” keyword. As there
is no such thing as “super.super”, you can reference only one higher level at a time.

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Data Encapsulation (Hiding)

parent class Restricting “outside” access to members is
class
class frame;
frame;
local
local logic
logic [4:0]
[4:0] addr;
addr; a key feature of Object-Oriented design.
local
local logic
logic [7:0]
[7:0] payload;
payload;
protected
protected bitbit parity;
parity;  All members are by default “public” –
sub-class accessible externally
function
function new(int
new(int add,
add, int
int dat);
dat);
...
...
class
class tagframe
tagframe extends
extends frame;
frame;  Use the local keyword to make a
endfunction
...
endfunction
local
local static
static int
int frmcount;
frmcount; member visible only to class methods
... int
int tag;
tag;
 Use the protected keyword to make
endclass
endclass
function
function new(int
new(int add, int sub-class
add, int dat);
dat);
super.new
super.new (add,dat);
(add,dat); a member visible only to class
class
...
class errframe extends tagframe;
... errframe extends tagframe; methods and methods of subclasses
... local
local static
static int
int errcount;
errcount;
...
...
endclass
...
endclass
function
function void
void add_error;
add_error;
parity
parity == ~parity;
~parity; errframe
errframe one
one == new(add1,
new(add1, data1);
data1);
errcount++;
errcount++;
endfunction
endfunction one.errcount
one.errcount == 0;
0; //
// ??
??
one.parity
one.parity == 1;
1; //
// ??
??
static
static function
function int
int geterrcount();
geterrcount(); one.add_error; // ??
one.add_error; // ??
return (errcount);
return (errcount); no_errs
no_errs == one.errcount;
one.errcount; //
// ??
??
endfunction
endfunction no_errs
no_errs == errframe::geterrcount;
errframe::geterrcount; //
// ??
??
...
...
endclass
endclass
11/6/2009 SystemVerilog for Verification 91

SystemVerilog class members are by default “public”, that is, code external to the class type
declaration can access them. Data encapsulation, or “hiding”, is an important tenet of Object-
Oriented Programming. You can declare class members “private” using the local keyword. Only
member methods of the class type declaration can access those private members. You can declare
other class members using the protected keyword. Only member methods of the class type
declaration and their subclasses can access those protected members.
In this example the frame class parity variable is protected, so only the frame class and its
subclasses can access that variable. Application code cannot access the parity variable. The
tagframe class frame count is local, so only methods declared within the tagframe class can access
the frame count.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 7.17

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Virtual Methods and Dynamic Look-Up

A base class handle can “point to” an object of any of its derivations.
Calls to a normal method resolve Calls to a virtual method
to the handle class, if resolve to the object class, if
implemented there, else the implemented there, else the
frame
nearest higher class where nearest higher class where
addr
implemented, i.e. compile-time payload implemented, i.e. run-time
resolution. parity resolution.
class new()
class frame;
frame; class
class frame;
frame;
/*virtual*/function getframe()
/*virtual*/function frame
frame virtual
virtual function
function frame
frame
getframe();
getframe(); getframe();
getframe();
...
... ...
...
endfunction
endfunction tagframe endfunction
endfunction
endclass
endclass frmcount endclass
endclass
tag
frame
frame frm_h,
frm_h, tmp_h;
tmp_h; new() frame
frame frm_h,
frm_h, tmp_h;
tmp_h;
tagframe
tagframe tag_h=new(1,2);
tag_h=new(1,2); getcount() tagframe
tagframe tag_h=new(1,2);
tag_h=new(1,2);
errframe
errframe err_h=new(3,4);
err_h=new(3,4); errframe
errframe err_h=new(3,4);
err_h=new(3,4);
...
... errframe ...
...
frm_h=tag_h;
frm_h=tag_h; frm_h=tag_h;
frm_h=tag_h;
tmp_h=frm_h.getframe(); errcount tmp_h=frm_h.getframe();
tmp_h=frm_h.getframe(); tmp_h=frm_h.getframe();
frm_h=err_h; new() frm_h=err_h;
frm_h=err_h; frm_h=err_h;
tmp_h=frm_h.getframe(); getframe() tmp_h=frm_h.getframe();
tmp_h=frm_h.getframe(); tmp_h=frm_h.getframe();
11/6/2009 SystemVerilog for Verification 92

You can use a handle of a superclass type to “point” to objects of its subclasses. Remember that
any of the subclass type declarations can redeclare members of its superclass, thus creating a
hierarchy of member method implementations.
For a “normal” method, the compiler selects which version to use based upon the handle type, so a
handle of the superclass type, even if it “points” to a subclass object, accesses the methods declared
in the superclass type.
For a virtual method, the compiler creates a look-up table, so that during simulation, the method
implementation is selected based upon the subclass type of the object that the superclass handle
happens to “point” to during the method call, so a handle of the superclass type, if it “points” to a
subclass object, accesses the methods declared in that subclass type. This mechanism is called
“polymorphism”, literally, “having many forms”.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 7.20

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“Pure” Virtual Methods and Virtual Classes

virtual
super-class A virtual class exists only as a
virtual class
class frame;
frame;
local
local logic
logic [4:0]
[4:0] addr;
addr; superclass – you cannot instantiate it
local
local logic
logic [7:0]
[7:0] payload;
payload;
protected
protected bit
bit parity;
parity;  Also known as an “abstract” class
virtual
virtual function
function logic
logic [13:0]
[13:0] getframe;
getframe;
endfunction
endfunction
...
... Only a virtual class may have “pure”
virtual methods
endclass
endclass sub-class

class
class tagframe
tagframe extends
extends frame;
frame;
 Prototype only – no implementation
...
...
function  Subclass provides implementation
function logic
logic [13:0]
[13:0] getframe;
getframe;
//define for tagframe
//define for tagframe  You instantiate the subclass
endfunction
endfunction
endclass sub-class
endclass
class
class errframe
errframe extends
extends tagframe;
tagframe; frame
frame one
one == new(1,
new(1, 2);
2); //
// error
error
...
... tagframe
tagframe two
two == new(3,
new(3, 4);
4);
function
function logic
logic [13:0]
[13:0] getframe;
getframe; errframe
errframe three
three == new(5,
new(5, 6);
6);
//define for errframe
//define for errframe frm = two.getframe;
frm = two.getframe;
endfunction
endfunction frm
frm == three.getframe;
three.getframe;
endclass
endclass

11/6/2009 SystemVerilog for Verification 93

You can use the “virtual” keyword to declare a class type that cannot be instantiated. A virtual
class type declaration would presumably declare the base variables upon which some other class
type declaration that can be instantiated would build. A class you cannot instantiate is called an
“abstract” class.
Only an abstract class can declare “pure” virtual methods. A pure virtual method is a method
declared with the virtual keyword, and prototyped, but not implemented. As it has no code body,
you can declare it only in a class type that cannot be instantiated. A subclass type declaration must
inherit the pure virtual method and provide its implementation. Only at a level in the class type
declaration hierarchy where all pure virtual methods have been implemented, can you instantiate
an object of that subclass type.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 7.19

The IEEE draft standard P1800/D9 proposes the “pure” keyword be added to optionally indicate a
pure virtual function.

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Class Parameters
You can parameterize a class class
class stack
stack #(parameter
#(parameter type
type st
st == int);
int);
declaration just like you local st data[100];
local st data[100];
parameterize an interface, static
static int
int depth;
depth;
module, or program. A parameter
task
task push(input
push(input st
st indat...
indat... );
can be a value or any arbitrary );
...
type – hence “template class”. ...
endtask
endtask
 You can override parameter task
task pop(
pop( output
output st
st outdat
outdat ...
... );
);
values and types on an per- ...
...
endtask
instance basis endtask
endclass
endclass
 Methods using type
parameters must work for all //
// int
int stack
stack (default)
(default)
stack
stack intstack
intstack == new;
expected type overrides new;

 Each combination of //
// 8-bit
8-bit vector
vector stack
stack
parameter types has its own stack
stack #(logic[7:0]) bytestack
#(logic[7:0]) bytestack == new;
new;
set of any static variables
 They can share static
variables from an inherited
non-templated superclass
11/6/2009 SystemVerilog for Verification 94

You can define a parameterized class, for example a queue, for which you can override the width,
depth, and even the type, of the data that it contains, on a per-instance basis.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 7.23

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Summary
With the SystemVerilog Object-Oriented testbench features, you can:
 Declare dynamic data types
 Create and destroy objects during simulation

 Declare hierarchical data types

 Building up “layers” of types promotes reuse

 Encapsulate data with protected and local class members

 Hiding your data from external methods simplifies maintenance of the type

 Raise the level of abstraction for building testbenches

 You can develop and debug the test environment more quickly

Other SystemVerilog features are also “class-like”

 Random constraints

 Covergroups

11/6/2009 SystemVerilog for Verification 95

Pause here for a moment and review what you have learned about how the SystemVerilog object-
oriented testbench features help you to define temporary objects, such as transactions.

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Quiz
1. What is the role of a class constructor?

2. What is the difference between a static and non-static property?

3. What is the difference between a static and non-static method?

4. What is inheritance?

5. What is the difference between a protected and a local class member?

6. Give an example of polymorphism.

Solutions in Appendix A

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About Lab 4
For this lab you explore the support
SystemVerilog provides for object-
counter_c
oriented design:
# count : int
 Class declaration + new ( int )
+ putval ( int ) : void
 Class constructor + getval () : int
 Class properties and class
methods
 Class aggregates upcounter_c downcounter_c

 Static class members

+ new ( int ) + new ( int )
 Polymorphism + next() : int + next() : int

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Random Stimulus

Chapter 6

November 6, 2009

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Aims & Topics

Aims
 To explore stimulus creation with random number generators

Topics
 Random and directed stimulus

 Pseudo-random number generators and seeding

 Unsigned random numbers

 Scope randomization
 Constraints
 randcase
 randsequence

11/6/2009 SystemVerilog for Verification 99

This chapter explores SystemVerilog features for randomization of variables and randomly
selecting statements for execution.

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CPU Coverage Testcase

Let’s look at a simplified 8-bit CPU having:
 7 immediate instructions
 ADDI, SUBI, ANDI, XORI, JMP, JMPC, CALL

 4 registers
 REG0, REG1, REG2, REG3

 In the following double byte format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
| X | X | X |- opcode -|- reg -|- - - - - - data - - - - - - -|

11/6/2009 SystemVerilog for Verification 100

Let’s take a look at why you might want to generate random stimulus and constrain it to
meaningful sets of values.

The CPU instruction contains an 8-bit data field, a 2-bit register field to address four registers, and
a 3-bit opcode field to specify one of seven immediate instructions.

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CPU Instruction Stimulus

Declare opcode and register values as enumerated types.
Assign values – pass to transactor …
Problem: How to test combinations of opcode, register and data?

typedef
typedef enum
enum {ADDI,
{ADDI, SUBI,
SUBI, ANDI,
ANDI, XORI,
XORI, JMP,
JMP, JMPC,
JMPC, CALL}
CALL} opcode_t
opcode_t ;;
typedef
typedef enum
enum {REG0,
{REG0, REG1,
REG1, REG2,
REG2, REG3}
REG3} regs_t
regs_t ;;

opcode_t
opcode_t opcode;
opcode;
regs_t
regs_t regs;
regs;
logic[7:0]
logic[7:0] data;
data;

initial
initial begin
begin
//generate
//generate stimulus
stimulus
opcode
opcode == ADDI;
ADDI;
regs
regs == REG0;
REG0;
data
data == 5;
5;
//pass
//pass toto transactor
transactor

11/6/2009 SystemVerilog for Verification 101

We can declare enumerated types for the opcode and reg values. We assume that a transactor will
translate the opcode, reg and data values into a form where they can be applied to the design with
the correct format and timing, all we have to do is to generate values for the three variables and
pass them to the transactor.

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Looped CPU Instruction Stimulus

typedef
typedef enum
enum {ADDI,
{ADDI, SUBI,
SUBI, ANDI,
ANDI, XORI,
XORI, JMP,
JMP, JMPC,
JMPC, CALL}
CALL} opcode_t
opcode_t ;;
typedef
typedef enum
enum {REG0,
{REG0, REG1,
REG1, REG2,
REG2, REG3}
REG3} regs_t ;
regs_t ;

opcode_t
opcode_t opcode;
opcode; Use nested loops to
regs_t
regs_t regs;
regs; index through the
logic[7:0] data;
logic[7:0] data;
7168 combinations
initial
initial
for
for (opcode=opcode.first();
(opcode=opcode.first(); opcode<=opcode.last();
opcode<=opcode.last(); opcode=opcode.next())
opcode=opcode.next())
for (regs=regs.first(); regs<=regs.last(); regs=regs.next())
for (regs=regs.first(); regs<=regs.last(); regs=regs.next())
for
for (data=0;
(data=0; data<=255;
data<=255; ++data)
++data) ADDI REG0 00 - FF
@(posedge clk);
@(posedge clk); ADDI REG1 00 - FF
...
... ADDI REG2 00 – FF
ADDI REG3 00 - FF
SUBI REG0 00 – FF
SUBI REG1 00 – FF
SUBI REG2 00 – FF
SUBI REG3 00 - FF
AND1 REG0 00 – FF
...

11/6/2009 SystemVerilog for Verification 102

A simple approach uses nested loops to generate all possible values over the ranges of the three
variables.
The outer loop iterates over the opcode values, the middle loop over the reg addresses, and the
inner loop over the range of data values.

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Looped Stimulus Coverage Analysis

Structured stimulus does not thoroughly test CPU functionality
Misses most transitions between value combinations
 What if ADDI followed by JMP causes out-of-range error?

Structural Metrics look good! Functional Metrics do not!

REG0 REG1 REG2 REG3 ADDI:ADDI  REG0:REG1 

ADDI     ADDI:SUBI  REG1:REG2 
SUBI     ADDI:ANDI  REG2:REG3 
ANDI     ADDI:XORI  REG0:REG2 
XORI     ADDI:JMP  REG1:REG3 
JMP     ADDI:JMPC  ...
JMPC     ...

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We then measure the structural and functional coverage of the 7168 patterns. Structural metrics,
consisting of coverpoints and cover crosses in a covergroup (see a later chapter), look good – we
have applied every possible value to each variable. Functional metrics, consisting of cover
statements with design properties (see a later chapter), do not look good. We have missed most of
the transitions between values.
Applying all such transitions requires a much more complex set of stimulus loops!
What we really want to do is to generate random sequences of operations, registers and data, and
constrain those random combinations to meaningful combinations.

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Randomization and Constraints

SystemVerilog provides a new set of constructs for generating and
constraining random variables
 Random generation allows minimal code to generate many data sets

 Constraints restrict the data set to meaningful data

 You can apply randomization (with constraints) to:

 Local variables
 Called “scope” randomization

 Class-based randomization

11/6/2009 SystemVerilog for Verification 104

With randomization, you can with minimal testbench code produce large amounts of stimulus that
thoroughly and effectively verifies the design.
With constraints, you can restrict the generated values and value transitions to those that are
meaningful.
SystemVerilog offers two forms of randomization:
 Randomization of local variables, covered in this chapter, and
 Randomization of class properties, covered in the next chapter.

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Pseudo-Random Number Generators

Pure random number sequences
fixed error cannot be verified
are useless for verification random if sequence does not repeat

 Sequence must be repeatable

Sim1: 2 5 1 1 6 6 7 0 7 4 3 8
 Allows debug-fix-debug cycle Sim2: 6 2 4 5 4 2 6 0 4 1 5 3
Sim3: 4 4 1 7 3 3 2 8 5 7 3 2

Verification uses pseudo-random pseudo-random

sequences
Seed = 4
 Controlled by seed(s) Sim1: 4 5 2 1 0 5 1 3 2 1 8 7
 Using the same seed generates Sim2: 4 5 2 1 0 5 1 3 2 1 8 7
Sim3: 4 5 2 1 0 5 1 3 2 1 8 7
the same sequence
 Using a different seed Seed = 7
generates a different sequence Sim1: 2 5 6 1 3 2 1 7 4 5 3 5
Sim2: 2 5 6 1 3 2 1 7 4 5 3 5
Sim3: 2 5 6 1 3 2 1 7 4 5 3 5

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A truly random sequence of values is largely useless for verification and debug of digital designs.
For verification and debug of digital designs, we need a pseudo-random repeatable sequence.
These sequences are generated algorithmically. The algorithm is typically a function that accepts a
seed reference as an argument, and when called, generates a new seed, from which it returns a the
new random value. Ensuring that the seed has the same initial value, ensures that the random
sequence is the same.

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Unsigned Random Numbers

$urandom
 Generates 32 bit random unsigned integer
$urandom_range
 Generates 32 bit random unsigned integer within a specified range

int
int value;
value;
bit
bit [63:0]
[63:0] addr;
addr;

value
value == $urandom();
$urandom(); //
// 32
32 bit
bit random
random number
number
value = $urandom(8);
value = $urandom(8); //
// 32
32 bit
bit random
random number
number with
with seed
seed
addr
addr == {$urandom,$urandom};
{$urandom,$urandom}; //
// 64
64 bit
bit random
random number
number

value
value == $urandom_range(10,2);
$urandom_range(10,2); //
// 32
32 bit
bit random
random number
number from
from 22 to
to 1010
value
value == $urandom_range(16);
$urandom_range(16); // 32 bit random number from 0
// 32 bit random number from 0 to 16 to 16
value
value == $urandom_range(1,9);
$urandom_range(1,9); //
// 32
32 bit
bit random
random number
number from
from 11 to
to 99

ranges are automatically

re-ordered to (max, min)

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If all you want is a random integer value, you can use the new $urandom() system function to
obtain a random unsigned 32-bit integer, or the new $urandom_range() system function to
constrain the value to a range of values. These functions differ from the Verilog $random()
function, in that they return unsigned values rather than signed values, and that the random
sequences are independent of each other.
--------
function int unsigned $urandom [ (int seed) ] ;
function int unsigned $urandom_range(int unsigned maxval, int
unsigned minval=0);

IEEE Std. 1800-2005 SystemVerilog LRM, Section 13.12

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Randomizing Scope Variables

You can randomize singular
variables of any integral type //type
//type declarations
declarations as
as before
before
opcode_t
opcode_t opcode;
opcode;
 Pass variables to function regs_t
regs_t regs;
regs;
std::randomize() logic[7:0] data;
logic[7:0] data;
int
int ok;
 Returns 1 on success ok;

 variables can randomize for

for (int
(int ii == 0;
0; i<7168;
i<7168; i++)
i++)
 constraints can be met begin
begin
ok
ok == randomize(opcode,
randomize(opcode, regs,
regs, data);
data);
 Otherwise returns 0 @(posedge
@(posedge clk);
clk);
end...
end...
std is a built-in
package automatically
implicitly imported

11/6/2009 SystemVerilog for Verification 107

You can randomize only singular integral variables. For example, you cannot randomize unpacked
structures, real variables, or any nets.
--------
[std::]randomize ( [variable_identifier_list] ) [ with
{constraint_expression [; constraint_expression] } ] ;

IEEE Std. 1800-2005 SystemVerilog LRM, Section 13.11

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Random Stability
Each design unit instance, class instance and process thread has its own
independent Random Number Generator (RNG)
 Each package and instance of interface, module or program RNG is
seeded with the implementation-dependent initial seed (usually 1)
 The RNG of each static thread or class object is upon creation seeded
with the next random value of its parent design unit’s RNG
 The RNG of each dynamic thread or class object is upon creation
seeded with the next random value of its parent thread’s RNG
 The RNG of thread and class objects are stable to the extent that their
creation order and randomization order is stable
 Add new threads and class objects and randomization calls after previous
threads and class objects and randomization calls or explicitly initialize the
RNGs

11/6/2009 SystemVerilog for Verification 108

Each design unit instance, class instance and process thread has its own independent Random
Number Generator (RNG).
 Each package and instance of interface, module or program RNG is seeded with the
implementation-dependent initial seed, usually 1.
 The RNG of each static thread or class object is upon creation seeded with the next random
value of its parent design unit’s RNG.
 The RNG of each dynamic thread or class object is upon creation seeded with the next random
value of its parent thread’s RNG.
 The RNG of thread and class objects are stable to the extent that their creation order and
randomization order is stable.
• To maintain random stability, add new threads and class objects and randomization calls
after previous threads and class objects and randomization calls, or explicitly initialize the
RNGs.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 13.13

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Setting the Random Seed

You can guarantee random stability by using the srandom() method to
manually seed the Random Number Generator (RNG) of the process
<process>.srandom(seed)
process::self.srandom(seed)

initial
initial
self() is a static function of //set
the built-in process class that
//set aa seed
seed at
at the
the start
start
returns the process handle
process::self.srandom(100);
process::self.srandom(100);
aa == randomize(x);
randomize(x);
...
...
end
end

11/6/2009 SystemVerilog for Verification 109

This example uses the self() static function of the process class to obtain a process handle
“pointing” to itself, and through that handle calls its srandom() function to set its random seed.
A SystemVerilog process is a class, but severely restricted. A process is either static, created with
the always or initial keywords; or dynamic, created with the fork keyword. You cannot instantiate a
process, or create it on-the-fly with the new keyword. In fact, you can do very few class-like things
with a process.
--------
class process;
enum state {FINISHED, RUNNING, WAITING, SUSPENDED, KILLED};
static function process self();
function state status();
function void kill();
task await();
function void suspend();
task resume();
endclass

IEEE Std. 1800-2005 SystemVerilog LRM, Section 13.12.3

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Thread Seeding Application

You can spawn multiple
concurrent threads using integer
integer a,
a, x,
x, y,
y, z;
z;
...
...
fork…join fork
fork
Each thread maintains its own begin
begin //
// use
use thread’s
thread’s initial
initial seed
seed
random number generator #($urandom_range(2,0))
#($urandom_range(2,0)) aa == randomize(x);
randomize(x);
end
end
 Seeded from the parent
begin
begin //
// set
set seed
seed at
at the
the start
start of
of thread
thread
 Can be manually reseeded process::self.srandom(100);
process::self.srandom(100);
#($urandom_range(2,0))
#($urandom_range(2,0)) aa == randomize(y);
randomize(y);
Values from each thread are end
end
dependent on the thread
hierarchy order but not on the begin
begin //
// use
use initial
initial seed
seed then
then set
set new
new seed
seed
#($urandom_range(2,0)) a = randomize(z);
thread execution order. #($urandom_range(2,0)) a = randomize(z);
process::self.srandom(200);
process::self.srandom(200);
#($urandom_range(2,0))
#($urandom_range(2,0)) aa == randomize(z);
The random sequence for end
randomize(z);
end
threads before the change in the
thread hierarchy does not //
// ADD
ADD MORE
MORE THREADS
THREADS HERE
HERE --
-- NOT
NOT ABOVE!
ABOVE!
change. join
join

11/6/2009 SystemVerilog for Verification 110

The initial seed of each process’ RNG is the next random value of its parent RNG. This allows you
to declare static processes and spawn dynamic processes after all previous processes have been
declared or spawned, without disturbing the RNG of previous processes. This also allows you to
shuffle entire hierarchies around if you use the srandom() void function to manually set the initial
seed of the hierarchy root.
This example illustrates two important features:
 Hierarchical seeding – the RNG of each forked thread is seeded from the next random value of
the parent’s thread RNG.
 Thread stability – the sequence of values for x, y and z are dependent upon their order in the
hierarchy, but not dependent on the order of process execution.

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Constraint Blocks
Use the with clause to attach a constraint block {…} containing:
 Constraint expressions
 Constraint expression ordering

//type
//type declarations
declarations as
as before
before
opcode_t
opcode_t opcode;
opcode;
regs_t
regs_t regs;
regs;
logic[7:0]
logic[7:0] data;
data;
int
int ok;
ok;

//
// conditions:
conditions: data
data only
only between
between 32
32 and
and 126
126
ok
ok == randomize(data)
randomize(data) with
with {data>=32;
{data>=32; data<=126;};
data<=126;};

//
// range:
range: opcode
opcode in
in range
range of
of ADDI
ADDI to
to SUBI
SUBI or
or JMP
JMP to
to JMPC
JMPC
ok
ok == randomize(opcode)
randomize(opcode) with { opcode
with { opcode inside {[ADDI:SUBI],[JMP:JMPC]};};
inside {[ADDI:SUBI],[JMP:JMPC]};};

//
// distribution:
distribution: REG0-REG1
REG0-REG1 twice
twice as
as likely
likely as
as REG2-REG3
REG2-REG3
ok
ok = randomize(regs) with { regs dist { [REG0:REG1]:=2, [REG2:REG3]:=1};};
= randomize(regs) with { regs dist { [REG0:REG1]:=2, [REG2:REG3]:=1};};

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A constraint block can contain constraint expressions and statements defining an order in which to
solve the constraints. The constraint expression can be almost any integral expression. It cannot
have side-effects, so you cannot use assignment operators in a constraint expression. The functions
you call in a constraint expression are further restricted. Refer to the LRM section 13.4.11 for those
restrictions.
--------
constraint_block_item ::=
solve identifier_list before identifier_list ;
| constraint_expression

IEEE Std. 1800-2005 SystemVerilog LRM, Section 13.4

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Conditional Constraints
Constraint expressions use two constructs for conditional constraints:
 implication: expression -> constraint_set
 if (expression) constraint_set [else constraint_set]

logic[7:0]
logic[7:0] data;
data;
...
...
//
// Randomize
Randomize data
data with
with values
values << 100
100 when
when mode
mode is
is small
small
//
// Randomize
Randomize data
data with
with values
values >> 200
200 when
when mode
mode is
is large
large
// Don’t constrain data if mode is not small or
// Don’t constrain data if mode is not small or large large
ok
ok == randomize(data)
randomize(data) with
with
{mode
{mode == small
== small ->
-> data
data << 100;
100;
mode
mode == large -> data >> 200;};
== large -> data 200;};

//
// Payload
Payload can
can be
be constrained
constrained in
in the
the same
same way
way with
with if/else
if/else
ok
ok == randomize(data) with
randomize(data) with
{{ if
if (mode
(mode ==
== small)
small) data
data << 100;
100; else
else
if
if (mode == large) data > 200; };
(mode == large) data > 200; };

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It is very common to have the constraints upon a variable dependent upon the value of another
variable. You can express this dependency using the SystemVerilog implication operator (->)
and/or the if…else construct. Nothing about these constructs is specific to constraints. We mention
them here because you will almost always use them in constraint blocks of any significant
complexity.
--------
constraint_expression ::=
expression_or_dist ;
| expression –> constraint_set
| if ( expression ) constraint_set [ else constraint_set ]
| foreach ( array_identifier [ loop_variables ] ) constraint_set

IEEE Std. 1800-2005 SystemVerilog LRM, Sections 14.4.5, 13.4.6

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Random Weighted Case: randcase

You can use randcase to randomly select a statement for execution
 You can provide different probabilities (weights) for each branch
 non-negative integral expressions that may be constant or variable

for
for (int
(int i=0;
i=0; i<50;
i<50; i++)
i++) for
for (int
(int i=0;
i=0; i<50;
i<50; i++)
i++)
begin
begin begin
begin
randcase
randcase randcase
randcase
20
20 :: gen_atm;
gen_atm; aa :: gen_atm;
gen_atm;
30 : gen_ethernet;
30 : gen_ethernet; aa ++ bb :: gen_ethernet;
gen_ethernet;
10
10 :: gen_ipv4;
gen_ipv4; aa -- bb :: gen_ipv4;
gen_ipv4;
55 :: gen_crc_error;
gen_crc_error; bb :: gen_crc_error;
gen_crc_error;
endcase
endcase endcase
endcase

Probability(gen_crc_error) = 5/65 ~ 8%

11/6/2009 SystemVerilog for Verification 113

You can use the randcase keyword to randomly select a statement for execution.
You can provide different probabilities, that is, weights, for each branch.
The randcase weights are non-negative integral expressions that may be constant or variable. An
item that you do not weight assumes the weight of 1. A weight of 0 indicates that the item shall
never be selected.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 13.15

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Random Sequence Generation: randsequence

You can use randsequence to start item
execute a random sequence of
statements based on rules called randsequence
randsequence (( main
main ))
a production list non-
main
main :: arith stk
arith stk last;
last;
arith : inc |
arith : inc | dec;dec;
terminals
Production list items are either: stk
stk :: push
push || pop;
pop;
inc
inc :: { do_inc(); };
{ do_inc(); };
 Terminal – indivisible items dec
dec :: {{ do_dec();
do_dec(); };};
that need no more definition terminals push
push :: { do_push(); };
{ do_push(); };
pop
pop :: {{ do_pop();
do_pop(); };};
 Non-terminal – defined in last
last :: {{ do_check();
do_check(); }; };
endsequence
terms of terminals and other endsequence
non-terminals
 All productions ultimately valid combinations
decompose into terminal
do_inc() do_push() do_check()
productions do_dec() do_push() do_check()
do_inc() do_pop() do_check()
do_dec() do_pop() do_check()

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You can use the randsequence keyword to execute a random sequence of statements based on rules
called a production list. The argument to the randsequence construct is the identifier of the
production to start with. This defaults to the first listed production.
Each production consists of a function declaration, with optional argument and return type
declarations, followed by a colon, followed by rules for the production, where rules are separated
by the bitwise OR (|) operator.
Each rule is a production list of one or more productions, and may have a weight associated with it,
and may have a code block associated with it.
A code block is data declarations and statements between curley brackets ({}).
Each randsequence construct creates its own automatic scope, which means that production
declarations are not visible outside of the randsequence construct. Furthermore, each code block
creates an anonymous automatic scope, so its declarations are also not visible outside the code
block.
The sequence in this example starts with the main production, which defines one production rule
consisting of the arithmetic (arith), stack (stk), and last productions, in sequence. The arithmetic
production defines the increment (inc) and decrement (dec) alternative rules, each equally likely to
be selected. The stack production defines the push and pop alternative rules, each also equally
likely to be selected.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 13.16.

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Random Production Weights

You can apply weights to production items to influence randomization
 The default weight is 1
 Apply weights with the := operator

 Weights apply to alternatives separated with ‘|’

randsequence
randsequence (( main
main ))
inc is twice as
main
main :: arith
arith stk
stk last;
last;
likely as dec
arith
arith :: inc:=2
inc:=2 || dec:=1;
dec:=1;
stk
stk :: push:=3
push:=3 || pop;
pop;
inc
inc :: { do_inc(); };
{ do_inc(); }; push is thrice
dec
dec : { do_dec();
: { do_dec(); }; }; as likely as pop
push
push :: {{ do_push();
do_push(); };};
pop
pop : { do_pop();
: { do_pop(); }; };
last
last :: {{ do_check();
do_check(); }; };
endsequence
endsequence

11/6/2009 SystemVerilog for Verification 115

You can weight production alternatives. These are the relative weights of production rules within a
production list, and do not weight the production list itself relative to any other production list.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 13.16.1

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Production Statements: case, if-else, repeat

randsequence
randsequence (( main
main )) very limited
main : constructs in
main : repeat(5) arith
repeat(5) arith stk
stk last;
last;
arith productions
arith :: ifif (incr)
(incr) inc;
inc; else
else dec;
dec;
stk
stk : case (which)
: case (which)
0:
0: push;
push;
1:
1: pop;
pop; less limited
endcase;
endcase; constructs in
inc
inc :: {{ do_inc();
do_inc(); }; }; code blocks
dec
dec : { do_dec();
: { do_dec(); }; };
push
push :: {{ do_push();
do_push(); }; };
pop
pop :: {{ do_pop();
do_pop(); }; };
last
last :: {{ do_check();
do_check(); }; };
endsequence
endsequence

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A production list may contain a restricted set of procedural constructs. It may contain the case and
if...else constructs to make the production conditional, and may contain the repeat construct to
repeat the production a number of times.
Contrast this with code blocks, which may contain arbitrary procedural constructs.

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Aborting Productions: break, return

You can use break and return in
code blocks to abort productions randsequence(test)
randsequence(test)
test:
test: run1
run1 run2;
run2;
 break terminates the entire run1: A
run1: A B;B;
randsequence production run2:
run2: BB C;
C;
A: { if(i==1)
 return aborts the generation
A: { if(i==1)
//
// exit
exit item
item AA
of current production only return;
return;
$display("A");
$display("A"); }; };
B: { if(i==2)
B: { if(i==2)
//
// exit
exit randsequence
randsequence
break;
break;
$display("B");
$display("B"); }; };
C: { $display("C");
C: { $display("C"); }; };
endsequence
endsequence

i == 1 produces B B C
i == 2 produces A

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Your code blocks can use the break keyword and the return keyword to abort productions. These
keywords have special semantics within a randsequence construct. Within a randsequence
construct, the break keyword terminates the entire randsequence production, and not just any loop
it happens to be in, and the return keyword terminates only the current production. As every
production declaration is a local function declaration, and every production item is a task call, the
code block of a production item can utilize those arguments and can return a value.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Sections 13.16.2, 13.16.3

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Passing Values Between Productions

A production definition is similar to a function definition:
[function_data_type] production_identifier [(tf_port_list)]:rs_rule{|rs_rule};

A production item is similar to a task call:

production_identifier [ ( list_of_arguments ) ]

 You can access passed arguments throughout the production scope

 You can access returned values after the production item (in the scope)

randsequence
randsequence (( main
main ))
main
main : arith($urandom)
: arith($urandom) {$display(arith);}
{$display(arith);} stk
stk last;
last;
int
int arith(int
arith(int i)i) :: inc(i)
inc(i) {return
{return inc;}
inc;} || dec(i)
dec(i) {return
{return dec;};
dec;};
stk
stk :: push
push || pop;
pop;
int
int inc(int
inc(int i)i) :: {{ return
return do_inc(i);
do_inc(i); };
};
int
int dec(int
dec(int i)i) :: {{ return
return do_dec(i);
do_dec(i); };
};
push
push : { do_push(); };
: { do_push(); };
pop
pop :: {{ do_pop();
do_pop(); };};
last
last :: {{ do_check();
do_check(); }; };
endsequence
endsequence

11/6/2009 SystemVerilog for Verification 118

The syntax for declaring a production is similar to the syntax for declaring a function. However, a
production is not a function; the production code block can consume time.
The syntax for passing data to a production is similar to a task call.
A production for which you have declared a type can return data. You return the data in the return
statement. The data is available as the production item name after the production item “call” in the
“calling” production.
This example passes a random number to the arithmetic production and displays the returned value.
The arithmetic production further exchanges this value with either the increment or decrement
production. The increment and decrement productions each call a function to implement their
operation.

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Summary
With these simple randomization features, you can:
 Generate large amounts of stimulus data from compact code
 Run longer simulations with more stimulus
 that more thoroughly tests the design
 Spend more of your own time crafting directed tests of corner cases

 Constrain the values of the random variables

 To create legal stimulus
 To explore areas of interest
 To conditionally switch between modes of operation

 Use randcase to randomly select a statement to execute

 Use randsequence to execute a random sequence of statements

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You can use these SystemVerilog randomization features to easily generate large amounts of
meaningful stimulus from very compact code, stimulus that more thoroughly tests the more easily
controlled and observed functionality of the design, while allowing you to spend your time crafting
directed tests to verify the less easily controlled and observed functionality of the design.
Pause here for a moment and review what you have learned about the simple SystemVerilog scope
randomization features.

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Quiz
Define the output for each value of i:

randsequence()
randsequence()
top
top :: AA B;
B;
AA :: CC DD E;
E;
BB :: CC EE {{ if
if (i
(i ==== 11 )) return;
return; }} D;
D;
CC :: {$display("C"); if(i == 3) return;};
{$display("C"); if(i == 3) return;};
DD :: {if
{if (i(i ==
== 22 )) return;
return; $display("D");};
$display("D");};
EE :: {if
{if (i(i ==
== 00 )) break;
break; $display("E");};
$display("E");};
endsequence
endsequence

i == 0 produces ?
i == 1 produces ?
i == 2 produces ?
i == 3 produces ?
Solutions in Appendix A

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About Lab 5
For this lab you randomize the data that the memory testbench writes to the
memory. You use scope variable randomization with an in-line constraint
block. Your constraint expressions will use “inside” expressions and
distributions.

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Class-Based Random Stimulus

Chapter 7

November 6, 2009

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Aims & Topics

Aims
 To explore stimulus creation with random number generators on class
properties

Topics
 Randomization of class properties

 Pre- and post-randomize methods

 In-line control

 Constraints

 Setting seeds

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This chapter explores randomization of class hierarchies. For this, SystemVerilog provides
additional capabilities, such as the pre_randomize() and post_randomize() methods, enabling and
disabling randomization on a per-property basis, and enabling and disabling individual named
constraint blocks.

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Random Class Properties

You declare integral class properties random using rand and randc
 rand – random variables uniformly distributed values over their range

 randc – random-cyclic variables cycle through the values in a random

permutation of their declared range, without repetition
 randc limited to bit and enumerated types and implementation may limit length

class
class RandClass;
RandClass;
rand
rand bit
bit [1:0]
[1:0] x;
x;
randc bit [1:0] y;
randc bit [1:0] y;
endclass
endclass

rand randc
x: Each valid value (00,01,10,11) y: Each valid value (00,01,10,11)
has an equal probability of being won’t repeat until all 4 values
chosen of 1/4. have been cycled through.
01 11 00 10 // Valid 01 11 00 10 // Valid
01 11 01 10 // Valid 01 11 01 10 // Error

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The following are direct quotes of portions of IEEE Std. 1800-2005 section 13.3. These portions
are quoted here because there is no way to more concisely or better explain the rand and randc
keywords:
 “The solver can randomize singular variables of any integral type.”
 “Variables declared with the rand keyword are standard random variables. Their values are
uniformly distributed over their range.”
 “Variables declared with the randc keyword are random-cyclic variables that cycle through all
the values in a random permutation of their declared range. Random-cyclic variables can only
be of type bit or enumerated types and can be limited to a maximum size.”
 “To reduce memory requirements, implementations can impose a limit on the maximum size of
a randc variable, but it should be no less than 8 bits.”
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 13.3

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Randomizing Class Objects: randomize()

Randomize the properties by calling the randomize() member function
 Every class has a built-in randomize() virtual member function
 You cannot redeclare the built-in randomize() virtual member function

module
module test;
test;

class
class RandClass;
RandClass; x is a random variable
rand
rand bit
bit [1:0]
[1:0] x;
x;
randc
randc bit
bit [1:0]
[1:0] y;
y; y is a random-cyclic variable
endclass
endclass

RandClass
RandClass myRand
myRand == new;
new; Randomizes all rand
and randc variables in
initial
initial class object
begin
begin
int
int success;
success;
success
success == myRand.randomize();
myRand.randomize();
end
end

endmodule
endmodule :: test
test

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Every class has a built-in virtual member function called randomize(), that returns an int value of 1
to indicate successful randomization, or 0 to indicate randomization failure. You cannot redeclare
this function.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 13.5.1

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pre_randomize() and post_randomize()

randomize() automatically calls the member functions:
 pre_randomize() before objects are randomized
 post_randomize() after objects are randomized

You can reimplement these functions to do whatever is needed …

function
function void
void pre_randomize;
pre_randomize;
if
if (super)
(super) super.pre_randomize();
super.pre_randomize();
.. .. ..
endfunction
endfunction

function
function void
void post_randomize;
post_randomize;
if
if (super)
(super) super.post_randomize();
super.post_randomize();
.. .. ..
endfunction
endfunction

11/6/2009 SystemVerilog for Verification 126

The randomize() function of the class automatically calls the void pre_randomize() and
post_randomize() functions of the class. You can redeclare these functions to do whatever you
want to do before and after the class object is randomized.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 13.5.2

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Application of pre_randomize()

class
class RandClass;
RandClass;
rand
rand bit
bit [1:0]
[1:0] x;
x;
randc Overrides built-in
randc bit
bit [1:0]
[1:0] y;
y; pre_randomize()
function void pre_randomize();
function void pre_randomize();
$display("x
$display("x was
was ",x,"
",x," yy was
was ",y);
",y);
endfunction
endfunction
endclass
endclass

RandClass
RandClass myRand
myRand == new;
new;
randomize()
initial
initial automatically calls
begin
begin pre_randomize()
int
int success;
success; before randomizing
success variables
success == myRand.randomize();
myRand.randomize();
$display("x
$display("x now
now ",
", myRand.x,,
myRand.x,,
"y
"y now
now ",
", myRand.y);
myRand.y);
end
end

11/6/2009 SystemVerilog for Verification 127

In this example, the class declaration reimplements the pre_randomize() function to display the
values of its variables just before they are assigned their next random value.

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In-Line Random Variable Control

You can select specific class variables to randomize
 randomize(…) with arguments randomizes specified variables only

class
class RandClass;
RandClass;
rand x, y are random variables
rand bit
bit [0:1]
[0:1] x;
x; //random
//random variables
variables
randc bit [1:0]
randc bit [1:0] y;
y;
bit
bit [1:0]
[1:0] a,
a, b;
b; //
// state
state variables
variables a, b are not random variables
endclass
endclass

RandClass
RandClass myRand
myRand == new;
new; randomize x and y only.
a and b not randomized.
initial
initial
begin
begin
int
int success;
success;
randomize x only.
success
y, a, b not randomized.
success == myRand.randomize();
myRand.randomize();
success
success == myRand.randomize(x);
myRand.randomize(x); randomize x and a only.
success = myRand.randomize(x,a);
success = myRand.randomize(x,a); y and b not randomized.
success
success == myRand.randomize(a,b);
myRand.randomize(a,b);
end
end
randomize a and b only.
x and y not randomized.

11/6/2009 SystemVerilog for Verification 128

Providing variable reference arguments to the randomize() function randomizes only those
variables, regardless of whether you declare the variables rand or randc. Randomization of state,
that is, non-random, variables, is performed in the normal fashion, that is, not random-cyclic.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 13.6

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Controlling Randomization: rand_mode()

Use the rand_mode() function to find if randomization is enabled:
int = object.random_variable.rand_mode()

 Applies to random (rand or randc) class properties

 Including properties that are themselves classes

 By default enabled for random variables

Use the rand_mode() task to disable and enable randomization:

object[.random_variable].rand_mode(bit on_off)

 Applies to class variables in the module scope

 Applies to random (rand or randc) class properties

 Including properties that are themselves classes

11/6/2009 SystemVerilog for Verification 129

The rand_mode() methods apply only to random properties of a class.

Use the rand_mode() function to determine whether randomization is enabled.
Use the rand_mode() task to disable and enable randomization of the random class properties. If
you specify only the class object and not the properties, it applies to all random properties of the
class object. If you also specify a random property, it applies only to that one property, even if the
property is of a class type. Setting the mode of a random property of a class type does not affect the
mode of its contained variables, but can affect whether or not they are randomized.
The LRM section 13.4.8 describes the algorithm for determining what to randomize. That
algorithm is approximately:
 First, from the object that called randomize(), recursively select contained class objects that are
declared rand and are enabled.
 Next, from this set of selected class objects, select the enabled constraints.
 Last, from the set of selected class objects, select the variables that are declared rand or randc
and are enabled.
You can also apply these methods to individually indexed elements of an unpacked array and
individual members of an unpacked structure providing that the array or structure are random class
properties.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 13.7

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Application of rand_mode()

class
class RandClass;
RandClass; x and y are
rand
rand bit
bit [0:1]
[0:1] x;
x; //random
//random variables
variables random vars
randc
randc bit
bit [1:0]
[1:0] y;
y;
bit [1:0]
bit [1:0] a,
a, b;
b; //
// state
state variables
variables
endclass
endclass
disable randomization of
RandClass
RandClass myRand
myRand == new;
new; all random variables of
class object
initial
initial
begin
begin re-enable y
int
int success,
success, state;
state; randomization
myRand.rand_mode(0);
myRand.rand_mode(0);
myRand.y.rand_mode(1);
myRand.y.rand_mode(1); y randomization
state
state == myRand.y.rand_mode();
myRand.y.rand_mode(); is enabled
success=myRand.randomize();
success=myRand.randomize();
state
state == myRand.a.rand_mode();
myRand.a.rand_mode(); only y randomized
end
end
error – a is not a
random variable

11/6/2009 SystemVerilog for Verification 130

In this example, the class handle variable is not a class member variable, so cannot be declared
rand. rand and randc apply only to class member variables. After disabling randomization of all
random properties of the class object, the example re-enables randomization of one of its members.
Subsequent randomization of the class object then randomizes only the one member variable that is
still active.

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Constraint Blocks
Constraints restrict the random data generation to meaningful values
A constraint expression can be almost any integral expression
 Cannot have side effects – e.g. no assignment operators

class
class RandClass;
RandClass;
rand
rand bit
bit [1:0]
[1:0] x;
x; Constrains x to the
randc bit [1:0]
randc bit [1:0] y;
y; values 01,10,11
constraint
constraint c1
c1 {{ xx !=
!= 2’b00;}
2’b00;}
endclass
endclass
; after constraint
expression but not
RandClass
RandClass myRand
myRand == new;
new; after constraint line

initial
initial
begin
begin Randomize x using
int
int success;
success; constraint block c1
success
success == myRand.randomize();
myRand.randomize();
$display("x
$display("x now
now ",
", myRand.x,,
myRand.x,,
"y
"y now ", myRand.y);
now ", myRand.y);
end
end

11/6/2009 SystemVerilog for Verification 131

You declare a constraint as a class member with the constraint keyword, followed by an identifier,
followed by constraint block items enclosed within a set of curley ({}) braces. Constraint block
items can be constraint expressions and can be statements ordering the constraint solution.
Constraint expressions can be almost any integral expression. They are restricted to not have side
affects, so you cannot use the assignment operators. The use of functions is also restricted. For
these restrictions on functions please refer to section 13.4.11
--------
constraint_declaration ::=
[ static ] constraint constraint_identifier constraint_block
constraint_block ::=
{ { constraint_block_item } }
constraint_block_item ::=
constraint_expression
| solve identifier_list before identifier_list ;

IEEE Std. 1800-2005 SystemVerilog LRM, Section 13.4

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Constraint Block Inheritance

Constraints are class members – are inherited along with other members

class
class RandClass;
RandClass;
rand
rand bit
bit [1:0]
[1:0] x;
x;
randc c1 constrains x to not be 00
randc bit
bit [1:0]
[1:0] y;
y;
constraint
constraint c1
c1 {{ xx !=
!= 2’b00;}
2’b00;}
endclass
endclass

class
class RandClassX
RandClassX extends
extends RandClass;
constraint
RandClass; c2 constrains x to not be 11
constraint c2
c2 {{ xx !=
!= 2’b11;}
2’b11;}
endclass
endclass

RandClassX
object of extended class
RandClassX myRand
myRand == new;
new;

initial
initial
begin
begin
int
int success;
success; x will be 01 or 10
success
success == myRand.randomize();
myRand.randomize();
$display("x
$display("x now
now ",
", myRand.x,,
myRand.x,,
"y
"y now ", myRand.y);
now ", myRand.y);
end
end

11/6/2009 SystemVerilog for Verification 132

Constraints are class members and are inherited along with all other inherited class members.
This example declares a class type with random variables and constraints on those random
variables, then extends the class to add additional constraints. Objects of the extended class type
utilize both sets of constraints.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 13.4.2

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Constraint Expressions: Set Membership

The inside operator is particularly useful in constraint expressions.

class
class RandClass;
RandClass;
rand
rand int
int x;
x; c1 constrains x to
randc
randc bit
bit [1:0]
[1:0] y;y; the set 3,7,11-20
constraint
constraint c1 {x inside
c1 {x inside {3,
{3, 7,
7, [11:20]};}
[11:20]};}
endclass
endclass

RandClass
RandClass myRand
myRand == new;
new;

initial
initial
begin
begin
int
int success;
success;
success
success == myRand.randomize();
myRand.randomize();
$display("x
$display("x now
now ",
", myRand.x,,
myRand.x,,
"y now ", myRand.y);
"y now ", myRand.y);
end
end

11/6/2009 SystemVerilog for Verification 133

A constraint expression using the inside operator constrains the value of the random variable to be
inside a list of one or more value ranges. A value range can be a single expression, or two
expressions enclosed by square brackets ([]) and separated by a colon (:).
--------
constraint_expression ::=
expression_or_dist ;
| expression –> constraint_set
| if ( expression ) constraint_set [ else constraint_set ]
| foreach ( array_identifier [ loop_variables ] ) constraint_set

inside_expression ::= expression inside { open_range_list }

IEEE Std. 1800-2005 SystemVerilog LRM, Section 8.19

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Constraint Expressions: Weighted Distributions

Provide a weighted set of values (distribution) with the dist keyword
 Default weight is 1
101 to 200
 := assigns weight to the item or every value in a range each get a
weight of 200
constraint c1 {x dist {[101:200]:=200};}
101 to 200
 :/ assigns weight to the item or to a range as a whole each get a
weight of 2
constraint c1 {x dist {[101:200]:/200};} (200/100=2)

class
class RandClass;
RandClass;
rand
rand int
int x;
x;
randc
randc bit [1:0]
bit [1:0] y;y;
constraint
constraint c1 c1 {x
{x dist
dist {7:=5,
{7:=5, [11:20]:=3,
[11:20]:=3, [26:30]:/1};}
[26:30]:/1};}
endclass
endclass

7 has a weight of 5 11-20 each have 26-30 each have

a weight of 3 a weight of 1/5

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A constraint expression using the dist operator also constrains the value of the random variable to
be inside a list of one or more value ranges. The dist operator differs from the inside operator, in
that you can weight the value ranges. Using different weighting operators, you can apply the
weight expression either to every value in the range, or to the range as a whole. For any range that
consists of a single expression, either operator has the same effect. The default weight is 1.
--------
expression_or_dist ::= expression [ dist { dist_list } ]
dist_list ::= dist_item { , dist_item }
dist_item ::= value_range [ dist_weight ]
dist_weight ::= := expression | :/ expression

IEEE Std. 1800-2005 SystemVerilog LRM, Section 13.4.4

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Constraint Expressions: Conditional Constraints

Constraint expressions can use two constructs for conditional constraints:
 implication: expression -> constraint_set
 if (expression) constraint_set [else constraint_set]

class
class RandClass1;
RandClass1; class
class RandClass2;
RandClass2;
rand
rand int
int x;
x; rand
rand int
int x;
x;
bit
bit mode;
mode; bit
bit mode;
mode;
constraint
constraint c1c1 constraint
constraint c2 c2
{{ {{
mode
mode ==
== 11 ->
-> xx << 100;
100; if
if (mode
(mode ==== 1)
1)
mode == 0 -> x > 10000;
mode == 0 -> x > 10000; xx << 100;
100;
}} else
else
endclass
endclass xx >> 10000;
10000;
}}
endclass
endclass

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It is very common to have the constraints upon a variable dependent upon the value of another
variable. You can express this dependency using the SystemVerilog implication operator (->)
and/or the if…else construct. Nothing about these constructs is specific to constraints. We mention
them here because you will almost always use them in constraint blocks of any significant
complexity.
--------
expression –> constraint_set
if ( expression ) constraint_set [ else constraint_set ]

IEEE Std. 1800-2005 SystemVerilog LRM, Sections 13.4.5, 13.4.6

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Constraint Expressions: Iterative Constraints

You can use a loop variable to “customize” each array element’s constraint
 foreach ( array_identifier [ loop_variables ] ) constraint_set

class
class RandClass2;
RandClass2;
rand
rand int
int A[];
A[];
constraint
constraint c1
c1 {{ foreach
foreach (A[i])
(A[i]) (i
(i <=
<= A.size()/2)
A.size()/2) ->
-> A[i]
A[i] <=
<= i;
i; }}
constraint
constraint c2
c2 {{ foreach
foreach (A[i])
(A[i]) (i
(i >> A.size()/2)
A.size()/2) ->
-> A[i]
A[i] >=
>= i;
i; }}
endclass
endclass

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You can use a loop variable to “customize” each array element’s constraint. The foreach construct
iterates over the elements of an array. This is especially useful for an array for which you do not
know the size. Of course you can always just use the size() method to obtain the size.
--------
foreach ( array_identifier [ loop_variables ] ) constraint_set

IEEE Std. 1800-2005 SystemVerilog LRM, Sections 13.4.7

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Ordering the Constraint Solution

Variables are randomized – then
constraints are checked (this goes on class
class UNORDERED;
UNORDERED;
until a solution is found or the random rand
rand bit
bit myBit;
myBit;
rand
rand int
int myInt;
space is exhausted) constraint
myInt;
constraint c1
c1
 First the randc variables {{
myBit
myBit ->
-> myInt
myInt ==
== 0;
0;
 Then the rand variables }}
How is this a problem? endclass
endclass

 Constraint expression solution is

bidirectional (no implied order) class
class ORDERED;
rand
ORDERED;
rand bit
bit myBit;
myBit;
 {myBit -> myInt == 0;} rand
rand int
int myInt;
myInt;
 myBit will almost never be 1 constraint
constraint c1
c1
{{
 or if myBit is further constrained to myBit
myBit ->
-> myInt
myInt ==
== 0;
0;
1, solver may run long to find answer solve
solve myBit before myInt;
myBit before myInt;
}}
Order using: solve … before … endclass
endclass
 Applies to rand variables only

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Class variables declared rand are evaluated simultaneously, and then constraints are applied to
select the valid subset of all possible combinations. This can cause almost all candidate solutions to
be discarded. For example, solving for a bit and an int gives 233 different combinations. Only one
of those satisfies the constraint that the int must be 0 if the bit is 1.
You can control the solution order by using the solve…before… statement. If you solve the bit
constraint first, the int will be unconstrained half the time. The other half of the time, the solver
needs to try only 232 combinations, at worst, and intelligent implementations will recognize that
there really isn’t any more solving to do.
Keep in mind the following restrictions:
 You cannot order randc variables.
• The solver solves randc variables first, then ordered rand variables, then unordered rand
variables.
 You can order only rand variables of integral types.
 You must avoid circular dependencies (e.g {solve a before b; solve b before c; solve c before
a;})
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 13.4.9

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Controlling Constraints: constraint_mode()

Use the constraint_mode() function to find if the constraint is enabled:
function int object.constraint_name.constraint_mode()

Use the constraint_mode() task to enable/disable constraints:

task object[.constraint_name].constraint_mode(bit on_off)

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You can disable and re-enable all constraints of the class object, or just individual constraints.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 13.8

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Application of constraint_mode()

class
class RandClass;
RandClass; blue constrains x to not 00
rand
rand bit
bit [0:1]
[0:1] x;
x;
constraint
constraint blue {x
blue {x !=
!= 2’b00;}
2’b00;}
constraint
constraint green
green {x{x !=
!= 2’b11;}
2’b11;}
endclass
endclass green constrains x to not 11

RandClass
RandClass myRand
myRand == new;
new;

initial disable all class

initial object constraints
begin
begin
int
int state,
state, success;
success;
myRand.constraint_mode(0); re-enable blue
myRand.constraint_mode(0);
myRand.blue.constraint_mode(1); constraint
myRand.blue.constraint_mode(1);
state
state == myRand.green.constraint_mode();
myRand.green.constraint_mode();
success state of constraint
success == myRand.randomize();
myRand.randomize();
end green is still 0
end

x will be 01, 10, 11

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This example declares two constraint block members of the class. It disables all constraints of the
class object, then enables just one of the constraints of the class object. The other constraint
remains disabled.

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Setting the Random Seed: srandom()

Use the srandom() class method to
class
class RandClass;
manually seed the Random Number
RandClass;
rand
rand int
int x;
x;
Generator (RNG) function
function new
new (int
(int seed=5);
seed=5);
this.srandom(seed);
this.srandom(seed);
<handle>.srandom(seed) endfunction
endfunction
obj.srandom(seed) endclass
endclass

this.srandom(seed) RandClass
RandClass myRand
myRand == new(7);
new(7);
or just srandom(seed)
initial
initial
 Use to get different random begin
begin
sequences with each run
int
int success;
success;
success
success == myRand.randomize();
myRand.randomize();
 Use to preserve random sequences myRand.srandom(9);
myRand.srandom(9);
between hierarchy changes success
success == myRand.randomize();
myRand.randomize();
end
end

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This example passes an initial random seed into the class object’s constructor. The constructor calls
the object’s srandom() method to set the random seed, overriding the initial random seed obtained
from its parent module. The test process later changes the object’s seed again, this time calling the
srandom() method through the class variable.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 13.12.3

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Summary
With these class randomization features, you can:
 Generate large amounts of stimulus data from compact code
 Run longer simulations with more stimulus
 that more thoroughly tests the design
 Spend more of your own time crafting directed tests of corner cases

 Constrain the values of the random variables

 To create legal stimulus
 To explore areas of interest
 To conditional switch between modes of operation

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Pause here for a moment and review what you have learned about the SystemVerilog class
randomization features.

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Quiz
The randomize call randomizes which variables?

class ClassA; ClassC objC = new;

randc bit bitA;
rand byte byteA; initial
endclass begin
objC.rand_mode(0);
class ClassB; objC.objB.intB.rand_mode(0);
randc byte byteB; objC.objB.rand_mode(1);
rand int intB; assert (objC.randomize());
ClassA objA = new; end
endclass

class ClassC;
rand int intC;
real realC;
rand ClassB objB = new;
endclass

Solutions in Appendix A

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About Lab 6
For this lab you randomize the data that the memory testbench writes to the
memory. You use class property randomization with an in-class constraint
block. Your constraint expressions will use “inside” expressions and
distributions. You will weight the distribution of data values and solve for
data values before solving for address values.

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Covergroup Coverage

Chapter 8

November 6, 2009

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Aims and Topics

Aims
 Introduce coverage using SystemVerilog Covergroups

Topics
 Introduction to functional coverage

 Simple coverage

 Automatic and user-defined bins

 Cross products
 Coverage options

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This chapter introduces SystemVerilog data-oriented functional coverage.

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Structural and Functional Coverage

Structural metrics (code coverage) are
tool-instrumented monitors to check: typedef
typedef enum
enum
{add,
{add, sub, divide}
sub, divide} t_opcode;
 Execution of design blocks, lines or t_opcode;
statements
Code add 
 Assignment of values to variables coverage sub 
divide 
Functional metrics are user-defined
scenarios to check: Functional add;sub;divide 
coverage 
 Assignment of sequences of values add;divide;sub
to variables add;add;add;add 
sub;sub;sub;divide 
 Stepping of the design through
control states (transactions)

Functional coverage complements but

does not replace code coverage

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Code coverage automatically measures whether, and potentially how many times, a line, statement,
block or branch has executed. More advanced code coverage can measure whether, and potentially
how many times, an expression term has a chance to control the outcome of the expression. Code
coverage does not automatically check transitions between design states, as the transition space is
extremely large
That sort of check may be important. You, as the designer, may know that two consecutive
SUBTRACT operations followed by a DIVIDE operation has caused an overflow error on previous
designs similar to yours. This is where user-directed functional coverage becomes imperative.
Functional coverage, as the name suggests, checks whether the test exercises the functionality of
the design. You identify the critical combinations and sequences that should be exercised to verify
the design functionality.

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Two Kinds of Functional Coverage

SystemVerilog has two types of functional coverage
 Covergroups for data-oriented functional coverage
 This chapter focuses on data-oriented functional coverage

 SystemVerilog Assertions (SVA) for control-oriented functional

coverage
 A later chapter introduces control-oriented functional coverage

covergroup functional coverage Property functional coverage

covergroup
covergroup cg cg @(posedge
@(posedge clk);
clk); property
property req_gets_gnt;
req_gets_gnt;
Addr:
Addr: coverpoint addr
coverpoint addr @(posedge
@(posedge clk)
clk)
{{ bins
bins low
low == {{ [0:’h0F],
[0:’h0F], 1919 };
}; req
req |-> ##[1:$] gnt;
|-> ##[1:$] gnt;
bins
bins mid[] = { 16, 17, 18 };
mid[] = { 16, 17, 18 }; endproperty
endproperty
bins
bins high
high == {{ [’h14:’hFF]
[’h14:’hFF] };}; }} cover
cover property
property (req_gets_gnt);
(req_gets_gnt);
AddrXvalid : cross Addr,
AddrXvalid : cross Addr, valid;valid;
endgroup
endgroup
cg
cg cg1
cg1 == new;
new;

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SystemVerilog offers both data-oriented functional coverage and control-oriented functional

coverage. This chapter focuses on data-oriented functional coverage. Later chapters introduce
SystemVerilog Assertions (SVA), which provide control-oriented functional coverage. The training
module “SystemVerilog Assertions” covers SystemVerilog assertions in greater detail.

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Data-Oriented Functional Coverage

Some key aspects of data-oriented functional coverage:
 It is user-specified – not automatically inferred from the design
 You write a test plan capturing the functionality to be tested
 Based on the design specification
 Independent of and prior to the actual design implementation
 Less likely to verify “what I built” rather than “what I should have built”
 You construct data value and data value transition scenarios reflecting that
functionality
 What this chapter is all about!

 The simulator measures whether (and optionally how many times) the
test has caused the design variables of interest to hit or sequence
through those scenarios
 It is purely a testbench construct – no concern about synthesis!

11/6/2009 SystemVerilog for Verification 148

Working with the design specification, you develop a test plan highlighting those data values,
combinations of values, and sequences of values, whose occurrence provides an indication of how
thoroughly the test exercises the design. You then translate those test plan items into the
SystemVerilog data-oriented functional coverage syntax. The simulator keeps these counts and
saves them in a database for an analysis tool to present to you.

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Defining a Coverage Model

Define a coverage model using
the covergroup keyword module
module example;
example;
 Define a sampling event logic
logic clk;
clk;
logic
logic [2:0] opcode;
[2:0] opcode;
 Define a coverpoint for logic [7:0] address;
logic [7:0] address;
each integral expression to
track covergroup
covergroup cg1
cg1 @(posedge
@(posedge clk);
clk);
 Instantiate the coverage c1: coverpoint opcode;
c1: coverpoint opcode;
model in the design using new c2:
c2: coverpoint
coverpoint address;
address;
endgroup : cg1
endgroup : cg1
 You can reuse covergroup
declarations in multiple
contexts cg1
cg1 cover_inst
cover_inst == new;
new;
...
...
The simulator “bins” coverpoint endmodule
endmodule
values into a coverage database

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You can declare a covergroup in a package, interface, module, program or class.

You declare a coverage event, which is usually the Verilog event expression, but can also be a
block event expression indicating the start or the end of a given named block, task, function, or
class method.
You declare as coverpoints those variables whose values you want to track. You can optionally
define specific variable values and/or ranges of values to track.
You instantiate the covergroup anywhere you can declare a variable.
The simulator “bins” the coverpoint values and stores this information in a coverage database.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 18.2

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Automatic Bins
The simulator tracks occurrences
of coverpoint values – on each module
module example;
example;
sample clock it increments the logic
logic clk;
clk;
associated “bin”. By default: logic
logic [2:0] opcode;
[2:0] opcode;
logic [7:0] address;
 One for each coverpoint value logic [7:0] address;
 Up to a preset limit covergroup
covergroup cg1
cg1 @(posedge
@(posedge clk);
clk);
 Named auto[<value>] c1: coverpoint opcode;
c1: coverpoint opcode;
c2:
c2: coverpoint
coverpoint address;
address;
endgroup : cg1
endgroup : cg1

cg1
cg1 cover_inst
cover_inst == new;
new;
...
...
endmodule
endmodule

opcode bins c1.auto[0] c1.auto[1] c1.auto[2] c1.auto[7]

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SystemVerilog by default automatically creates a single bin for every value in the coverpoint
variable range. These are called automatic, or implicit, bins. For an enumerated coverpoint, there is
one bin for each valid value. For an integral coverpoint variable, the number of automatic bins is at
most 2M where M is the number of bits required to represent the variable. When 2M is greater than
the preset limit, the values are distributed as evenly as possible, with the last bin getting any extra
values. Later slides show how to define bins and how to change the preset limit for automatic bin
creation.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 18.4.2

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Explicit Bins
You can define the bins yourself:
 To track only a subset of c1:
c1: coverpoint
coverpoint var1
var1 {{
values bins
bins VV == {1,
{1, 2,
2, 5}
5} ;;
 To control what values }}
increment which bin
bin V increments for var1 = 1, 2 or 5

Use the bins keyword, and

provide a: value set examples

 bin name
{{ [0:5],
[0:5], 10
10 }} -- values
values 0-5
0-5 and
and 10
10
{{ [0:5],
[0:5], [9:14]
[9:14] }} –– values 0-5 and 9-14
values 0-5 and 9-14
 list of value ranges {{ ’h1,
’h1, ’h2,
’h2, ’hF
’hF }} –– values
values 1,
1, 2,
2, 15
15
{{ [1:9], [7:12]
[1:9], [7:12] }} –– range
range overlap allowed
overlap allowed
 a range can be a single value {{ [16:$]
[16:$] }} -- range
range 16
16 to
to max
max value
value
 occurrence of listed value
increments bin

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You can explicitly declare bins enclosed in curley braces ({}) immediately after the coverpoint
identifier. Note that if you do not explicitly specify coverpoint bins or options, you terminate the
coverpoint declaration with a semicolon, but if you do explicitly specify coverpoint bins or options,
you instead terminate each bin or option specification itself with a semicolon.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 18.4

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Explicit Scalar and Vector Bins

You can define scalar or vector bins
scalar example
 Scalar bin cs: coverpoint var1
cs: coverpoint var1 { {
 A single bin //
// bin
bin VV increments
increments for
for 1,1, 22 or
or 55
bins
bins VV == {1,
{1, 2,
2, 5}
5} ;;
 Incremented for all values in
}}
value range list
 Vector bin (array of bins) creates a single bin cs.V
 A unique bin for each value in
the range list
vector example
 Incremented when variable cv:
cv: coverpoint var1 {{
coverpoint var1
takes the corresponding value //
// bins
bins V[1],
V[1], V[2]
V[2] and
and V[5]
V[5]
 You can mix scalar and vector bins V[] = {1, 2, 5}
bins V[] = {1, 2, 5} ; ;
bins for the same coverpoint }}

[] for multiple bins

creates 3 bins cv.V[1], cv.V[2], cv.V[5]

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A scalar bin is one bin that counts occurrences of any of the values in its open range list.
A vector bin is an array of bins, by default one array element for each unique value in the open
range list.

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Examples of Explicit Bins

For a single coverpoint variable, you can explicitly specify (for example):
a) An illegal bin for values that are illegal even if they appear in other bins
b) An ignore bin for other values you want ignored even if in other bins
c) A single bin for all the values in a range list
d) A fixed number of bins for the entries in the range list
e) A separate bin for each unique value in a given range list
f) A default bin for all remaining values

logic
logic [3:0]
[3:0] var1;
var1;

ce:
ce: coverpoint
coverpoint var1
var1 {{
illegal_bins
illegal_bins aa == {{ 0,0, 15
15 };
}; //
// 11 bin
bin for
for illegal
illegal values
values
ignore_bins b = { [13:15]
ignore_bins b = { [13:15] }; }; //
// 11 bin for ignored values
bin for ignored values
bins
bins cc == {{ 2,
2, 33 };
}; //
// 11 bin
bin for
for 2,
2, 33
bins
bins d[2]
d[2] == {{ [9:11],
[9:11], 9,
9, [12:15]
[12:15] };
}; //
// 22 bins
bins - d[0] == {9,10,11,9}
- d[0] {9,10,11,9}
//
// -- d[1]
d[1] == {12}
{12}
bins e[] = { [0:2], 2,
bins e[] = { [0:2], 2, 6 }; 6 }; //
// 33 bins
bins e[1], e[2], e[6]
e[1], e[2], e[6]
bins f
bins f = default;
= default; //
// 11 bin for 4,5,7,8
bin for 4,5,7,8
}}
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a) The illegal_bins keyword specifies bins for illegal values. The simulator does not cover these
values even if they appear in other bins, and issues an error upon occurrence of the illegal
values.
b) The ignore_bins keyword specifies bins for ignored values. The simulator does not cover these
values even if they appear in other bins, but does not issue an error upon their occurrence
unless they are also illegal values.
c) A scaler bin is one bin for all the specified values.
d) For a vector bin of a specified size, the values are distributed as evenly as possible by their
appearance in the open range list, with the last bin getting any extra values. Duplicate values
are retained, so can show up in multiple bins. Illegal and ignored values are removed after the
values are distributed.
e) For a vector bin of an unspecified size, the values are distributed each to their own bin. The
standard implies this to mean unique values, with duplicate values not retained. Illegal and
ignored values are removed after the values are distributed. Here, that results in an empty bin
(e[0]), which is removed.
f) The default keyword specifies bins for values that do not appear in any other bins. You cannot
use the illegal_bins or ignore_bins keywords with the default keyword.

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How Many Bins?

module
module example_with_bins;
example_with_bins;
logic
logic clk;
clk;
logic
logic [2:0]
[2:0] opcode;
opcode;
logic
logic [15:0]
[15:0] address;
address; How many bins in
? this covergroup?
covergroup
covergroup cg1
cg1 @(posedge
@(posedge clk);
Question What are their names?
clk);
c1:
c1: coverpoint
coverpoint opcode;
opcode; Answers in appendix A
c2:
c2: coverpoint
coverpoint address
address {{
bins
bins low[]
low[] == {{ [0:’h0F]
[0:’h0F] }} ;;
bins
bins high = { [’h10:’hFF] }} ;;
high = { [’h10:’hFF]
}}
endgroup
endgroup :: cg1
cg1

cg1
cg1 cover_inst
cover_inst == new();
new();

...
...

endmodule
endmodule

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Cross Coverage
You can track cross-products of:
 Coverpoints within the covergroup
logic
logic [1:0]
[1:0] veca,
veca, vecb;
vecb;
...
...
 Other scope variables covergroup
covergroup cg1
cg1 @(posedge
@(posedge clk);
clk);
 Creates implicit coverpoint c1: coverpoint veca;
c1: coverpoint veca;
 Participates in cover cross c2:
c2: coverpoint
coverpoint vecb;
vecb;
crossab:
crossab: cross c1, c2;
cross c1,
 No coverage data reported for c2;
endgroup : cg1
variable endgroup : cg1

c1.auto[0]
c1.auto[1]
c1.auto[2]
c1.auto[3]
Use the cross keyword, and provide a:
 cross name (optional)
 list of coverpoints and/or variables c2.auto[0]
c2.auto[1]
c2.auto[2]
c2.auto[3]

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You can declare cover crosses of two or more already declared coverpoints within the covergroup
and/or other integral variables. SystemVerilog automatically creates “virtual” coverpoints for cover
cross variables for which you did not declare a coverpoint. It does not report coverage data for
these “virtual” coverpoints.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 18.5

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Automatic Cross Bins

reg
reg [1:0]
[1:0] a;
a;
reg [3:0]
reg [3:0] b;b;
reg
reg c;
c;
covergroup
covergroup cgcg @(posedge
@(posedge clk);
clk);
bcp:
bcp: coverpoint
coverpoint bb {{
bins
bins b1
b1 == {{ [9:12]
[9:12] };
}; //one
//one bin
bin b1
b1
bins
bins b2[]
b2[] == {{ [13:15]
[13:15] };
}; //3
//3 bins:
bins: b2[13],
b2[13], b2[14],
b2[14], b2[15]
b2[15]
bins restofb[] = default;
bins restofb[] = default; //9
//9 bins:
bins: [0]
[0] ... [8] not in cross
... [8] not in cross
}}
ccp:
ccp: coverpoint
coverpoint c; c; //
// two
two automatic
automatic bins
bins
AxBxC:
AxBxC: cross a, bcp, ccp;
cross a, bcp, ccp; //
// 32
32 bins = a(4) xx bcp(4)
bins = a(4) bcp(4) xx ccp(2)
ccp(2)
endgroup
endgroup :: cg
cg

AxBxC.auto[0] = <a.auto[0], b.b1, c.auto[0]>

Crosses AxBxC.auto[1] = <a.auto[0], b.b1, c.auto[1]>
created AxBxC.auto[2] = <a.auto[0], b.b2[13], c.auto[0]>
AxBxC.auto[3] = <a.auto[0], b.b2[13], c.auto[1]>
AxBxC.auto[4] = <a.auto[0], b.b2[14], c.auto[0]>
....

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This example declares a cover cross of one variable and two previously declared coverpoints:
 The variable has four possible values for which four “virtual” bins are automatically created.
 The first declared coverpoint has one explicit scalar bin, and one explicit vector bin containing
three elements, for a total of four bins.
 The second coverpoint has two possible values for which two bins are automatically created.
The cover cross thus has 32 automatic bins, one for each combination of coverpoint bins that make
up the cross.
Pause here and examine this cross coverage example.

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Explicit Cross Bins and Selections

You can create cross coverage
bin selections using conjunction reg [1:0] one;
reg [1:0] one;
disjunction and negation of bins reg [3:0] two;
reg [3:0] two;
 binsof selects all or a covergroup
covergroup cg
cg @(posedge
@(posedge clk);
clk);
specific bin from a cp1: coverpoint one
cp1: coverpoint one { {
coverpoint bins
bins A[]
A[] == {{ [0:3]
[0:3] };}
};}
cp2:
cp2: coverpoint
coverpoint two
two {{
 intersect filters the
bins
bins low
low == {{ [0:5]
[0:5] };
selection to specified };
bins
bins mid = { [6:10] };
mid = { [6:10]
value ranges };
bins
bins high
high == {{ [11:15]
[11:15] };}
};}
 You can use !, &&, || on onextwo:
onextwo: cross cp1, cp2 {{
cross cp1, cp2
resulting bin selections bins
bins x1
x1 == binsof(cp2)
binsof(cp2) intersect
intersect {{ [8:10]};
[8:10]};
bins
bins x2 = binsof(cp1.A[2]) &&
x2 = binsof(cp1.A[2]) && !binsof(cp2.high);}
!binsof(cp2.high);}
cp1.A[0]
cp1.A[1]
cp1.A[2]
cp1.A[3]

endgroup
endgroup :: cgcg

x1 = <cp2.mid,cp1.A[0], cp2.mid,cp1.A[1],
cp2.high cp2.mid,cp1.A[2], cp2.mid,cp1.A[3]>
cp2.mid x1 x2 = <cp2.low,cp1.A[2], cp2.mid,cp1.A[2]>
cp2.low x2

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SystemVerilog by default automatically creates a single bin for every product of the cover cross. It
does not include any default coverpoint bins or any declared as illegal or to ignore.
You can explicitly declare cover cross bins enclosed in curley braces ({}) immediately after the list
of coverpoints to cross. As with coverpoint bins, if you do not explicitly specify cover cross bins or
options, you terminate the cover cross declaration with a semicolon, but if you do explicitly specify
cover cross bins or options, you instead terminate each bin or option specification itself with a
semicolon.
You do not specify an open value range for a cover cross bin. Instead you use the binsof keyword
to select those coverpoint bins that should participate in the cross, optionally filtered to an open
value range with the intersect keyword. You can then perform conjunction, disjunction and
negation operations on the resulting bin selections.
The example declares the cover cross bin “x1” to include the bins of coverpoint “cp2” that contain
the values 8 through 10, so only the “mid” bin of coverpoint “cp2” participates in the “x1” cover
cross bin. The example declares the cover cross bin “x2” to include the “A[2]” bin of coverpoint
“cp1” conjoined with the negation of the “high” bin of coverpoint “cp2”.
Pause here and examine this selection of cross coverage bins.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 18.5

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Illegal and Ignored Cross Bins

Use ignore_bins to exclude
reg
reg [1:0]
[1:0] one;
bins from a cross reg
one;
reg [3:0]
[3:0] two;
two;
 Even if selected elsewhere covergroup
covergroup cg
cg @(posedge
@(posedge clk);
clk);
in the same cross cp1:
cp1: coverpoint
coverpoint one one {{
bins
bins A[]
A[] == {{ [0:3]
[0:3] };}
};}
cp2:
cp2: coverpoint
coverpoint two two {{
Use illegal_bins to specify bins
bins low
low == {{ [0:5]
[0:5] };
};
illegal cross-product values bins
bins mid = { [6:10] };
mid = { [6:10] };
bins
bins high
high == {{ [11:15]
[11:15] };}
};}
 Even if selected or onextwo: cross cp1, cp2
onextwo: cross cp1, cp2 { {
excluded elsewhere bins
bins x3
x3 == !! binsof(cp2)
binsof(cp2) intersect
intersect {{ [0:2]};
[0:2]};
cp1.A[0]
cp1.A[1]
cp1.A[2]
cp1.A[3]

ignore_bins x4 = binsof(cp1.A[1]);}
ignore_bins x4 = binsof(cp1.A[1]);}
endgroup
endgroup :: cg
cg

cp2.high x3 = <cp2.mid,cp1.A[0], cp2.mid,cp1.A[2],

x3
cp2.mid cp2.mid,cp1.A[3], cp2.high,cp1.A[0],
cp2.low cp2.high,cp1.A[2], cp2.high,cp1.A[3]>

x4

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As with coverpoint bins, you can declare cover cross bins to be illegal or to be ignored. Coverpoint
bins that participate in a cover cross bin to be ignored are removed from any other cover cross bin
where they may otherwise participate. Coverpoint bins that participate in an illegal cover cross bin
are also removed from any other cover cross bin where they may otherwise participate.
Furthermore, the simulator must issue an error upon the occurrence of any such illegal cross-
product.
This example declares the cross coverage bin “x3” to exclude the bins of coverpoint “cp2” that
contain the values 0 through 2, and the cross coverage ignore bin “x4” that removes from all cross
bins the bins of coverpoint “cp1.A[1]”.
Pause here for a moment to ensure you understand the effect of ignore and illegal bins.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Sections 18.5.2, 18.5.3

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Covergroup Options
You can specify options to control the behavior
of covergroups, coverpoints and cover crosses. type option
int a, b;
Each of these constructs has two built-in int a, b;
covergroup
covergroup cg1
cg1 @(posedge
@(posedge clk);
clk);
structures: c1: coverpoint a {
c1: coverpoint a {
 Type-specific (static) options type_option.comment
type_option.comment == "a";}
"a";}
c2: coverpoint b;
c2: coverpoint b;
struct {) endgroup
endgroup :: cg1
cg1
...
} type_option; cg1::type_option.comment
cg1::type_option.comment == "ab";
"ab";
cg1 one = new;
cg1 one = new;

 Instance-specific options
instance option
struct { int a, b;
int a, b;
... covergroup
covergroup cg1
cg1 @(posedge
@(posedge clk);
clk);
} option; c1: coverpoint a
c1: coverpoint a {{
option.auto_bin_max
option.auto_bin_max == 10;}
10;}
c2: coverpoint b;
c2: coverpoint b;
See field definitions on following slides… endgroup
endgroup :: cg1
cg1

cg1
cg1 one
one == new;
new;
one.c2.option.auto_bin_max
one.c2.option.auto_bin_max == 256;
256;
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The built-in covergroup base class declares for the covergroup, coverpoint, and cover cross, static
structures named “type_option” with options that you set for the covergroup type, and automatic
structures named “option” with options that you can modify for each covergroup instance. Within
the covergroup declaration, you can reference these fields hierarchically as you would for any class
member structure. You can later procedurally set most instance-specific options for each individual
instance of the covergroup.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 18.6

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Reference: Type-Specific type_option Fields

Field Field Default cover cover cover Description
Type Ident Value group point cross
int weight 1    Weight of this element for
calculation of covergroup or
overall coverage
int goal 100    Target goal

string comment ""    Comment to include in

coverage report
bit strobe 0  Whether to defer samples
to end of time slot

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You set type-specific options only within the covergroup definition. Type-specific weight, goal and
comment options you set at the covergroup level do not affect the values set at the coverpoint or
cover cross level. You can also set weight, goal and comment options as instance-specific options.
The next slide describes the instance-specific options.
 Set the weight field to modify the relative weight of the coverpoint or cover cross when
calculating the enclosing covergroup coverage metric, and the relative weight of the
covergroup when calculating the overall coverage metric, for a type-based coverage report.
 Set the goal field to modify the target goal for the element. The standard does not state how the
vendor should use this field.
 Set the comment field to provide a string you want included in the coverage report.
 Set the strobe field to defer sampling to the end of the time slot, to where the $monitor and
$strobe system tasks execute.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 18.9

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Reference: Instance-Specific option Fields

Field Field Default cover cover cover Description
Type Ident Value group point cross
string name unique  Instance name
int weight 1    Weight of this element for
calculation of covergroup
or overall coverage
int goal 90    Target goal
string comment ""    Comment to include in
coverage report
int at_least 1    Target count to consider
bin as “covered”
int auto_bin_max 64   Max number of auto bins
int cross_num_prin 0   Max number of uncovered
t_missing cross bins to report
bit detect_overlap 0   If true issue warning for
values overlapping bins
bit per_instance 0  If true track coverage for
each instance

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You can set instance-specific options within a covergroup definition, and except for the per_instance option, can also
set them for each individual instance of the covergroup. Instance-specific options other than weight, goal and comment
that you set at the covergroup level provide new default values for coverpoint and cover cross options for which you do
not set a value.
 Set the name field to provide a name for the covergroup instance. The simulator generates a unique name for each
covergroup instance for which you do not supply a name.
 Set the weight field to modify the relative weight of the coverpoint or cover cross when calculating the enclosing
covergroup coverage metric, and the relative weight of the covergroup when calculating the overall coverage
metric, for an instance-based coverage report.
 Set the goal field to modify the target goal for the element. The standard does not state how the vendor should use
this field.
 Set the comment field to provide a string you want included in the coverage report.
 Set the at_least field to modify the hit count for considering a bin covered.
 Set the auto_bin_max field to modify the maximum number of bins to be automatically created.
 Set the cross_num_print_missing field to modify the number of uncovered cover cross bins that must be saved to
the coverage database and printed in the coverage report.
 Set the detect_overlap field to have the simulator issue a warning when the values of two coverpoint bins overlap.
 Set the per_instance field to track coverage data for each covergroup instance as well as each covergroup type.
You may want to track data on a per-instance basis if you differently parameterize each covergroup instance.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 18.9

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Reference: Covergroup Methods

Method Group Point Cross Description
void sample()  Force an immediate sample
real get_coverage    Get coverage for type
([ref int cov, ref int tot]) – this is a static method
real get_inst_coverage    Get coverage for instance
([ref int cov, ref int tot])
void set_inst_name(string)  Set the instance name
void start()    Start collecting coverage
void stop()    Stop collecting coverage

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These are methods of the covergroup base class that you call for specific covergroup instances. The
get_coverage() method is a static method that you can also call for the covergroup type using the
scope resolution operator.
 Use the sample() method to force an immediate sample.
 Use the get_coverage() method to obtain the current percent coverage for all instances of the
covergroup type. If you provide the optional reference arguments, the simulator places the
covered bin count and total bin count in the referenced variables.
 Use the get_inst_coverage() method to obtain the current percent coverage for only the one
specific instance of the covergroup type.
 Use the set_inst_name() method to provide a new instance name for the covergroup instance.
 Use the start() and stop() methods to start and stop collecting coverage data for the specific
covergroup instance.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 18.7

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Reference: Covergroup System Tasks & Functions

System Task/Function Description
$set_coverage_db_name ( filename ) Set coverage database filename
$load_coverage_db ( filename ) Load cumulative coverage database
$get_coverage ( ) Display percent cumulative coverage

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These are system tasks and functions that you can use to store and retrieve coverage information.
With these routines you can display only the overall cumulative coverage calculated by covergroup
type. As these routines are less than optimally useful, vendors typically provide proprietary means
for managing coverage data.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 18.8

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Summary
SystemVerilog data-oriented functional coverage with covergroups offers:
 Specification of the sampling event
 Specification of variables to sample
 Automatic and explicit binning of value counts
 Explicit scalar and vector bins
 Explicit bins for values and for transitions between values
 Explicit (default) bins for unspecified values, transitions
 Explicit bins, ignore_bins, and illegal_bins

 Specification of cross-products
 Automatic and explicit binning of cross counts
 Filtering and combining cross-product bins

 Options to control covergroup, coverpoint and cover cross behavior

 Methods to start, stop and calculate coverage, and force sampling

 System functions and tasks to manage a coverage database

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Pause here for a moment and review what you have learned about SystemVerilog data-oriented
functional coverage.

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Quiz

bit
bit [7:0]
[7:0] avec,
avec, bvec;
bvec;
covergroup
covergroup cg cg @(posedge
@(posedge clk);
clk);
cpa:
cpa: coverpoint
coverpoint avec
avec
{{ bins
bins a1
a1 == {{ [0:63]
[0:63] };
}; How many bins in this
bins
bins a2 = { [64:127] };
a2 = { [64:127] }; ? covergroup cross c?
bins a3 = { [128:191]
bins a3 = { [128:191] }; };
Question What are their names?
bins
bins a4
a4 == {{ [192:255]
[192:255] };
}; }} Solutions in Appendix A
cpb:
cpb: coverpoint
coverpoint bvec
bvec
{{ bins
bins b1
b1 == {0};
{0};
bins
bins b2 == {{ [1:84]
b2 [1:84] };
};
bins
bins b3
b3 == {{ [85:169]
[85:169] };
};
bins
bins b4 = { [170:255] };
b4 = { [170:255] }; }}
cc :: cross
cross cpa,
cpa, cpb
cpb
{{ bins
bins c1 = ! binsof(cpa)
c1 = ! binsof(cpa) intersect
intersect {[100:200]};
{[100:200]};
bins
bins c2 = binsof(cpa.a2) ||
c2 = binsof(cpa.a2) || binsof(cpb.b2);
binsof(cpb.b2);
bins
bins c3
c3 == binsof(cpa.a1)
binsof(cpa.a1) &&&& binsof(cpb.b4);
binsof(cpb.b4); }}
endgroup
endgroup

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About Lab 7
For lab 7 you collect and analyze data-oriented functional coverage of the
memory address and data. You declare and instantiate a covergroup
containing a coverpoint for the address and a coverpoint for the data and a
cover cross of the coverpoint bins. You run the simulation and examine the
resulting coverage data.

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Queues and Dynamic and Associative

Arrays
Chapter 9

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Aims & Topics

Aims
 To explore features of dynamic arrays, associative arrays and queues.

Topics
 Dynamic arrays

 Associative arrays

 Queues

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This chapter explores the SystemVerilog dynamic and associative arrays, and queues.

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Dynamic Arrays
Use a dynamic array when the array size must change during the simulation
 Declare a dynamic array by leaving an unpacked dimension unsized
 Use the new[] operator to allocate and initialize (construct) the array
 new[size] – allocates array and initializes to default initial values
 new[size](array) – allocates array and initializes from existing array of the same
type (e.g. itself) when setting or changing the array size
 Dynamic arrays have the size() and delete() methods
 function void delete() // delete all elements (sets size to 0)

logic
logic [7:0]
[7:0] dynarr[];
dynarr[]; //
// dynamic
dynamic array
array of
of 8-bit
8-bit vectors
vectors
int index;
int index;
...
...
dynarr
dynarr == new[8];
new[8]; //initialize
//initialize
for
for (int i=0; i<8; i++) dynarr[i] == i+1;
(int i=0; i<8; i++) dynarr[i] i+1;
index = dynarr.size();
index = dynarr.size(); // 8
// 8
dynarr
dynarr == new[16]
new[16] (dynarr);
(dynarr); //
// resize
resize array
array keeping
keeping values
values
index
index == dynarr.size();
dynarr.size(); //
// 16
16
dynarr.delete();
dynarr.delete(); //
// 00

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Use a dynamic array when the array size changes during the simulation. Declare the dynamic array
by leaving an unpacked dimension unsized. Create, and re-create, the array during run time using
the new operator. As an argument to the new operator, you can provide an existing array of the
same type to initialize the new array. Dynamic arrays have the size() and delete() methods, as well
as the standard array manipulation methods (see 5.15) and standard array query system functions
(see 22.6).
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 5.6

The IEEE draft standard P1800/D9 clarifies that you can declare more than one unsized dimension,
thus in effect declaring a dynamic array of dynamic arrays.

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Dynamic Array Example

parameter
parameter num_vectors
num_vectors == 32;
32;
logic
logic [7:0]
[7:0] dyn[];
dyn[]; //
// dynamic
dynamic array
array declaration
declaration
bit
bit [4:0] addr;
[4:0] addr;
logic
logic [7:0]
[7:0] wdata,
wdata, rdata;
rdata;
initial
initial begin
begin
dyn
dyn == new[num_vectors];
new[num_vectors]; //
// array
array allocation
allocation size:32
size:32
$display("dyn.size():%d",
$display("dyn.size():%d", dyn.size());// will print 32
dyn.size());// will print 32
for
for (int
(int i=0;
i=0; i<num_vectors;
i<num_vectors; i++)
i++) begin
begin
write_mem(i, i+5);
write_mem(i, i+5);
dyn[i]
dyn[i] == i+5;
i+5; //
// dynamic
dynamic array
array write
write
end
end
for
for (int
(int i=0;
i=0; i<num_vectors;
i<num_vectors; i++)
i++) begin
begin
read_mem(i, rdata);
read_mem(i, rdata);
if
if (rdata
(rdata !==
!== dyn[i])
dyn[i])
$display("Error
$display("Error at at Addr:%h
Addr:%h -- Wrote:%h,
Wrote:%h, Read:%h",
Read:%h",
i, dyn[i] rdata);
i, dyn[i] rdata);
end
end
dyn.delete();
dyn.delete(); //
// deallocate
deallocate array
array memory
memory
$display("dyn.size():%d", dyn.size());// should
$display("dyn.size():%d", dyn.size());// should be 0 be 0
end
end

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This example declares a dynamic array to store 8-bit logic vectors. During run time, it allocates
space for 32 elements. In a loop, it writes data to a memory component and stores the data in the
dynamic memory. In a second loop, it reads data from the memory component and compares it to
the data in the dynamic memory. It deletes the dynamic memory when finished with it.

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Associative Arrays
Use an associative array when the data space is unbounded or sparsely populated
 Declare the array by specifying a type instead of a size for its one dimension
 The key can be any type for which a relative order can be determined
 Or ‘*’ to permit indexing by any integral type

 Array elements do not exist until you assign to them

 Array elements are “pairs” of associated key and data values

 Associative arrays have the num(), delete(), exists(), first(),

last(), next(), and prev() methods

bit
bit [3:0]
[3:0] aa1
aa1 [int];
[int]; //
// associative
associative array
array of
of 4-bit
4-bit 2-state
2-state
//
// with
with index type of int
index type of int
logic
logic [7:0]
[7:0] aa2
aa2 [integer];
[integer]; //
// associative
associative array
array of
of 8-bit
8-bit logic
logic
//
// with
with index type of integer
index type of integer

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Use an associative array when the address space is unbounded or sparsely populated. Declare the
associative array by specifying a type instead of a size for its one dimension. The key can be any
type for which a relative order can be determined, that is, any type to which SystemVerilog can
apply a relational operator. Associative array elements do not exist until you assign them. You
assign “pairs” of associated key and data values.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Sections 5.9 – 5.13

The IEEE draft standard P1800/D9 adds that associative arrays using the wildcard index type shall
not participate in a foreach loop or in an array manipulation method that returns an index value.

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Associative Array Methods

Method Description Syntax

num() Returns the number of entries in an function int num();
associative array
delete() Removes a single entry if an index is specified function void delete(input
removes all entries if no index specified index);
exists() Returns 1 if an element exists at the indexed function int exists (input index);
location, else returns 0
first() Assigns the value of the first (smallest) index function int first(ref_index);
in the array to ref_index
Returns 0 if array empty, otherwise 1
last() Assigns the value of the last (largest) index of function int last(ref_index);
the array to ref_index
next() Assigns the next value to ref_index function int next(ref_index);
prev() Assigns the previous value to ref_index function int prev(ref_index);

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Associative arrays have the num(), delete(), exists(), first(), last(), next(), and prev() methods, as
well as the standard array manipulation methods (see 5.15) and standard array query system
functions (see 22.6). Pause here for a moment and examine the associative array methods.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 5.10

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Associative Array Lookup Table

logic
logic [7:0]
[7:0] assoc[int];
assoc[int]; //
// associative
associative array
array declaration
declaration
bit
bit [4:0] rand_a;
[4:0] rand_a;
logic
logic [7:0] rand_d,
[7:0] rand_d, rdat;
rdat;
initial begin
initial begin
for
for (int
(int i=0;
i=0; i<=31;
i<=31; i++)
i++) begin
begin
success
success == randomize(rand_a,
randomize(rand_a, rand_d);
rand_d); //
// random
random data
data gen
gen
write_mem (rand_a, rand_d);
write_mem (rand_a, rand_d);
assoc[rand_a]
assoc[rand_a] == rand_d;
rand_d; //
// associative
associative array
array assign
assign
end
end
$display("Memory
$display("Memory locations
locations to
to check:%d",
check:%d", assoc.num());
assoc.num());
for (int i=0; i<=31; i++)
for (int i=0; i<=31; i++)
if
if (assoc.exists(i))
(assoc.exists(i)) begin
begin //
// only
only read
read address
address if
if written
written
read_mem(i, rdat);
read_mem(i, rdat);
if
if (rdat
(rdat !=
!= assoc[i])
assoc[i]) //
// check
check against
against array
array data
data
$display("Error
$display("Error atat Addr:%h"
Addr:%h" i);
i);
assoc.delete(i);
assoc.delete(i); //
// Deallocate
Deallocate memory
memory at
at index
index
end
end
$display("array
$display("array size:%d",
size:%d", assoc.num());
assoc.num()); //
// should
should display
display 00
end
end

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This example declares an associative array to store 8-bit logic vectors with keys of the int type. In a
loop, it randomizes address and data 32 times, writes the data to a memory component, and stores
the address/data pairs in an associative memory. As the address vector is only 5 bits wide, it is very
likely that some addresses are written multiple times. In a second loop, the example iterates
through the potential address space. For each address, if the associative array has an entry for that
address, it verifies that the memory component has the correct data, then deletes the entry for that
address. Deleting entries individually is inefficient.

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More Efficient Lookup Table

logic
logic [7:0]
[7:0] assoc[int];
assoc[int]; //
// associative
associative array
array
bit
bit [4:0] rand_a;
[4:0] rand_a;
logic
logic [7:0]
[7:0] rand_d,
rand_d, rdat;
rdat;
int ai;
int ai; //
// index
index for
for methods
methods
initial begin
initial begin
for
for (int
(int i=0;
i=0; i<=31;
i<=31; i++)
i++) begin
begin
success
success == randomize(rand_a,
randomize(rand_a, rand_d);
rand_d); //// random
random data
data gen
gen
write_mem (rand_a, rand_d);
write_mem (rand_a, rand_d);
assoc[rand_a]
assoc[rand_a] == rand_d;
rand_d; //
// associative
associative array
array assign
assign
end
end
$display("Addresses
$display("Addresses Assigned:%d",
Assigned:%d", assoc.num());
assoc.num());
if (assoc.first(ai))
if (assoc.first(ai)) //
// assign
assign first
first index
index
do begin
do begin
read_mem(ai,
read_mem(ai, rdat);
rdat);
if (rdat !== assoc[ai])
if (rdat !== assoc[ai]) //
// check
check data
data against
against array
array
$display("Error at Addr:%h", ai);
$display("Error at Addr:%h", ai);
end
end
while(assoc.next(ai));
while(assoc.next(ai)); //
// assign
assign next
next index
index
assoc.delete();
assoc.delete(); //
// deallocate all memory
deallocate all memory
end
end
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This algorithm is more efficient. It utilizes associative array methods to iterate through only the
assigned entries. It deletes the entire associative array at once when finished with it.

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Queues
Use a queue “array” where insertion and extraction order are important
 Declare a queue by using $ as the size of its one dimension:
int q_int[$];
int q_int[$:200]; // optionally limit the queue size
 Use $ to reference the end of the queue: myInt = q_int[$];
 Queues have the size(), insert(), delete(), pop_front(),
pop_back(), push_front() and push_back() methods

integer
integer q_integer[$];
q_integer[$]; //
// queue
queue of
of integers
integers
logic
logic [15:0]
[15:0] q_logic
q_logic [$];
[$]; //
// queue
queue of
of 16-bit
16-bit logic
logic
int
int q_int[$:2000];
q_int[$:2000]; //
// queue
queue of
of int
int –– max
max size
size of
of 2000
2000
time
time q_time
q_time [$:10];
[$:10]; //
// queue
queue of
of time
time –– max
max size
size of
of 10
10

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Use a queue when insertion and extraction order are important. Declare the a queue by using the
“dollar” ($) character as the size of its one dimension. You can optionally limit the queue size by
appending a colon (:) followed by a constant expression after the “dollar” character. You can use
the “dollar” character to represent the end of the queue in subsequent array subscript operations.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 5.14

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Queue Methods

Method Description Syntax

size() returns the size of the queue function int size();
insert() inserts an item at the index location function void insert (int index, qtype item);
delete() removes item at the specified index function void delete(int index);
pop_front() removes an item in the front of the function q_type pop_front();
queue (0)
pop_back() removes an item from the end of the function q_type pop_back();
queue ($)
push_front() places an item at the front of the function void push_front(q_type item);
queue (0)
push_back() places an item at the back of the function void push_back(q_type item);
queue ($+1)

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Queues have the size(), insert(), delete(), pop_front(), pop_back(), push_front() and push_back()
methods. Unlike the associative array, you cannot delete an entire queue in one statement. An
index value that lies outside the current queue bounds or is otherwise invalid causes a read
operation to return the default value for the queue type. An index value that lies outside the current
queue bounds plus one or is otherwise invalid causes a write operation to issue a warning and not
do the write. Indexing the element just past the current queue end for a write operation is the
equivalent of a push_back() operation.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 5.14.2

The IEEE draft standard P1800/D9 proposes that the delete() function delete the entire queue if no
index argument is provided.

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Queue Methods Example

int
int data,
data, q_int[$];
q_int[$]; //
// queue
queue of
of unlimited
unlimited size
size
bit [7:0] q_bit[$:100];
bit [7:0] q_bit[$:100]; //
// queue with maximum size of
queue with maximum size of 100
100

initial
initial begin
begin
q_int.push_front(0);
q_int.push_front(0); //
// {0}
{0}
q_int.push_back(1);
q_int.push_back(1); //
// {0,1}
{0,1}
q_int.push_front(2);
q_int.push_front(2); //
// {2,0,1}
{2,0,1}
q_int.insert(1,
q_int.insert(1, 3);
3); //
// {2,3,0,1}
{2,3,0,1}
q_int.insert(3, 4);
q_int.insert(3, 4); //
// {2,3,0,4,1}
{2,3,0,4,1}
q_int.delete(2);
q_int.delete(2); //
// {2,3,4,1}
{2,3,4,1}
q_int.insert(2,5);
q_int.insert(2,5); //
// {2,3,5,4,1}
{2,3,5,4,1}
data
data == q_int.pop_back();
q_int.pop_back(); //
// {2,3,5,4}
{2,3,5,4} data
data == 11
data
data == q_int.pop_front();
q_int.pop_front(); //
// {3,5,4}
{3,5,4} data
data == 22
while
while (q_int.size()
(q_int.size() >> 0)
0) //
// checking
checking queue
queue size
size
data
data == q_int.pop_back();
q_int.pop_back(); //
// loop
loop executes
executes 33 times
times
q_bit.push_front(8’h01);
q_bit.push_front(8’h01); //
// {’h01}
{’h01}
q_bit.push_back(8’h45);
q_bit.push_back(8’h45); //
// {’h01,’h45}
{’h01,’h45}
q_bit.push_front(8’h89);
q_bit.push_front(8’h89); //
// {’89,’h01,’h45}
{’89,’h01,’h45}
end
end

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Queue methods support inserting and extracting elements. This example illustrates use of several of
the methods.

Pause here and examine this example using queue methods.

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Queue Indexing Example

int
int data,
data, q_int[$];
q_int[$]; //
// queue
queue of
of unlimited
unlimited size
size
bit
bit [7:0]
[7:0] q_bit[$:100];
q_bit[$:100]; //
// queue
queue with
with maximum
maximum size
size of
of 100
100

initial
initial begin
begin
q_int
q_int = {0,q_int};
= {0,q_int}; //
// {0}
{0}
q_int
q_int == {q_int,1};
{q_int,1}; //
// {0,1}
{0,1}
q_int
q_int == {2,q_int};
{2,q_int}; //
// {2,0,1}
{2,0,1}
q_int = {q_int[0],3,q_int[1:$]};
q_int = {q_int[0],3,q_int[1:$]}; //
// {2,3,0,1}
{2,3,0,1}
q_int
q_int == {q_int[0:2],4,q_int[3]};
{q_int[0:2],4,q_int[3]}; //
// {2,3,0,4,1}
{2,3,0,4,1}
q_int = {q_int[0:1],q_int[3:4]};
q_int = {q_int[0:1],q_int[3:4]}; //
// {2,3,4,1}
{2,3,4,1}
q_int
q_int == {q_int[0:1],5,q_int[2:3]};
{q_int[0:1],5,q_int[2:3]}; //
// {2,3,5,4,1}
{2,3,5,4,1}
data
data = q_int[$]; q_int
= q_int[$]; q_int == q_int[0:$-1];
q_int[0:$-1]; //
// {2,3,5,4}
{2,3,5,4} data
data == 11
data
data == q_int[0];
q_int[0]; q_int
q_int == q_int[1:$];
q_int[1:$]; //
// {3,5,4}
{3,5,4} data
data == 22
while
while (q_int.size()
(q_int.size() >> 0)
0) begin
begin //
// checking
checking queue
queue size
size
data
data == q_int[$];
q_int[$]; //
// loop
loop executes
executes 33 times
times
q_int
q_int == q_int[0:$-1];
q_int[0:$-1]; end
end
q_bit = {8’h01,q_bit};
q_bit = {8’h01,q_bit}; //
// {’h01}
{’h01}
q_bit
q_bit == {q_bit,8’h45};
{q_bit,8’h45}; //
// {’h01,’h45}
{’h01,’h45}
q_bit = {8’h89,q_bit};
q_bit = {8’h89,q_bit}; //
// {’89,’h01,’h45}
{’89,’h01,’h45}
end
end

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A queue is an array, so if you really want to, you can still use unpacked array indexing and
concatenation to insert and extract elements. As this example illustrates, you probably don’t really
want to. The queue methods are much more friendly.

We won’t bother examining this slide too closely.

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Array Manipulation Methods

Array methods support searching, ordering, and reducing arrays:
method [[(iterator)] with (expression)]
 array locator methods — search an unpacked array in any order for
elements or indexes that satisfy the expression and return a queue of
those elements or indexes
 cannot apply to associative arrays using wildcard index type
 e.g.: q_int = array_int.find with (item>0)

 array ordering methods — reorder an unpacked array

 cannot apply to associative arrays
 e.g.: q_int.sort

 array reduction methods — reduce an unpacked array of integral

values to a single value
 e.g.: var_int = q_int.xor

The iterator (default identifier item) references the current element at each
iteration. It is visible only within the expression. See following slides...
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Built-in methods support searching, ordering, and reducing arrays. These methods apply to any
unpacked array, with the exception that locator methods do not apply to associative arrays that use
the wildcard index type and ordering methods do not apply to associative arrays at all. The locator
methods return a queue and the reduction methods return a single value.
Within the “with” expression you may refer to the current array element, using the “item” identifier
by default, or using whatever name you pass to the method.
Within the “with” expression you may refer to the current element’s index by using the iterator’s
index() method and passing to it the dimension number for which you want the current index. The
dimension number defaults to 1, that is, the first dimension.

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Reference: Array Locator Methods

function array_type[$] locator_method (array_type iterator = item);
function int_or_index_type[$] index_locator_method(array_type iterator = item);

Locator Method Description

find(), Find element(s) satisfying relational expression.
find_first(), Specifying with is mandatory.
find_last()
find_index(), Find index(s) of elements satisfying relational expression.
find_first_index(), Specifying with is mandatory.
find_last_index()
min(), max(), Find element(s) satisfying expression.
unique() Specifying with is optional.
unique_index() Find indexes of elements having unique expression.
Specifying with is optional.

The with clause specifies an expression for evaluation, e.g.:

q_int = q_string.unique_index with (item[$]);

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Array locator methods apply to any unpacked array except associative arrays using the wildcard
index type. The min(), max(), and both unique methods further require that relational operators be
defined for the expression to be evaluated. Where the “with” clause is optional, this expression is
by default the array element itself.
This example returns a queue of indexes of the strings whose last character is unique.

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Reference: Array Ordering Methods

function void ordering_method ( array_type iterator = item )

Method Description
reverse() Reverse array elements.
Specifying with is an error.
sort() Sort array elements (ascending).
rsort() Sort array elements (descending).
shuffle() Randomize array element order.
Specifying with is an error.

The optional with clause specifies an alternative expression for evaluation, e.g.:
typedef struct {string nm; int unsigned id; shortreal GPA;} student;
student students[];
...
students.rsort() with (item.GPA);

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Array ordering methods apply to any unpacked array except associative arrays. The sorting
methods further require that relational operators be defined for the expression to be evaluated for
sorting purposes. As this expression is by default the array element itself, for some array types you
will want to specify some other appropriate expression.
This example declares a dynamic array of an unpacked struct type. For sorting purposes, it uses the
value of the GPA field of each element.

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Reference: Array Reduction Methods

function expr_or_array_type reduction_method (array_type iterator = item);

Method Description
sum() Sum of expressions
product() Product of expressions
and() Conjunction of expressions (bitwise)
or() Disjunction of expressions (bitwise)
xor() Parity of expressions (bitwise)

The optional with clause specifies an alternative expression for evaluation, e.g.:
int ia2d[2][2] = ’{default:2};
int j;
...
j = ia2d.product with (item.product); // 16

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Array reduction methods can apply to any unpacked array.

The corresponding operation must be defined for the type of the expressions that participate in the
reduction. These expressions are by default the array elements, which then by default must be
integral, but you can specify any expression for which the corresponding operation is defined.
This example calculates a product of the “ia2d” unpacked array. Each element of the “ia2d” array
is itself a one-dimension unpacked array of int, so cannot directly participate in the product. This
example instead uses the value returned from calling the product method of each element in turn.

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Summary
Features of SystemVerilog arrays allow efficient and flexible definition,
storage and access to large test data sets
 Dynamic arrays useful for contiguous data which varies in size during
simulation
 Track an undetermined number of dynamic objects

 Associative arrays are ideal for sparse or unbounded data sets

 Model a system’s extended address space

 Queues are useful where insertion and extraction order is important

 Synchronize data using FIFO and LIFO (stack) mechanisms

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Pause here for a moment and review what you have learned about SystemVerilog arrays.

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Quiz
Match the array that best meets each design need:

1. I want to concisely code an RTL instruction A. Packed array

processor to strip the opcode, address and
B. Unpacked array
data fields off the instruction word…
C. Dynamic array
2. I need to validate the architecture of my
processor stack… D. Associative array
3. I need to validate the architecture of my E. Queue
packet data temporary storage…
4. I need to validate the architecture of my
instruction cache…
5. I want to perform matrix operations on fixed-
size “chunks” of data of the real type…

Solutions in Appendix A

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About Lab 8
For lab 8 you implement a “scoreboard” for the memory write transactions.
You implement it, using a:
 dynamic array

 associative array

 queue array

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Interprocess Synchronization

Chapter 10

November 6, 2009

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Aims and Topics

Aims
 To explore SystemVerilog interprocess synchronization mechanisms

Topics
 Non-blocking event trigger

 Event sequences

 Event variables

 Mailboxes
 Semaphores

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This chapter explores the SystemVerilog interprocess synchronization mechanisms: enhanced

events, mailboxes and semaphores.

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Non-Blocking Event Trigger: ->>

You can trigger SystemVerilog events with a non-blocking ->> operator
 Executes without blocking

 Schedules an event for the NBA region

module
module test();
test();
event
event e;
e;
bit
bit clk
clk == 1’b0;
1’b0;
always
always @clk
@clk
#5
#5 clk
clk <=
<= ~clk;
~clk;
always
always @e
@e
$display($time);
$display($time);
initial
initial begin
begin
->>
->> #3
#3 e;
e;
->>
->> @(posedge
@(posedge clk)
clk) e;
e;
end
end
endmodule
endmodule

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SystemVerilog adds a non-blocking event trigger (->>) that schedules the event for the NBA
region. You can use intra-assignment delays just as you do with the non-blocking assignment
operator.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 14.5.2

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Blocking Versus Non-Blocking Trigger

You use the non-blocking event trigger for the same reason you use the
non-blocking assignment – to prevent races between processes.
 Non-blocking event triggers occur in the NBA region:

module
module test();
test(); module
module test();
test();
event
event e;
e; event
event e;
e;
integer
integer ii == 0;
0; integer
integer ii == 0;
0;
always
always @e
@e always
always @e
@e
$display("i
$display("i is
is %d",i);
%d",i); $display("i
$display("i is
is %d",i);
%d",i);
initial
initial initial
initial
begin
begin begin
begin
ii <=
<= 1;
1; ii <=
<= 1;
1;
->
-> e;
e; //
// blocking
blocking ->>
->> e;
e; //non-blocking
//non-blocking
end
end end
end
endmodule
endmodule endmodule
endmodule

output i is 0 output i is 1

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The non-blocking event trigger serves the same general purpose as the non-blocking assignment –
to prevent a race between a block that triggers the event and a block that waits for the event in the
same delta cycle.

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Persistent Event Trigger: triggered

A process can wait for the triggered property of the event
 The triggered state persists to the end of the time step

“hangs” completes
module
module test;
test; module
module test;
test;
event
event e1,
e1, e2;
e2; event
event e1,
e1, e2;
e2;
initial
initial initial
initial
begin
begin begin
begin
$display("fork");
$display("fork"); $display("fork");
$display("fork");
fork
fork fork
fork
@e1;
@e1; @e1;
@e1;
->
-> e1;
e1; ->>
->> e1;
e1;
->
-> e2;
e2; ->
-> e2;
e2;
@e2;
@e2; wait(e2.triggered);
wait(e2.triggered);
join
join join
join
$display("join");
$display("join"); $display("join");
$display("join");
end
end end
end
endmodule
endmodule endmodule
endmodule

output fork output fork

join

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An event is not persistent. If a process “waits” for an event after it occurs, the process can go on
waiting forever.
The first example illustrates this. The forked blocks can be scheduled in any order. It is very likely
that one of the event controls is too late – its associated event has already occurred.
The second example utilizes the non-blocking event trigger, which schedules the event for the
NBA region, after the event control has had a chance to “wait” for that event. The example also
illustrates use of the triggered event property, which persists to the end of the time step. If the “e2”
event has already occurred when the “wait” statement executes, the triggered property is still true.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 14.5.4

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Event Sequencing: wait_order

A process can wait for a module
module test;
test;
specific sequence of events event
event e1,
e1, e2,
e2, e3;
e3;
always
always
 Upon each sequential wait_order(e1.triggered,
wait_order(e1.triggered, e2,
e2, e3)
e3)
$info("events
$info("events in
in order");
event, subsequent events else
else
order");

must not yet have triggered $warning("events

$warning("events out
out of
of order");
order");
...
...
 The first event can endmodule
endmodule
alternatively be the equivalent
triggered property module
module test;
test;
event
event e1,
e1, e2,
e2, e3;
e3;
 Construct is somewhat
always begin
always begin
wait(e1.triggered);
wait(e1.triggered);
similar to a concurrent @(e2
@(e2 or
or e3);
e3);
assertion in a procedural if
if (!e3.triggered)
(!e3.triggered) begin
@e3;
begin
@e3;
block $display("events
$display("events in
in order");
order");
end
end
 Associated action block else
else
$display("events
$display("events out
out of
of order");
order");
end
end
...
...
endmodule
endmodule

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A process can wait for a specific sequence of events. The first listed event can alternatively be the
triggered state of an event. The wait_order statement has characteristics very similar to a
concurrent assertion. Occurrence in turn of each event implies that the next event in the list has not
yet occurred and will occur before any of the later events in the list. Re-occurrence of an event has
no additional effect. Events out of order constitute an error by default. You can change this in an
associated action block.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 14.6

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Event Variables
A SystemVerilog event variable is a handle “pointing” to a synchronization queue.
 You can assign and compare these handles to each other.
 Assignment causes both to “point” to the same queue

module
module test;
test;
event
event e1,
e1, e2;
e2;
initial
initial
fork
fork
#1
#1 e2
e2 == e1;
e1; //
// e1,
e1, e2
e2 both
both now
now have
have e1
e1 synchronization
synchronization queue
queue
#2
#2 @e1
@e1 $display
$display ("e1
("e1 triggered");
triggered");
#2
#2 @e2
@e2 $display
$display ("e2
("e2 triggered");
triggered");
#3 -> e2;
#3 -> e2; //
// trigger e2
trigger e2 (and
(and also
also e1)
e1)
join
join
endmodule
endmodule

output e1 is triggered
e2 is triggered

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A SystemVerilog event variable is a handle that “points” to a synchronization queue. The queue is
a list of processes “waiting” for the event.
This example declares two event variables and then assigns one to the other. This makes both event
variables “point” to the same list of processes. Processes can access this synchronization queue
through either variable.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 14.7

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Event Variables – Merging Events

Merging events merges only the event variables.
 Both now “point” to the RHS synchronization queue

module
module test;
test;
event
event e1,
e1, e2;
e2;
initial
initial
fork
fork
#1
#1 @e1
@e1 $display
$display ("e1
("e1 triggered");
triggered");
#1
#1 @e2
@e2 $display
$display ("e2
("e2 triggered");
triggered");
#2
#2 e2 = e1; // e1, e2 both
e2 = e1; // e1, e2 both now
now have
have e1
e1 synchronization
synchronization queue
queue
//
// e2 synchronization queue is
e2 synchronization queue is lost
lost
#3
#3 ->
-> e2;
e2; //
// trigger
trigger e2e2 (and
(and also
also e1)
e1)
join
join
endmodule
endmodule

output e1 is triggered

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What the standard refers to as “event merging” is really just the merging of the event variables.
The source synchronization queue is assigned to the target event variable, so that both variables
“point” to the same queue. If no other variable still “points” to the synchronization queue of the
target variable, processes on that queue can wait forever, and the queue can be reused.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 14.7.1

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Event Variables – Reclaiming Events

You can assign the null value to an event.
 Triggering a null event shall have no effect.
 The effect of waiting on a null event is undefined

module
module test;
test;
event
event e1;
e1;
initial
initial
fork
fork Event e1 is set to null
#1
#1 @e1
@e1 $display
$display ("e1
("e1 triggered
triggered once");
once"); Synchronization
#2 -> e1; // trigger e1 queue can be released
#2 -> e1; // trigger e1
#3
#3 e1
e1 == null;
null; //
// e1
e1 synchronization
synchronization queue
queue lost
lost
#4 @e1 $display ("e1 triggered twice");
#4 @e1 $display ("e1 triggered twice"); At time 3 e1 is null. This
#5 -> e1; // nothing happens may not block at all or
#5 -> e1; // nothing happens may block forever
join
join
endmodule
endmodule Triggering null event
e1 has no effect

output e1 triggered once

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Assigning the null value to an event variable assigns a "null" synchronization queue. This
disassociates the variable from its previous synchronization queue. When a synchronization queue
is no longer associated with any event variable, the simulator can reuse the queue. The effect of
waiting on a null event is undefined. An implementation may choose to wait forever or not wait at
all, without warning, and triggering the null event has no effect.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 14.7.2

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Mailboxes
Mailboxes are a message-based synchronization mechanism
Used for passing messages where order is important (FIFO)
 Any process puts mail into the mailbox
 Blocking: put(anytype message)
 Non-Blocking: int try_put(anytype message)

 Any process gets mail from the mailbox

 Blocking: get(ref variable)
 Non-blocking: int try_get(ref variable)
 User is responsible for type compatibility!

 Any process can alternatively use peek() and try_peek() to

check for mail without removing it
mailbox
mailbox hugebox
hugebox == new;
new; //
// mailbox
mailbox of
of unlimited
unlimited size
size
mailbox
mailbox fourbox;
fourbox;
fourbox
fourbox == new(4);
new(4); //
// mailbox
mailbox of
of size
size 44
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Mailboxes are a class-like message-based process synchronization mechanism.

A mailbox is conceptually like a mailbox, with a delivery slot on one side, and a door on the other
slide for retrieving mail.
When you create the mailbox, you pass to its constructor the maximum capacity of the mailbox. If
you do not pass a number, the mailbox has unlimited capacity and can never be full.
A mailbox by default accepts messages of any type. Later slides show you how to restrict a
mailbox to just one type.
Any process can place messages in the mailbox. The blocking put() task attempts to put a message
in the mailbox and blocks if the mailbox is full. The non-blocking try_put() function attempts to
put a message in the mailbox and returns 0 if the mailbox is full.
Messages become available for retrieval in the same order they are place in the mailbox.
Any process can retrieve messages from the mailbox. The blocking get() task attempts to get a
message from the mailbox and blocks if the mailbox is empty. The non-blocking try_get() function
attempts to get a message from the mailbox and returns 0 if the mailbox is empty.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 14.3

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Mailbox Methods
Method Description Syntax
new() Mailbox constructor which optionally specifies function new(int bound = 0);
maximum size Note by default no maximum size.
num() Returns the number of messages currently in function int num();
the mailbox
put() Places a message in the mailbox task put (<message>);
– blocks if mailbox full
try_put() Places a message in a mailbox function int try_put (<message>);
– returns 0 if mailbox full
get() Retrieves a message from the mailbox – task get (ref <variable>);
blocks if mailbox empty
– error if type mismatch
try_get() Retrieves a message from the mailbox function int try_get (ref <variable>);
– returns +int if successful
– returns 0 if empty
– returns -int if type mismatch
peek() Copies a message from the mailbox task peek (ref <variable>);
– blocks if mailbox empty
– error if type mismatch
try_peek() Copies a message from the mailbox function int try_peek (ref <variable>);
– returns +int if successful
– returns 0 if empty
– returns -int if type mismatch

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The new() constructor constructs a mailbox of an optionally limited size.

The num() function returns the number of messages currently in the mailbox.
The blocking put() task attempts to put a message in the mailbox and blocks if the mailbox is full.
The non-blocking try_put() function attempts to put a message in the mailbox and returns 0 if the
mailbox is full.
The blocking get() task attempts to get a message from the mailbox and blocks if the mailbox is
empty. It is an error to attempt to get a message of a type incompatible with the type of the
message at the head of the mailbox queue.
The non-blocking try_get() function attempts to get a message from the mailbox and returns 0 if
the mailbox is empty and returns a negative integer on an attempt to get a message of a type
incompatible with the type of the message at the head of the mailbox queue.
The peek() task and try_peek() function operate similarly to the get() task and try_get() function
but copy the message instead of removing it.
Use the try_get() and try_peek() functions when you do not know what type of message is at the
head of the mailbox queue.

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Process Synchronization with a Mailbox

mailbox receiver
mailbox #(int)
#(int) mbox
mbox == new(4);
new(4); int
int rdat,
rdat, i=0;
i=0;
initial
initial
sender while
while (i<=5)
(i<=5)
initial
initial if
if (mbox.try_get(rdat))
(mbox.try_get(rdat))
for
for (int
(int i=0;
i=0; i<6;
i<6; i++)
i++) time #1
#1 i++;
i++;
#1ns mbox.put(i);
#1ns mbox.put(i); else
else
0
#7;
#7;
0 1
1 2 receiver unsuccessful
2 at time 0 – waits a while
3
sender blocks at 3 4
time 4 – mbox full
5

6
sender continues as 4 7 0 receiver gets
receiver gets mail mail at time 7
5 8 1

9 2

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At time 1, the sender starts putting six messages into the mailbox, at intervals one time unit apart.
The mailbox can hold at most four messages, so the sender blocks at time 5.
At time 0, the receiver attempts to retrieve a message from the mailbox. At that time, the mailbox
is empty, so the receiver waits for seven time units, and then retrieves six messages, at intervals
one time unit apart.
As the receiver takes messages out of the mailbox, the sender resumes putting messages into the
mailbox.

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Typeless Mailbox
common declarations A mailbox can hold messages of different types
class
class pkt;
 Blocking get() or peek() with
pkt;
rand
rand bit
bit [4:0]
[4:0] addr;
addr;
rand
rand logic [7:0] data;
logic [7:0] data; incompatible variable type results in
endclass
endclass runtime error
mailbox
mailbox mbox
mbox == new;
typedef enum
new;
 Non-blocking try_get() or try_peek()
typedef enum
{pass,
{pass, fail,
fail, hung}
hung} state_t;
state_t;
with incompatible variable type returns a
...
... negative integer
 Possible solution – try all types?
sender
string
string pstring;
pstring;
pkt
pkt ppkt
ppkt == new;
new; receiver
state_t
state_t pstatus;
pstatus; string gstring;
string gstring;
...
... pkt
pkt gpkt;
gpkt; ??
pstring
pstring == "test
"test one";
one"; state_t
state_t gstatus;
gstatus; ok
ok == mbox.try_get(gstring);
mbox.try_get(gstring);
assert(ppkt.randomize);
assert(ppkt.randomize); ...
... if
if (ok
(ok << 0)
0) begin
begin
mbox.put(pstring);
mbox.put(pstring); mbox.get(gstring);
mbox.get(gstring); ok
ok == mbox.try_get(gpkt);
mbox.try_get(gpkt);
mbox.put(ppkt);
mbox.put(ppkt); mbox.get(gpkt);
mbox.get(gpkt); if
if (ok
(ok << 0)
0) begin
begin
mbox.put(pstatus);
mbox.put(pstatus); mbox.get(gstatus);
mbox.get(gstatus); ok = mbox.try_get(gstatus);
ok = mbox.try_get(gstatus);
...
... ...
... ...
...

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A mailbox by default accepts messages of any type.

To retrieve a message using the blocking get() or peek() methods requires you to know the type of
the message at the head of the mailbox queue. Unless you always put and get the messages in a
preordained order, you are unlikely to know the type of the message at the head of the mailbox
queue.
You can alternatively write code that uses the non-blocking try_get() or try_peek() methods that
return a negative integer upon attempt to retrieve a message of a different type than that at the head
of the mailbox queue. This code can iterate through all the types that you place in the mailbox.
You may elect to more simply use a separate mailbox for each message type.

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Mailbox Parameters
common declarations You can type-parameterize a mailbox
class
class pkt;
pkt;
bit
bit [4:0]
[4:0] addr;
addr;  Define type upon declaration
logic [7:0] data;
logic [7:0] data;  Holds messages of that and
endclass
endclass
typedef
equivalent types
typedef enum
enum
{pass,
{pass, fail,
fail, hung}
hung} state_t;
state_t;  Compiler detects type mismatch
mailbox
mailbox #(string) smbox == new;
#(string) smbox new;
mailbox #(pkt)
mailbox #(pkt) pmbox = new;
pmbox = new;
mailbox
mailbox #(state_t)
#(state_t) tmbox
tmbox == new;
new;
...
... sender
string
string pstring;
pstring;
pkt
pkt ppkt
ppkt == new;
new; receiver
state_t
state_t pstatus;
pstatus; string gstring;
string gstring;
...
... pkt
pkt gpkt;
gpkt;
pstring
pstring == "test
"test one";
one"; state_t
state_t gstatus;
gstatus;
assert(ppkt.randomize);
assert(ppkt.randomize); ...
...
smbox.put(pstring);
smbox.put(pstring); smbox.get(gstring);
smbox.get(gstring);
pmbox.put(ppkt);
pmbox.put(ppkt); pmbox.get(gpkt);
pmbox.get(gpkt);
tmbox.put(pstatus);
tmbox.put(pstatus); tmbox.get(gstatus);
tmbox.get(gstatus);
...
... ...
...

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You can simply use a separate mailbox for each message type.
You specify the one type a mailbox may accept, by overriding its type parameter when you declare
the mailbox variable.
The compiler can now detect any attempt to store or retrieve messages of an incompatible type.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 14.4

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Semaphores
Semaphores are a key-based synchronization mechanism.
Used for mutual exclusion, controlling access to shared resources, and
process synchronization.
 A process requests semaphore key(s) before accessing the resource
 Requesting more keys than a semaphore currently has can block until
sufficient keys are returned
 Blocking: get(int keyCount=1)
 Non-blocking: int try_get(int keyCount=1)

 A process returns semaphore key(s) after accessing the resource

 int put(int keyCount=1)

 The user assumes responsibility for key management

semaphore
semaphore keybox
keybox == new(5);
new(5); //
// semaphore
semaphore with
with 55 keys
keys
semaphore sync;
semaphore sync;
sync
sync == new(4);
new(4); //
// semaphore
semaphore with
with 44 keys
keys

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Semaphores are a class-like key-based process synchronization mechanism.

A semaphore is conceptually like a basket of keys.
When you create the semaphore, you pass to its constructor the number of keys you want the
basket to initially hold. If you do not pass a number, there will be no keys.
When a process needs to access a resource, it requests a number of keys, by default just one, from
the basket. This can be a blocking request, if insufficient keys are available the process blocks, or a
non-blocking request, if insufficient keys are available an error flag is returned. The order in which
processes block is the order in which they are later serviced.
The process returns some or all of its keys when it no longer needs a portion, or any, of the
resource.
This is all the semaphore does. It is up to the user to define, manage and utilize the resource.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 14.2

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Semaphore Methods

Method Description Syntax

new() Semaphore constructor which function new(int keyCount = 0);
specifies number of keys Note default number of keys set is 0.
get() Extracts a set number of keys from the task get(int keyCount = 1);
semaphore
– blocks if the keys are not available
try_get() Extracts a set number of keys from the function int try_get(int keyCount=1);
semaphore without blocking
– returns 0 if the keys are not available
put() Returns a set number of keys to the task put(int keyCount=1);
semaphore

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The new() constructor constructs a semaphore with the specified number of keys. The default value
of its argument is 0 – no keys.
The blocking get() requests one or more keys and suspends the calling process if the key or keys
are not available. The blocked process resumes when sufficient keys to meet its needs are put into
the semaphore.
The non-blocking try_get() returns 0 if the key or keys are not available.
The put() method puts keys into the semaphore. The user is responsible for key management, for
example, to ensure that a process returns only those keys that it previously retrieved.

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Process Synchronization with Semaphore

smphre is a single-key semaphore
initial
initial begin
begin :: P1
P1
Processes access the resource between smphre.get;
smphre.get;
calls to get() and put() writemem(addr,
writemem(addr, data);
data);
#2ns;
#2ns;
 Process P1 requests a key at time 0 smphre.put;
smphre.put;
and gets it and accesses the ...
...
resource
 Process P2 requests a key at time 1 semaphore
semaphore smphre;
smphre; memory
and blocks waiting for a key smphre
smphre == new(1);
new(1);
 Process P1 completes its resource
access and returns the key initial
initial begin
begin :: P2
P2
 Process P2 unblocks, gets the key, #1ns;
#1ns;
and accesses the resource smphre.get;
smphre.get;
writemem(addr,
writemem(addr, data);
data);
 Process P2 completes its resource #1ns;
#1ns;
access and returns the key smphre.put;
smphre.put;
...
...

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In this example:
 At time 0, process P1 requests a key, and gets it, and accesses the resource.
 At time 1, process P2 requests a key and blocks, waiting for the key.
 At time 2, process P1 completes its resource access and returns the key.
• Process P2 now unblocks, gets the key, and accesses the resource.
 At time 3, process P2 completes its resource access and returns the key.

Remember the user is responsible for defining, managing and utilizing the resource. Common user
errors include:
 Writing procedural statements that access the resource without first obtaining the requisite
number of keys.
 Writing procedural statements that fail to return keys after completing the resource access.
 Writing procedural statements that return keys to the semaphore that they never took out of the
semaphore.

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Summary
This chapter explored interprocess synchronization:
 Enhanced events
 Help prevent race conditions
 Provide more control over order of execution

 Mailboxes
 Multiple-type FIFO operations with built-in blocking synchronization

 Semaphores
 Multi-purpose synchronization mechanism with built-in blocking and request
“weighting” with keys

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Pause here for a moment and review what you have learned about interprocess synchronization.

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Quiz
1. Where would you use the non-blocking event trigger?

2. True or False: Merging events creates a synchronization queue that

contains the processes from both previous synchronization queues.

3. What does a blocking get() or peek() do if the message at the head

of the mailbox queue is the wrong type?

4. What happens if a process puts more keys in a semaphore than the

process got from the semaphore?

Solutions in Appendix A

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About Labs 9, 10 and 11

In lab 9 you explore In lab 10 you In lab 11 you
the SystemVerilog synchronize multiple synchronize multiple
enhanced event processes by use of a processes by use of a
construct: event semaphore. mailbox.
handles, assignment
and comparison, the
non-blocking event
trigger, and waiting for
the triggered state of
an event.

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Direct Programming Interface (DPI)

Chapter 11

November 6, 2009

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Aims and Topics

Aims
 To describe the Direct Programming Interface (DPI)

Topics
 DPI Overview

 Data types

 Imported tasks and functions

 Pure and context definitions

 Exported tasks and functions

 Compilation

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This chapter describes the Direct Programming Interface. It shows you how to make task and
function import and export declarations, and how to compile and use the foreign language code
with your SystemVerilog simulation.

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The Verilog PLI

module
module top;
top; #include
#include <stdio.h>
<stdio.h>
...
...
$MySystemTask
$MySystemTask ...
... int
int MySystemTask
MySystemTask ...
...
...
... ...
...

The PLI is the traditional interface between Verilog and C code

Advantages Disadvantages
Powerful Difficult, even for simple operations
Safe handling of type conversion Linking is different for each simulator
Full visibility of design hierarchy Multiple applications across multiple
simulators create tool management
Synchronization to simulation events
problems

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The PLI is a true application programming interface. Through it you can access and navigate the
full design hierarchy, and can synchronize a C application to any point of simulation time or to any
simulation event. With this power comes difficulty of use, which typically limits its use to a
handful of experts in any company.

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The SystemVerilog DPI

DPI is a “lightweight” interface between SystemVerilog and “foreign” code
 Maps between SystemVerilog subroutines and external routines
 Import: SystemVerilog calls subroutines defined externally
 Export: SystemVerilog defines subroutines called externally

 The SystemVerilog side is unaware of the foreign implementation

 The standard currently accommodates only the C foreign language

module
module top; #include
top; #include <stdio.h>
<stdio.h>
... #include
... #include <svdpi.h>
import
import "DPI-C"
"DPI-C" context
context c_imp
c_imp == import <svdpi.h>
function
function int
int imp_func(...); int
imp_func(...); int c_imp
c_imp (...)
(...)
{{
export
export "DPI-C"
"DPI-C" c_exp
c_exp == ...
...
function exp_func;
function exp_func; }}

function
function int
int exp_func
exp_func ... extern
... extern int
int c_exp
c_exp (...);
(...);
...
... ...
...
endfunction
endfunction export

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The direct programming interface is a “lightweight”, compared to the PLI, interface between
SystemVerilog and foreign programming languages. It maps SystemVerilog subroutine calls to
foreign language implementations, and SystemVerilog subroutine declarations to foreign language
calls. The standard clearly separates the specification of the SystemVerilog “layer” from the
specification of each foreign “layer” so that accommodation of additional foreign languages does
not change the SystemVerilog view of the interface. The standard currently specifies only the C
foreign layer.

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DPI Characteristics
The SystemVerilog and foreign language layers are independent
 Each layer does its own data interpretation and conversion
 Each layer follows its own syntax and semantics rules
 e.g. for declaring and calling subroutines

Only SystemVerilog data types can be transferred across interface

 Can handle 2-state or 4-state data types
 Simple types have a direct mapping in both layers
 Complex types may require custom conversion

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These points are worth reiterating:

 The two layers are independent of each other. You declare subroutines and make subroutine
calls in each layer as if the other layer does not exist. You follow the syntax and semantics of
the host language for all declarations and statements and data type management.
 This requires that the data types passed between the layers be restricted to the subset that map
between the layers. This in particular excludes dynamic types such as classes and class-like
types such a covergroups and virtual interfaces, dynamic and associative arrays, and queues,
events, mailboxes and semaphores.

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Data Type Mapping

Data Type Mapping

SystemVerilog C
byte char
shortint short int
int int
No
longint long long long
type
real double
shortreal float
string const char*
chandle void*
bit † unsigned char
† requires
svdpi.h logic † unsigned char

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The mapping between SystemVerilog and foreign language data types is specified by the foreign
layer. Here we present the mapping specific to the C foreign language.
The mapping of simple SystemVerilog data types such as byte, int, real and string is
straightforward, as they have obvious C counterparts. The logic type maps to an unsigned char on
the C side to accommodate the four states. For consistency, the bit type also maps to an unsigned
char. Your C code should not use the character value directly, but should instead include svdpi.h
and use the text macros representing the four states. The SystemVerilog LRM describes the name
and core functionality of svdpi.h and permits vendors to differ in their implementations.
--------
typedef signed __int8 int8_t;
typedef uint8_t svScalar;
typedef svScalar svBit;
typedef svScalar svLogic;
#define sv_0 0
#define sv_1 1
#define sv_z 2
#define sv_x 3

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Data Type Mapping (continued)

Simple SystemVerilog data types map to corresponding C types
 #include "svdpi.h" for svBit (bit) and svLogic (logic) definitions
SystemVerilog enumerated types map to their base type (default int)
 enumerated names are not available in the C layer
SystemVerilog packed (vector) types map to a canonical representation
 #include "svdpi.h" for svBitVecVal (bit) svLogicVecVal (logic)
Unpacked types having no packed types map to corresponding C types
 unpacked arrays and unpacked structs of simple types
Unpacked types having packed types (vectors) have a vendor-specific mapping

C
SystemVerilog #include
#include <stdio.h>
<stdio.h>
module
module top;
top; #include
... #include <svdpi.h>
<svdpi.h>
...
import
import "DPI-C"
"DPI-C" context
context c_imp
c_imp == DPI int
int c_imp
c_imp (...)
(...)
function
function int
int imp_func
imp_func (...);
(...); {{ ...
...
}}

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SystemVerilog enumerated types are accessible on the C side as the enumeration base type, but the
enumeration value names are not available.
SystemVerilog packed types are accessible on the C side as arrays of the svBitVecVal type or
svLogicVecVal type as described in svdpi.h.
SystemVerilog unpacked arrays, structures and unions having only the simple types map to their
corresponding C arrays, structures and unions of their corresponding C types.
--------
typedef unsigned __int32 uint32_t;
typedef uint32_t svBitVecVal;
typedef struct vpi_vecval {
uint32_t a;
uint32_t b;
} s_vpi_vecval, *p_vpi_vecval;
typedef s_vpi_vecval svLogicVecVal;

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Importing Tasks and Functions

import "DPI-C" [property] [ c_identifier = ] prototype;
The import prototype declares how SystemVerilog “sees” the C subroutine
 Argument and return types must be compatible with that in the C layer

 You call the imported subroutine exactly as if it was in SystemVerilog

SystemVerilog
module
module parity_calculator()
parity_calculator()
...
...
import
import "DPI-C"
"DPI-C" function
function int
int parityf
parityf (input
(input int
int a);
a);
...
...
initial C
initial #include
#include <stdio.h>
<stdio.h>
...
... #include <svdpi.h>
parity #include <svdpi.h>
parity == parityf(var);
parityf(var);
...
... int
int parityf
parityf (int
(int a)
a) {{
endmodule
endmodule ...
...
return
return parity;
parity;
}}

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An import declaration imports a C function as a SystemVerilog task or function. The import

declaration maps the C function name to a SystemVerilog task or function name. After you import
a C function, you call it as if it was a SystemVerilog task or function.
--------
import "DPI-C" [context | pure] [c_identifier =] function
function_data_type function_identifier ([argument_list]);

import "DPI-C" [context] [c_identifier =] task task_identifier

([argument_list]);

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Warning: Data Type Compatibility

The compilers (C and SystemVerilog) cannot communicate.
The linker is aware of symbols, but not how they are interpreted.
YOU assume responsibility for argument direction and type compatibility!
 Declaration mismatches can lead to elaboration errors
 Type incompatibility can lead to unpredictable behavior

SystemVerilog
module
module parity_calculator()
parity_calculator()
...
...
import
import "DPI-C"
"DPI-C" function
function int
int parityf
parityf (input
(input int
int a);
a);
...
...
initial C
initial #include
#include <stdio.h>
<stdio.h>
...
... #include <svdpi.h>
parity #include <svdpi.h>
parity == parityf(var);
parityf(var);
...
... int
int parityf
parityf (int
(int a)
a) {{
endmodule
endmodule ...
...
return
return parity;
parity;
}}

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As the SystemVerilog and C layers are compiled and elaborated or linked separately, there is no
opportunity for the DPI to check function declarations or verify data type compatibility. It is
therefore critical that you match the import declaration to the C function with respect to the
function name, return type and argument types.
A name mismatch will probably result in only a “symbol not found” error. A type mismatch error
can be more serious and can lead to unpredictable effects as the C layer misinterprets the
SystemVerilog arguments.

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Import Linkage Name

import "DPI-C" [property] [ c_identifier = ] prototype;
The SystemVerilog name and C function name are by default identical
 You can optionally specify a different SystemVerilog name
 You can import a C function multiple times if the SystemVerilog names
do not clash (use different names or different scopes)
SystemVerilog
module
module one();
one();
...
...
import
import "DPI-C"
"DPI-C" parityf
parityf == function
function int
int calc_parity
calc_parity (input
(input int
int a);
a); C
initial #include
#include <stdio.h>
<stdio.h>
initial
...
... #include
#include <svdpi.h>
<svdpi.h>
parity
parity == calc_parity(a);
calc_parity(a);
... int
int parityf
parityf (int
(int a)
a) {{
...
...
...
SystemVerilog return
return parity;
parity;
module
module two();
two(); }}
...
...
import
import "DPI-C"
"DPI-C" parityf
parityf == function
function int
int calc_parity
calc_parity (input
(input int
int a);
a);
initial
initial
...
...
parity
parity == calc_parity(a);
calc_parity(a);
...
...

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By default, you call an imported subroutine using the same name as the C function. You can
specify a different SystemVerilog name for the C function if you provide the C linkage name in the
import declaration. This is useful when the C function name is a reserved word or illegal identifier
in the SystemVerilog namespace. It also allows you to import a C function multiple times with
different SystemVerilog names.
The C linkage name must of course be a legal C identifier, and if not a legal SystemVerilog
identifier, must be appropriately escaped.

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Aspects of Task and Function Import

 You can place import declarations in the compilation unit scope,
packages, interfaces, modules or programs
 Import declarations support these function return types:
 void, byte, shortint, int, longint, real, shortreal,
string, chandle, scalar values of bit or logic
 Import declarations support these formal argument types:
 Above types, packed array/struct/union of bit or logic,
enumerated types, further constructs of supported types (including
unpacked array, packed or unpacked struct, packed union, typedef)
 enumeration values map as their base type (no value names)
 C function imported as a task must return the void type
 “small” values are passed by value, others by reference

 You can give imported functions or tasks the context property

 You can give imported functions the pure property

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You can place import declarations in the compilation unit scope, packages, interfaces, modules or
programs. Placing it in a package simplifies sharing it among multiple design and test units.
You can import any C function. It is common to import functions from the C math library.
SystemVerilog returns the function results by value, so restricts the function return types to the
"small" types. It passes small arguments by value and large arguments by reference, which on the
C side means by pointer.
C functions imported as a SystemVerilog task must return the void type.
You can give a C function imported as a SystemVerilog task or function the context property. You
can give a C function imported as a SystemVerilog function the pure property. Following slides
describe these properties.

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Context Tasks and Functions

import "DPI-C" context [ c_identifier = ] prototype;
A context subroutine is aware of the context (scope) of the import
declaration. Provide imported subroutines with context if they:
 Call exported SystemVerilog subroutines
 Access any SystemVerilog objects other than through their arguments
 e.g. through PLI or VPI routines

An imported subroutine that is not context and not pure can access
variables only in its own name spaces and can make calls to the operating
system, to for example, access the filesystem.

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The context property makes the imported task or function aware of the context, that is the scope, of
its declaration. Do not confuse this with the scope of its invocation. A “context” import can,
through exported subroutines or the PLI, access simulation objects in its own context. To access
objects in other contexts, it needs to change its context. The svdpi.h header defines the
svSetScope() routine for setting the context.
An imported subroutine that is not context and not pure can access variables only in its own name
spaces and can make calls to the operating system, to for example, access the filesystem.

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Pure Functions
import "DPI-C" pure [ c_identifier = ] prototype ;
The SystemVerilog implementation can optimize calls to pure functions.
You can provide imported functions with the pure property if:
 They return a non-void value
 They have at least one input and no output or inout arguments

 The result depends solely on the values of the input arguments

 They do not directly or indirectly:

 Perform any file operations
 Access any persistent data
 Read or write anything

You cannot provide imported tasks with the pure property.

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The pure property informs the implementation that the imported function returns a non-void value
and has at least one input argument and no output or inout arguments and has no side-effects
whatsoever. The implementation can optimize the function call. The pure property cannot apply to
imported tasks.

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Exporting Tasks and Functions

export "DPI-C" [c_identifier =] {function | task} name;

The export declaration makes the SystemVerilog subroutine visible in the C

global name space
 Argument and return types must be compatible with those in C layer
 You call the exported subroutine exactly as if it was in C

SystemVerilog
module
module dpi_test()
dpi_test()
...
...
export
export "DPI-C"
"DPI-C" function
function parityf;
parityf;
...
...
initial
initial C
...
... #include
#include <stdio.h>
<stdio.h>
function
function int
int parityf(input
parityf(input int
int a);
a); #include
#include <svdpi.h>
<svdpi.h>
...
... extern
extern int
int parityf(int
parityf(int a);
a);
endfunction
endfunction ...
endmodule ...
endmodule int
int ii == parityf(val);
parityf(val);
...
...
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An export declaration exports a SystemVerilog subroutine as a C function. The export declaration

maps the SystemVerilog task or function name to a C function name. After you export a
SystemVerilog task or function, the C layer makes an extern declaration and calls it as if it was a C
function.
--------
export "DPI" [c_identifier =] function function_identifier;
export "DPI" [c_identifier =] task task_identifier;

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Export Linkage Name

export "DPI-C" [c_identifier =] {function | task} name;
The SystemVerilog subroutine name and C function name are by default identical
 You can optionally specify a different SystemVerilog name
 You can export a SystemVerilog task or function only once
 You can export multiple SystemVerilog tasks or functions to the same C
identifier if exported from different scopes and the signatures are identical
SystemVerilog
module
module one(...);
one(...);
...
...
export C
export "DPI-C"
"DPI-C" parityf
parityf == function
function calc_parity;
calc_parity; #include
#include <stdio.h>
<stdio.h>
function
function int
int calc_parity(input
calc_parity(input int
int a);
a); #include
#include <svdpi.h>
<svdpi.h>
...
...
endfunction
endfunction int
int word,
word, parity;
parity;
extern
extern int parityf(int);
int parityf(int);
void
void dostuff(){
dostuff(){
SystemVerilog
module ...
module two(...);
two(...); ...
...
... parity
parity == parityf(word);
parityf(word);
export
export "DPI-C"
"DPI-C" parityf
parityf == function
function calc_parity;
calc_parity; }}
function
function int
int calc_parity(input
calc_parity(input int
int a);
a);
... dostuff() called from
...
endfunction SystemVerilog context
endfunction
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By default, you call an exported subroutine using the same name as the SystemVerilog subroutine.
You can specify a different SystemVerilog name for the C function if you provide the C linkage
name in the export declaration. This is useful when the SystemVerilog subroutine name is a
reserved word or illegal identifier in the C namespace. As every call of an exported SystemVerilog
task or function is associated with a context, you can export a SystemVerilog task or function
multiple times to the same C identifier if the exports are declared in different scopes and have the
same signature. that is, return type, name, and argument types.
The C linkage name must of course be a legal C identifier, and if not a legal SystemVerilog
identifier, must be appropriately escaped.

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Aspects of Task and Function Export

You can place export declarations in the compilation unit scope, packages,
interfaces, modules or programs. Export declarations:
 Can export only those subroutines defined in their own scope
 Can export a subroutine no more than once

 Cannot export class member methods

Exported subroutines:
 Accept the same argument data types as imported subroutines

 Are always “context” (aware of their scope)

 Can be called by imported “context” subroutines
 Functions cannot call tasks

 Exported tasks can consume time

 This is how you create a time delay in the C layer
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You can place export declarations in the compilation unit scope, packages, interfaces, modules or
programs. Placing it in a package simplifies sharing it among multiple design and test units.
An export declaration can export only the subroutines declared in its own scope, and can export a
subroutine at most once. An export declaration is illegal within a class type declaration and so
cannot export a class method.
An imported subroutine with the “context” property can call an exported subroutine. This is how
you create a time layer in C. The time is actually consumed by the exported SystemVerilog task
called by an imported task. A SystemVerilog function cannot of course call a SystemVerilog task
regardless of what language actually implements the task.

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Imported and Exported Functions Example

module
module top;
top;
bit
bit b1
b1 == 1’b1,
1’b1, b2
b2 == 1’b0;
1’b0;
int
int res_top;
res_top;

import
import "DPI-C"
"DPI-C" context
context c_func
c_func ==
function
function int import_c_func ((
int import_c_func
input
input bit
bit bin1,
bin1,
inout
inout bit bin2
bit bin2 );
);

export
export "DPI-C"
"DPI-C" sv_func
sv_func == function
function export_sv_func;
export_sv_func;

function
function int
int export_sv_func(input
export_sv_func(input bit
bit eb1,
eb1, #include
#include <stdio.h>
<stdio.h>
inout
inout bit
bit eb2
eb2 );
); #include <svdpi.h>
if (eb1 != eb2)
#include <svdpi.h>
if (eb1 != eb2)
...
...
endfunction extern
extern int
int sv_func(svBit,
sv_func(svBit, svBit*)
svBit*)
endfunction

initial
initial begin
begin int
int c_func
c_func (svBit
(svBit b1,
b1, svBit
svBit *b2)
*b2)
#2
#2 res_top
res_top == import_c_func(b1,
import_c_func(b1, b2);
b2); int
int res;
res;
$display("res_top
$display("res_top :: %d\n",
%d\n", res_top); printf(" b1
res_top); printf(" b1 == %d,
%d, b2
b2 == %d\n",
%d\n",
end
end b1,
endmodule b1, *b2);
*b2);
endmodule res
res = sv_func(b1, b2);
= sv_func(b1, b2);
printf("
printf(" b1
b1 == %d,
%d, b2
b2 == %d\n",
%d\n",
b1,
b1, *b2);
*b2);
return res;
return res;
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}} 222

The SystemVerilog initial block calls the “import_c_func”, which is linked to the C function
named “c_func” in the import declaration. This function is imported with the context property so
that it can in turn call exported SystemVerilog subroutines.
The C implementation of the “c_func” function calls the “sv_func” function that it has previous
declared to have external linkage. This function is linked to the SystemVerilog function named
“export_sv_func” in the export declaration.

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The Disable Handshake

You can disable (Verilog construct) a call to an imported subroutine.
Your C code must respect and acknowledge the disable <- i.e. a requirement.
 The disable manifests only on return from calling an exported subroutine
 An exported task returns an int (1=disabled,0=normal)
 Remember all C layer subroutine calls are function calls
 For an exported function, caller must check svIsDisabledState()

 The imported subroutine may not call any more exported subroutines

 The imported subroutine must acknowledge the disable

 An imported task must return an int (1=disabled,0=normal)
 Remember all C layer subroutine declarations are function declarations
 An imported function must call svAckDisabledState()

 SystemVerilog simulators are not required to propagate the returned values

You code this handshake for all imported subroutines that call exported subroutines.
No handshake mechanism exists for disabled exported subroutines.

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The SystemVerilog statement calling an imported subroutine may become disabled. This is
important if the imported subroutine calls exported subroutines, for a disabled statement must have
no further visible effect in the SystemVerilog layer.
Upon return from the exported subroutine call, SystemVerilog advises the imported subroutine that
its call has been disabled. An exported task call returns 1 rather than 0 to flag the disable. The
imported subroutine can also call svIsDisabledState() to check its status.
A disabled imported subroutine must immediately cease any activity in the SystemVerilog layer
and must acknowledge the disable. An imported task returns 1 rather than 0, and an imported
function calls svAckDisabledState().
Pause here to examine this disable handshake protocol.

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Example disable Handshake for Imported Functions

module
module test;
test;

function
function void
void voidExportFunc();
voidExportFunc();
disable
disable disableMe;
disableMe;
$display("exportTask
$display("exportTask exit");
exit"); //
// no
no display
display
endfunction : voidExportFunc
endfunction : voidExportFunc

export
export "DPI-C"
"DPI-C" function
function voidExportFunc
voidExportFunc ;;
import
import "DPI-C"
"DPI-C" context function void voidImportFunc()
context function void voidImportFunc() ;;

initial
initial
begin
begin :: disableMe
disableMe
voidImportFunc();
voidImportFunc();
end
end

endmodule
endmodule :: test
test #include
#include <stdio.h>
<stdio.h>
#include
#include "svdpi.h“
"svdpi.h“
extern
extern void
void voidExportFunc();
voidExportFunc();
void
void voidImportFunc()
voidImportFunc() {{
voidExportFunc();
voidExportFunc();
printf("svIsDisabledState()
printf("svIsDisabledState() is
is %d\n",svIsDisabledState());
%d\n",svIsDisabledState());
if
if (svIsDisabledState())
(svIsDisabledState()) svAckDisabledState();
svAckDisabledState();
}}

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An imported subroutine that calls an exported subroutine must comply with the disable protocol.
That protocol requires the imported subroutine, upon return from calling an exported subroutine, to
check whether it, the imported subroutine, was disabled. If it is disabled, it may not call any more
exported subroutines and must acknowledge the disable.
This example calls an imported function from within a named block. The imported function in turn
calls an exported function. The exported function disables the named block, causing the imported
function call to terminate abnormally. Upon return from calling the exported function, the imported
function must check its disabled status, and if disabled, must acknowledge it.
Pause here to examine this disable of the call to an imported function.

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Example disable Handshake for Imported Tasks

module
module test;
test;

task
task exportTask();
exportTask();
#1
#1 disable
disable disableMe;
disableMe;
#1
#1 $display("exportTask exit");
$display("exportTask exit"); //
// no
no display
display
endtask : exportTask
endtask : exportTask

export
export "DPI-C"
"DPI-C" task
task exportTask
exportTask ;;
import
import "DPI-C" context task
"DPI-C" context task importTask()
importTask() ;;
initial
initial

begin
begin :: disableMe
disableMe
importTask;
importTask;
end
end

endmodule
endmodule :: test
test #include
#include <stdio.h>
<stdio.h>
#include
#include "svdpi.h"
"svdpi.h"
extern
extern int
int exportTask();
exportTask();
int
int importTask()
importTask() {{
int
int disabled
disabled == exportTask();
exportTask();
printf("exportTask
printf("exportTask returned
returned %d\n",disabled);
%d\n",disabled);
printf("svIsDisabledState()
printf("svIsDisabledState() isis %d\n",svIsDisabledState());
%d\n",svIsDisabledState());
return
return disabled;
disabled;
}}

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An imported subroutine that calls an exported subroutine must comply with the disable protocol.
That protocol requires the imported subroutine, upon return from calling an exported subroutine, to
check whether it, the imported subroutine, was disabled. If it is disabled, it may not call any more
exported subroutines and must acknowledge the disable.
This example calls an imported task from within a named block. The imported task in turn calls an
exported task. The exported task disables the named block, causing the imported task call to
terminate abnormally. Upon return from calling the exported task , the imported task must check its
disabled status, and if disabled, must acknowledge it.
Pause here to examine this disable of the call to an imported task.

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Compilation
SystemVerilog recommends two alternatives for including the linked C object code:
 By directly providing the library name with the -sv_lib option

 By entry in a bootstrap file whose name is provided with -sv_liblist

 Optionally providing a path prefix with –sv_root

SystemVerilog elaborator
compiler

 simulator
top.v top top

C compiler linker


taskfunc.c taskfunc.o myLib.so

<sim> mvDesign -sv_lib myLib

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The actual usage methodology is vendor dependent, but is likely to be something like this:
 You separately compile your C code and link it into a shared object library with a platform-
specific extension, such as .sl or .so for UNIX variants and .dll for Windows.
 You compile, elaborate and simulate your SystemVerilog code as usual, and provide the
shared-object library to the simulator.

The standard recommends that command line options be provided for this purpose, and even
suggests names for them:
 The -sv_lib option provides a pathname for the shared object library minus its extension – the
tool provides the correct extension for the platform.
 The -sv_root option provides a single directory path that is prefixed to any relative path
specified by the -sv_lib option.

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DPI Summary
Advantages Potential Issues
Easy to use No arbitrary data types
 Standard interface  SystemVerilog types only
 if no packed types  Packed array and struct layout is
 Doesn’t require new simulator dependent upon platform and
executable implementation

 Look and feel of standard Does not replace PLI

SystemVerilog subroutines  No access to simulation data
Easy access to standard C functions structure

Bi-directional interface  No synchronization with simulation

events
 SystemVerilog can call C

 C can call SystemVerilog

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Pause here for a moment and review what you have learned about the direct programming
interface.

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Quiz
1. Write a function import statement to import the exp2f function (from the
cmath library) with the base2exp SystemVerilog identifier. Assume the
C function has no side effects. The C function prototype is:
float exp2f(float x);

2. True or False: The standard supports import and export of class

methods.

3. How do you make an imported task (implemented in C) consume time?

4. How does an imported function that calls an exported function detect

and acknowledged that the call to the imported function is disabled?

Solutions in Appendix A

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About Lab 12
In lab 12, you replace a C++ transaction-level model with an equivalent
SystemVerilog model that you create. To do this, you determine the
appropriate SystemVerilog data type for the function arguments, write and
export the functions, and on the C++ side declare the functions to have
external linkage.

system_c :
system
system_c.h packet_c :
packet
packet_c.h

producer_c : consumer_c :
producer consumer
producer_c.h consumer_c.h

channel_c : channel (channel_c.h)

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Introduction to Assertion Based Verification

Chapter 12

November 6, 2009

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Aims and Topics

Aims
 Overview of Assertion Based Verification (ABV)

Topics
 What is an assertion?

 What is Assertion Based Verification (ABV)?

 Who writes assertions – for what purpose?

 Why you should use assertions

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This chapter introduces assertion-based verification: what it is, what it does, and why you might
want to adopt the methodology.

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What is an Assertion?
An assertion is a check embedded in, or
bound to, a design unit
During simulation, assertions watch to
see:
Testbench
 If a specific condition occurs, or

 If a specific sequence of events A A

A A A
occurs
Assertions generate warnings or errors B1 B2
when:
DUV
 A specified condition fails, or
HDL
 A specified sequence does not
complete
Assertions offer a way to significantly
enhance productivity for designers
 Find bugs earlier and more easily

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An assertion is just a statement that something is true. What’s important about an assertion is that it
asserts that some design property holds, and the simulator reports the failure of that design property
to hold. Stating the assertion is the easy part. Crafting useful design properties is more difficult.
However, it’s far easier than debugging a broken system without the help of assertions.
The graphic illustrates where you can place an assertion. Note that you can place them on design
inputs and design outputs and design interconnect and in the design blocks. You do not typically
see assertions on a testbench.

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What is Assertion Based Verification (ABV)?

Assertion-Based Verification is the
structured use of assertions to describe Interface Functional Protocol
and check design properties Assertions Assertions Assertions

DUV
Assertions monitor and report:
 Expected behavior

 Forbidden behavior Arbiter

PCI
Bus
Assertions are used by:
FIFO FSM
 Static verification tools
Processor
 no test vectors AHB
Bus
 Dynamic verification tools
 dependent upon test effectiveness (as
measured using functional coverage)

11/6/2009 SystemVerilog for Verification 233

Assertion-based verification is a verification methodology that utilizes assertions. This slide pretty
much reiterates what we have just said. It does also point out that assertions are not limited to just
simulation tools. Formal verification tools, that do their verification statically, typically with very
little helper test stimulus, if any, also use assertions.

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Assertions Are Not New ...

You have been “asserting” correct design conditions right along, using:
if ( !good_condition ) $display ( error_message ) ;

`ifndef
`ifndef SYNTHESIS
SYNTHESIS
always @GNT
always @GNT
@(negedge
@(negedge clk)clk)
if
if (( GNT
GNT !=!= 4’h0
4’h0 ))
begin: GNT_CHK
begin: GNT_CHK
integer
integer cnt,cnt, idx;
idx;
cnt =
cnt = 0 ;0 ;
for
for (( idx
idx == 0;0; idx
idx <=
<= 3;
3; idx
idx == idx+1
idx+1 ))
if
if (( GNT[idx]
GNT[idx] !=!= 1’b0
1’b0 )) cnt
cnt == cnt
cnt++ 1;
1;
if
if ( cnt > 1 ) $display ( "ERROR: Multiple GNT"
( cnt > 1 ) $display ( "ERROR: Multiple GNT" );
);
end
end
`endif
`endif

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Verification personnel writing Verilog testbenches have been using an informal type of assertion
right along. They write a process, that upon appropriate events, checks that some expression has
the desired value, and if not, takes appropriate action. They can even write a check that spans
multiple cycles, although that is more difficult, and thus rare.

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… But Formal Syntax and Semantics Help ...

Assertion-Based Verification goes well beyond HDL-based assertions:
 Standard language constructs to concisely express temporal behaviors
 PSL and SVA

 Standard tool support taking advantage of the new constructs

 Failure messaging
 Statistics gathering
 Debug features

11/6/2009 SystemVerilog for Verification 235

The use of assertions is not new. What is relatively new is the standardization of language
constructs with which you can concisely express temporal design behaviors, and consistent support
of those constructs, with failure messages, statistics collection and reporting, and user-friendly
debug features.

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... And Have a Long History of Successful Use!

Assertion Monitors 34% 34% of all bugs found were identified by assertions
Cache Coherency Checkers 9% on DEC Alpha 21164 project
Register File Trace Compare 8% [Kantrowitz and Noack DAC 1996]
Memory State Compare 7%
End-of-Run State Compare 6% 17% of all bugs found were identified by assertions
PC Trace Compare 4% on Cyrix M3(p1) project.
Self-Checking Test 11% [Krolnik '98]
Simulation Output Inspection 7%
Simulation hang 6% 25% of all bugs found were identified by assertions
Other 8%
on DEC Alpha 21264 project.
[Taylor et at.DAC 1998]
Kantrowitz and Noack [DAC 1996]
50% of all bugs found were identified by assertions
on Cyrix M3(p2) project
Assertion Monitors 25% [Krolnik ‘98]
Register Miscompare 22% 85% of all bugs were found using over 4000
Simulation "No Progress” 15%
PC Miscompare 14%
assertions on HP
Memory State Miscompare 8% [Foster and Coelho HDLCon 2000]
Manual Inspection 6%
Self-Checking Test 5%
10,000 assertions in Cisco RTL project
[Sean Smith 2002]
Cache Coherency Check 3%
SAVES Check 2% 1000's of assertions in Intel Pentium project
[Bentley 2001]

Taylor et al. [DAC 1998]

Many other examples. . . . .

http://www.dac.com

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The key points of this slide are:

 That assertions have been used successfully in many real projects, and
 That assertions have been proven to be very effective in finding bugs.

A quick revisit to the DAC archives will reveal that use of assertions is pretty much mainstream
now.

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Who Writes Assertions and Why?

Who Type of Assertion Reason Example

An asynchronous FIFO does not

System Ensure implementation meets
Abstract properties indicate full and empty at the same
Architects functional spec.
time.

RTL Implementation has properties the When Read and Write pointers
Functional Property
Designer RTL designer intended it to have. both 0, the FIFO indicates empty.

IP Indicate to IP User that the IP

Correct use of IP FIFO was read when it was empty.
Designer is not being used correctly.

Ensure test stimulus exercises the

Verification Did we read from full FIFO, write to
Functional Coverage corner cases as required by
Engineer the last empty FIFO location, etc.
the test plan

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A system architect develops abstract properties that represent the desired behavior of the system at
the functional level. At this point the actual implementation is not known.
The block designer develops objective properties that represent the desired behavior of the system
at the register level. It is important to verify this reinterpretation of the architect’s properties.
As an IP designer, the RTL designer will want to embed input assertions in the design to detect
future misuse of the design.
The verification engineer focuses on design functional coverage points, which should include that
the testbench actually exercised the asserted properties. Thus, functional coverage is a fundamental
part of an Assertion Based Verification methodology.

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Why Use Assertions?

 Improved observability – assertions are embedded in the design

 Close to potential source of bugs

 No need to propagate error to outputs and “back-track" to source

 Automatically and constantly checks behavior

 Improved verification efficiency

 Writing assertions helps designers to produce better designs

 Forces them to concisely and unambiguously document their design intent
 Encourages them to better understand their design
 Detects bugs far earlier in the design cycle

 Verification personnel can focus on system-level issues

 Embedded assertions travel with the design from:

 Project to project – ideal for IP

 Tool to tool – ideal for design methodology integrity

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You can place assertions anywhere in your design hierarchy, enabling you to monitor design
behavior locally and highlight problems as soon as they occur at the source of the problem.
Conventional testbenches need to propagate a problem to the design outputs to detect it, and then
you have to trace the error back through the design, and probably back through time as well, to
determine the source. Assertions have the potential to detect problems during the early stages of
testbench development, when the testbench might not yet be sufficiently robust to even propagate a
problem to the outputs.
You can have the simulation terminate upon failure of critical assertions, thus permitting other
projects to use the compute cycles that would otherwise be wasted.
Writing design properties encourages you to think more clearly about your design. This itself can
highlight problems before you even finish the property. Overall verification efficiency is improved
by designers producing better designs to begin with.
Your embedded assertions travel with your design as it is used in different projects, warning
against unexpected or incorrect use of your design block.
Your embedded assertions also travel with your design from tool to tool, for example from
simulation to formal verification, avoiding duplication of the verification effort.

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Issues with Assertions

 You must carefully construct the asserted property

 It’s easy to define a property that is not really 100% true

 even easier to define properties that miss design behavior nuances

 How do you know when your property set is sufficiently complete?

 Quality of test stimulus is critical

 The simulator can make only those checks that the test exercises

 Coverage metrics reveal what checks are exercised

 Checking assertions consumes platform cycles

 Other issues as we will see...

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The most prominent issue with the Assertion Based Verification methodology is that you, the user,
must craft the design properties. It’s very easy to construct a property that is not really 100% true.
It’s even easier, perhaps very common, to miss nuances of design behavior, some corner cases, that
really ought to be checked. There is also the issue of “how do you know when your property set is
sufficient”.
The simulator can check only those properties that the testbench exercises, so testbench quality is
critical. This demands coverage metrics, which help to solve the “how do you know when you have
tested enough” question, but do nothing for the “how do you know when your property set is
sufficient” question.

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Summary
 Complex properties are difficult to write using Verilog

 A dedicated syntax like SystemVerilog Assertions helps greatly

 Assertions can reduce debugging time by identifying incorrect design
behavior when and where it occurs. The Assertion Based Verification
methodology:
 Captures specifications
 Captures design assumptions

 Documents interfaces

 Provides white-box visibility in simulation

 Supports advanced verification technologies
 Simulation, acceleration, emulation
 Functional coverage
 Static (formal) verification

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Pause here for a moment, and review what you have learned about assertion-based verification.

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Quiz
1. What is an assertion?

2. True or False: Formal (static) verification tools can also utilize

assertions.

3. What obvious incentive does an IP designer have for embedding

assertions?

Solutions in Appendix A

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Introduction to SystemVerilog Assertions

Chapter 13

November 6, 2009

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Aims and Topics

Aims
 To introduce SystemVerilog Assertions

Topics
 Concurrent assertion structure

 Creating a simple concurrent assertion

 Conditional assertions (implication)

 Multi-cycle sequences
 Repetition in sequences

11/6/2009 SystemVerilog for Verification 243

This chapter introduces SystemVerilog Assertions: how to declare and assert design properties,
some property operators, and some sequence operators with which you can construct more
complex properties.

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Concurrent Assertions
 Embedded in functional code and ignored by synthesis

 Supported by mainstream simulators and formal verification tools

 You define and assert functional properties of a design

 A boolean expression about some design behavior

 What it should or should not do

 Can be single or multiple cycle

 Uses Verilog syntax, yet …

 Mathematically precise and computationally efficient

 Sufficiently expressive to specify “real world” design properties

11/6/2009 SystemVerilog for Verification 244

We have previously learned that an immediate assertion is a procedural statement that some
boolean condition is true. The assertion is checked when the procedural statement executes.
You typically place concurrent assertions outside procedural blocks to execute concurrently with
the procedural blocks and utilize their own clock event.
A property is a design behavior that may span multiple cycles. It is a design requirement, similar to
a synthesis constraint that the design must work with a 250MHz clock. SystemVerilog has special
operators you use to develop concise property expressions to represent complex multicycle design
behavior.

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Concurrent Assertion Structure

Let's examine the following required design behavior:
“wr_en and rd_en are never both high at the negative edge of the clock”

rw_chk
label : assert property ( [clocking_event]
@(negedge clock) !(wr_en
property_spec && rd_en)
property_expr );

Label Assertion Property Clocking Event Boolean Expression

Statement Directive A design The property is evaluated on For the property to hold, this
label. to check behavior. each clock. expression must be true.
property
property. Usually (but not here) temporal.

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This slide illustrates the construction of a concurrent assertion.

 You can label any statement, but you especially should label an assertion statement, so that the
tool can, upon assertion failure, clearly report to you the failing assertion.
 The assert keyword creates the assertion, and the property keyword indicates that this is a
concurrent assertion. The asserted property specification is always enclosed in parentheses.
 The property specification has a property expression that can be preceded by a clocking event.
The tool evaluates the property expression upon a clocking event, so all assertions must be
clocked. The clock can be part of the property specification, part of a property expression, and
can be specified other places as well.
• The clocking event can be as simple as a Verilog event expression, as shown here, but can
also be more complex.
• The property expression can be as simple as a Verilog expression, as shown here, but is
often much more complex.
--------
assert_property_statement ::=
assert property (property_spec) action_block
property_spec ::=
[clocking_event] [disable iff (expression_or_dist)]
property_expr
property_expr ::= sequence_expr | ...
sequence_expr ::= expression_or_dist [ boolean_abbrev ] | ...

IEEE Std. 1800-2005 SystemVerilog LRM, Section 17.13

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Creating a Simple Property

A design property can be as simple as a single-cycle boolean expression
 Identical to an if condition

 Any Verilog expression syntax

EN1
EN1 ||
|| EN2;
EN2;

((A
((A ++ B)
B) >=
>= 42)
42) &&
&& (C
(C ||
|| D);
D);

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A property expression can be simply a boolean expression. Use parentheses where needed to
appropriately group the operands and to enhance readability.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 17.4

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Naming and Asserting the Property

You have two options:
 Define the property inline with the assertion statement

ASSERT1
ASSERT1 :: assert
assert property
property (( @(EN1
@(EN1 or
or EN2)
EN2) EN1
EN1 ||
|| EN2
EN2 );
);
assertion
parentheses

 Name and assert the property in separate statements

required

 Property can be used as a building block in other properties

 Property can have arguments

property
property PROP1;
PROP1;
@(EN1
@(EN1 or EN2)
or EN2) EN1
EN1 ||
|| EN2;
EN2;
endproperty
endproperty

ASSERT1
ASSERT1 :: assert
assert property
property (PROP1);
(PROP1);

always label
assertions
Labels are used to reference the assertion
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You can specify the property within the assertion statement itself. Be sure to label the assertion
statement so that upon assertion failure the tool reports a name that is meaningful to you.
Otherwise the tool reports the scope of the assertion.
You can alternatively declare and name the property. You can parameterize a declared property.
You can instantiate the declared property as an operand in a property expression that uses property
operators. If you assert the named property and omit the assertion statement label, the tool can
upon assertion failure report the property name.
The assertion label and property name must be valid Verilog identifiers. They reside in the module
name space and must not clash with other identifiers in that name space.
--------
property_declaration ::=
property property_identifier [ ( [ tf_port_list ] ) ] ;
{ assertion_variable_declaration }
property_spec ;
endproperty [ : property_identifier ]

IEEE Std. 1800-2005 SystemVerilog LRM, Sections 17.11, 17.13.1

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Clocking the Property

Properties are evaluated upon clocking events
 Verilog @identifier or @(event_expression)
 Accepts any variable or combination of variables
 SystemVerilog @(event_expression) enhancements
 sequence endpoint events
 iff qualifier
 All assertions must be clocked!

property
property PCLK1;
PCLK1;
@(posedge
@(posedge CLK)
CLK) EN1
EN1 ||
|| EN2;
EN2;
endproperty
endproperty
property
property PCLK2;
PCLK2;
@(EN1
@(EN1 or
or EN2)
EN2) EN1
EN1 ||
|| EN2;
EN2;
endproperty
endproperty
property
property PCLK3;
PCLK3;
@(negedge
@(negedge ADDR_EN)
ADDR_EN) ADDR
ADDR <=
<= 7;
7;
endproperty
endproperty

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All assertions must be clocked. You can specify the clock in a sequence expression that the
property uses, or in the property specification.
The clocking event is typically just the Verilog event control. The parenthesized syntax also
accepts a sequence name and the SystemVerilog “if-and-only-if” (iff) clock qualifier. For a
sequence name, it is the endpoint of the sequence that clocks the property. Of course that sequence
itself must also be clocked.
--------
event_expression ::=
[ edge_identifier ] expression [ iff expression ]
| sequence_instance [ iff expression ]
| event_expression or event_expression
| event_expression , event_expression

IEEE Std. 1800-2005 SystemVerilog LRM, Section 17.14

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Input Sampling and Property Evaluation

Each SystemVerilog simulation cycle is sample
Preponed
divided into a series of time slots. property
signals
This helps avoid race conditions between Active
block execution and assertion evaluation. evaluate
initial/always
property
property PIPE;
PIPE;
blocks Inactive
@(posedge
@(posedge clk)
clk)
ip
ip ->
-> ##2
##2 op; complete
op; NBA
end
end property: PIPE
property: PIPE non-blocking
assignments
always
always @(posedge
@(posedge clk)
clk)
temp <= evaluate
Observed
temp <= ip;
ip;
properties
always
always @(posedge
@(posedge clk)
clk)
op Re-active
op <=
<= temp;
temp;
evaluate
A_PIPE
A_PIPE :: assert
assert property
property (PIPE)
(PIPE) action
$display("PIPE succeeded");
$display("PIPE succeeded");
blocks Re-inactive
else
else
$warning("PIPE
$warning("PIPE failed");
failed");
Postponed

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A SystemVerilog simulation time instant is divided into several regions. The regions separate
various activities in order to help avoid races between the writing and reading of a variable.
Assertion evaluation occurs in the Observed region, after all current variable updates complete, but
uses sampled values from the Preponed region to evaluate the sequence and property expressions.
This means that you can safely use the same clock edge to clock the assertions that you use to
update the variables. Assertion evaluation uses the pre-clock values.
This diagram omits several regions used only for PLI callbacks.

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Illustration of Property Evaluation

All property assertions are clocked
property
property EN_1HOT;
EN_1HOT;
Evaluation uses sampled values @(EN1
@(EN1 OR EN2)
OR EN2) EN1
EN1 ||
|| EN2;
EN2;
endproperty
i.e. pre-clock values endproperty

 Evaluates EN_1HOT when EN1 property

property EN_1HOT_CLK;
EN_1HOT_CLK;
changes or EN2 changes @(posedge
@(posedge CLK)
CLK) EN1
EN1 ||
|| EN2;
EN2;
endproperty
endproperty
 2 evaluations, 1 failure
 using values before change
EN_1HOT succeeds
 Evaluates EN_1HOT_CLK on EN_1HOT fails

positive edge of CLK EN1

 2 evaluations, 2 successes
EN2
 using values before
posedge CLK CLK

EN_1HOT_CLK succeeds

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Clock asynchronous properties on any change of any signal used in the property expression.
Clock synchronous properties on the appropriate edge of the appropriate clock signal.
Property expression evaluation uses the sampled values, that is, the values before the clock event.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 17.3

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Assertion Placement
You can declare a property in a
compilation unit scope, package,
interface, module, program or module
module mod1
mod1
clocking block. (input
(input logic
logic CLK,
CLK,
...
...
You can assert a property only output
output logic
logic EN1,
EN1, EN2);
EN2);
within an interface, module or
`ifndef
`ifndef USING_OLD_TOOL
program, or always or initial block. USING_OLD_TOOL
property
property PROP1;
PROP1;
@(posedge
@(posedge CLK)
CLK) EN1
EN1 ||
|| EN2;
EN2;
endproperty
endproperty
What to do about old tools that do
ASSERT1:
ASSERT1: assert
assert property
property (PROP1);
not know about SystemVerilog? `endif
`endif
(PROP1);

...
 Does the tool pre-define a text ...
macro?
 Or use bind construct (later
chapter) with new tool to bind
separate assertion modules
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You can declare a property, as a type, in the compilation unit scope, package, interface, module,
program or clocking block. You can assert the property only in an interface, module, or program,
or in an always or initial block.
SystemVerilog does not predefine a macro that you can use to “hide” code from compilers that do
not support it. Perhaps the compiler itself defines a macro you can use to bypass compilation of the
SystemVerilog assertions.
SystemVerilog provides a “bind” construct with which you can externally, perhaps from the
testbench, instantiate assertion components within a module without modifying the module
description.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Sections 17.11, 17.13

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Sequences
You cannot write a complex temporal property
using only the property operators sequence
@(negedge
@(negedge CLK)
CLK)
Special operators that construct sequences AA ##1
##1 BB ##1
##1 C;
C;
facilitate writing properties that span time
Sequences are building blocks of properties CLK

Shown here is sequence concatenation A

 Sequences joined by cycle delay B

 Here each sequence is just a boolean C

Sequence operators include: start end
 Replication

 Matching

 Composition

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You cannot write a complex temporal property using only the property operators. The only
property operator that connects two cycles is the next-cycle implication (|=>) operator, and you
cannot chain this operator because the resulting expression is a property and the left operand must
be a sequence.
A sequence is a series of boolean conditions over successive cycles.
The “pound pound” (##) token is the cycle delay operator. Here we are using it to construct the
sequence “A followed by B followed by C” in successive evaluations. Here the inputs are boolean
signals, but they could be boolean expressions or even sequences of boolean expressions.
This chapter later more fully describes the cycle delay operator.

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Same Cycle Sequence Implication: |->

For properties that only conditionally
property
property SCI;
must hold use: SCI;
@(negedge
@(negedge CLK)
CLK)
sequence |-> property (REQ
(REQ && !ACK) |->
&& !ACK) |-> BSY;
BSY;
Overall property holds if: endproperty
endproperty
 Antecedent sequence does not
complete
CLK
 Consequent property holds in the
REQ
same cycle the antecedent
sequence completes ACK
 Sequence and/or property can be BSY
single or multiple cycle
SCI
holds

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SystemVerilog provides two sequence implication operators. This is the “same cycle” implication
operator. For this operator, the consequent property must hold in the same cycle in which the
antecedent sequence completes. This operator is a property operator, that is, the resulting
expression is a property expression which you can use as an operand in yet another property
expression.
For this example, the left side sequence and right side property are both non-temporal, so you can
replace this same-cycle implication with a simple boolean expression.
--------
property_expr ::= ... | sequence_expr |-> property_expr | ...

IEEE Std. 1800-2005 SystemVerilog LRM, Section 17.11.2

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Next Cycle Sequence Implication: |=>

For properties that only conditionally
property
property NCI;
must hold use NCI;
@(negedge
@(negedge CLK)
CLK)
sequence |=> property (REQ
(REQ && !ACK) |=>
&& !ACK) |=> BSY;
BSY;
Overall property holds inf: endproperty
endproperty
 Antecedent sequence does not
complete
CLK
 Consequent property holds in the
REQ
cycle after the antecedent sequence
completes ACK
 Sequence and/or property can be BSY
single or multiple cycle
NCI NCI
active finish

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SystemVerilog provides two sequence implication operators. This is the “next cycle” implication
operator. For this operator, the consequent property must hold in the cycle after that in which the
antecedent sequence completes. This operator is a property operator, that is, the resulting
expression is a property expression which you can use as an operand in yet another property
expression.
--------
property_expr ::= ... | sequence_expr |=> property_expr | ...

IEEE Std. 1800-2005 SystemVerilog LRM, Section 17.11.2

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Sequence Property Analysis

property
property STATE;
STATE;
@(negedge
@(negedge CLK)
CLK) (A
(A ##1
##1 B)
B) |=>
|=> C;
C;
endproperty
endproperty

1 2 3 4 5 6 7 8

CLK

C
1-active 1-inactive 2-active 2-enabled 2-succeeded 3-active 3-enabled 3-failed
4-active 4-inactive

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Here is an analysis of the evaluation of a temporal property:

 (1) A is true, so attempt 1 of the STATE property assertion becomes active.
 (2) B is false, so attempt 1 of the STATE property assertion becomes inactive.
 (3) A is true, so attempt 2 of the STATE property assertion becomes active.
 (4) B is true, so attempt 2 of the STATE property assertion becomes enabled.
 (5) C is true, so attempt 2 of the STATE property assertion succeeds and finishes.
 (6) A is true, so attempt 3 of the STATE property assertion becomes active.
 (7) B is true, so attempt 3 of the STATE property assertion becomes enabled. A is still true, so
attempt 4 of the STATE property assertion becomes active.
 (8) C is false, so attempt 3 of the STATE property assertion fails. B is false, so attempt 4 of the
STATE property assertion becomes inactive.

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Cycle Delay Repetition

Use ## with any constant integral property
property A3B;
A3B;
expression to define a number of @(negedge
@(negedge CLK)
CLK)
cycle delays !A
!A |=>
|=> ##3
##3 B;
B;
 N cycles later SEQ starts (and //
// !A
!A |->
|-> ##4
##4 B;
B;
completes when it should) endproperty
endproperty
##N SEQ
 SEQ1 completes and N cycles
later SEQ2 starts (and CLK
completes when it should) A
SEQ1 ##N SEQ2
B
 ##0 is allowed and useful !A next +three B
(sequence fusion)

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The cycle delay expression can be an integral constant expression or a range between two integral
constant expressions. Here we have a three cycle delay. The property holds in any given cycle if
either “A” is true in that cycle or if “A” is false and four cycles later “B” is true. Note that this
example uses next-cycle implication.
A delay of zero is valid and useful. A zero delay between the end of the left sequence and the start
of the right sequence means that the left sequence ends and the right sequence begins in the same
cycle. This is called sequence fusion.
--------
IEEE Std. 1800-2005 SystemVerilog LRM, Section 17.5

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Consecutive Sequence Repetition

You can specify multiple
consecutive repetitions of a property
property CONSEC;
CONSEC;
sequence @(negedge
@(negedge CLK)
CLK)
 SEQ repeats consecutively N !A[*4]
!A[*4] |=>
|=> A;
A;
times endproperty
endproperty
SEQ[*N]
CLK
 N can be 0 (empty sequence)
A
 A sequence that admits an
empty match cannot be used !A 2 3 4 A
directly as a property A is never low more than 4 cycles

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SystemVerilog provides three sequence repetition operators for your convenience. This slide
illustrates the consecutive repetition operator, which simply repeats its boolean for whatever many
cycles is the constant integral expression or range between two constant integral expressions. You
can use this consecutive repetition operator with a boolean expression, an instance of a declared
sequence, and with an inline sequence specification enclosed within parentheses.
--------
sequence_expr ::=
...
| expression_or_dist [ boolean_abbrev ]
| ( expression_or_dist {, sequence_match_item } ) [ boolean_abbrev ]
| sequence_instance [ sequence_abbrev ]
| ( sequence_expr {, sequence_match_item } ) [ sequence_abbrev ]
...

boolean_abbrev ::= consecutive_repetition | ...

sequence_abbrev ::= consecutive_repetition

IEEE Std. 1800-2005 SystemVerilog LRM, Section 17.7.2

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Consecutive Repetition with Ranges

You can specify a range for
consecutive repetition property
property RANGE;
RANGE;
SEQ[*min:max] @(negedge
@(negedge CLK)
CLK)
AA ##1
##1 !A
!A |->
|-> !A[*2:4]
!A[*2:4] ##1
##1 A;
 SEQ repeats A;
endproperty
consecutively between endproperty
min and max times
CLK
 min can be 0
 max can be $ A
(unlimited) !A 2 3 4 A
A goes low for 2 and 4 cycles only

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This example specifies a range for the consecutive repetitions. The property holds in any given
cycle if “A” is either false in that cycle, or true in the next cycle, or false for the next two to four
cycles and true in the cycle after that.
This slide provides an example of how difficult it is to craft a property that truly represents your
intentions. If the specification stated that “A” is low for between two and four cycles, then this
property would not reflect that specification, as the property as defined also holds for all cycles if
“A” is low at cycle zero and stays low. Note the difference between “is low” and “goes low”.

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Further SVA Features

This was only the briefest of introductions!
 There are more property operators, such as conditional properties
 There are more sequence operators, such as:
 Non-consecutive repetition
 Concurrent, alternate and overlapping sequences

 And other advanced SVA features

 Detecting the end of a sequence
 Parameterized sequences and properties
 Action blocks on property pass or failure
 Functional coverage

The “SystemVerilog Assertions” training covers these plus has coding

guidelines and recommendations, functional coverage, working examples
and SVA for Formal Verification.
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SystemVerilog has several more advanced property and sequence operators and features. The
“SystemVerilog Assertions” training covers these plus has coding guidelines and
recommendations, functional coverage and working examples

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Summary
 SystemVerilog assertions are based on Verilog boolean conditions

 Constructing a simple assertion is straight-forward:

 Write a boolean condition using Verilog syntax

 Define when the condition is checked with a clock expression

 Name the condition using the property statement

 Assert the property using an assert statement

 With sequences you can easily express complex, multi-cycle properties

 Boolean expressions separated by cycle delay ##N

 SVA has many features for defining multi-cycle and repeated sequences
 e.g. consecutive repetition [*N]

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Pause here for a moment and review what you have learned about SystemVerilog assertions.

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Quiz
Code this property and assert it:
If the req…ack handshake occurs …
 gnt is true on only the 2nd cycle after the req…ack handshake
 end is true on only the 6th cycle after gnt is true

clk
req
req
ack ack
gnt
gnt A data B
end
data
end

Solutions in Appendix A

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Conclusions and Next Steps

Chapter 14

November 6, 2009

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What This Verification Module Covered...

The SystemVerilog constructs that target design verification
 Data Types
 Classes and object-oriented design
 Dynamic and associative arrays and queues

 New constructs and interfaces

 Programs and final and clocking blocks
 Interfaces used as transactors and virtual interfaces
 Direct Programming Interface (DPI)

 Features enabling advanced verification techniques

 Constrained randomization of scope and class variables
 Functional coverage with covergroups and property covers
 Introduction to SystemVerilog Assertions
 Interprocess synchronization with events, mailboxes and semaphores

Following the course...

 Several months “hands-on” work to become experienced
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Congratulations upon finishing this SystemVerilog Verification training! We hope the information
in this training module met your verification and system-level design needs. You should expect to
become truly proficient with these constructs only after several months of practical application.

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What’s Next?
— SystemVerilog Language and Application —
Design Verification Module Assertion
Module Module
Day 1 Day 2 Day 3 Day 4 Day 5
Overview Overview Random Interprocess Introduction to Assertion Based
Stimulus Synchronization Verification (ABV)
Data Types Verification
Features Class-Based Direct Immediate Assertions
Procedures
Randomization Programming
Verification Simple Boolean Assertions
Operators Interface (DPI)
Blocks Coverage
Sequences
User-Defined Assertion-Based
Transaction- Arrays and
Data Types Verification Sequence Composition
Based Queues
Hierarchy & Verification SystemVerilog Advanced Features
Connectivity Assertions
Classes Coding Guidelines
Subroutines
Functional Coverage
Interfaces
Practical Application
Static Verification

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Successful completion of the Verification training qualifies you to now move on to the
SystemVerilog Assertions training. To complete this additional training will take approximately
another two days of your effort.

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Additional Resources
You can obtain additional information from the following sources:
 Standards
 IEEE Std. 1800-2005 http://www.ieee.org

 Advocacy groups
 Accellera http://www.accellera.org
 EDA.org http://www.eda.org

 News groups
 http://groups.google.com/group/comp.lang.verilog
 http://groups.google.com/group/SystemVerilog

 SystemVerilog Publications
 "SystemVerilog for Verification". Spear, C., Springer (http://www.springer.com), 2006.
 “SystemVerilog Assertions Handbook”, Cohen, B. (et al), VhdlCohen Publishing
(http://www.abv-sva.org), 2005.

 Cadence Documentation
 SystemVerilog Reference (http://sourcelink.cadence.com)

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Quiz Solutions

Appendix M2A

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3. Verification Blocks
1. What do the input, inout, and output clocking directions signify?
 The clocking directions specify whether the clocking applies to sampling the signal,
driving the signal, or both sampling and driving the signal.

2. How is a specific clocking block defined as the default?

 The default keyword, either added to the beginning of a clocking block declaration
or used in a separate default statement

3. Given the clocking blocks, what do these delays represent?

clocking
clocking cb1
cb1 @(negedge
@(negedge clk);
clk); @(cb1);
@(cb1); //
// @(negedge
@(negedge clk);
clk);
output
output posedge drive;
posedge drive; ##2;
##2; //
// repeat(2)
repeat(2) @(cb2);
@(cb2);
endclocking
endclocking cb1.drive
cb1.drive <=
<= ##3
##3 1;
1; //
// repeat(3)
repeat(3) @(cb1)
@(cb1)
clocking
clocking cb2
cb2 @(negedge
@(negedge clk);
clk); ##3;
##3; cb1.drive <= 2’b10; //
cb1.drive <= 2’b10; // repeat(3)
repeat(3) @(cb2);
@(cb2);
endclocking
endclocking ##(j-2)
##(j-2) cb1.drive
cb1.drive <=<= 1;
1; //
// repeat(j-2)
repeat(j-2) @(cb1)
@(cb1)
default
default clocking
clocking cb2;
cb2;
int j = 3;
int j = 3;

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4. Transaction-Level Modeling
1. What is a transaction?
 A transaction is a transfer of data between design blocks.
2. What components produce and consume transactions?
A] RTL Design. B] System-level Design. C] Testbench. D] B & C.
 Testbenches and system-level designs utilize transactions.
3. True of False: A transactor converts between a transaction interface and
a signal interface.
 True: A transactor converts between a transaction interface and a
signal interface.
4. What features of SystemVerilog interfaces most prominently support
transaction-based verification?
 SystemVerilog interface methods and clocking blocks prominently
support transaction-based verification.

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5. Classes
1. What is the role of a class constructor?
 The class constructor initializes the class properties.
2. What is the difference between a static and non-static property?
 One instance of a non-static property exists for each instance of the class type.
One instance of a static property exists and is not associated with any class instance.
3. What is the difference between a static and non-static method?
 A static method of a class can access only the static members of the class.
4. What is inheritance?
 A subclass inherits the members of its superclass and can redeclare them.
5. What is the difference between a protected and a local class member?
 A subclass method can access a protected member of its superclass.
Only class member methods can access local members of a class.
6. Give an example of polymorphism.
 An implementation of a virtual method is selected dynamically based upon the
subclass object that the superclass handle “points” to.

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6. Random Stimulus
Define the output for each value of i:

randsequence()
randsequence()
top
top :: AA B;
B;
AA :: CC DD E;
E;
BB :: CC EE {{ if
if (i
(i ==== 11 )) return;
return; }} D;
D;
CC :: {$display("C"); if(i == 3) return;};
{$display("C"); if(i == 3) return;};
DD :: {if
{if (i(i ==
== 22 )) return;
return; $display(
$display( "D");};
"D");};
EE :: {if
{if (i(i ==
== 00 )) break;
break; $display("E");};
$display("E");};
endsequence
endsequence

i == 0 produces C D
i == 1 produces C D E C E
i == 2 produces C E C E
i == 3 produces C D E C E D

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7. Class-Based Random Stimulus

The randomize call randomizes which variables?

class ClassA; ClassC objC = new;

randc bit bitA;
rand byte byteA; initial
endclass begin
objC.rand_mode(0);
class ClassB; objC.objB.intB.rand_mode(0);
randc byte byteB; objC.objB.rand_mode(1);
rand int intB; assert (objC.randomize());
ClassA objA = new; end
endclass
Answer: byteB
class ClassC; – rand_mode() applied to a non-rand object
rand int intC; applies to random properties of the object
real realC;
rand ClassB objB = new; – rand_mode() applied to a random property
endclass affects only that one property

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8. Coverage (question)

module
module example_with_bins;
example_with_bins;
logic
logic clk;
clk;
logic
logic [2:0]
[2:0] opcode;
opcode;
logic
logic [15:0]
[15:0] address;
address; How many bins in
? this covergroup?
covergroup
covergroup cg1
cg1 @(posedge
@(posedge clk);
Question What are their names?
clk);
c1:
c1: coverpoint
coverpoint opcode;
opcode;
c2:
c2: coverpoint
coverpoint address
address {{
bins
bins low[]
low[] == {{ [0:’h0F]
[0:’h0F] }} ;; opcode:
bins
bins high = { [’h10:’hFF] }} ;;
high = { [’h10:’hFF] 8 implicit
}} “c1.auto[0]” to “c1.auto[7]”
endgroup
endgroup :: cg1
cg1
address:
cg1
cg1 cover_inst
cover_inst == new();
new(); 16 explicit vectored
“c2.low[0]” to “c2.low[F]”
...
... 1 explicit scalar
“high”
endmodule
endmodule

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8. Coverage

bit
bit [7:0]
[7:0] avec,
avec, bvec;
bvec;
covergroup
covergroup cgcg @(posedge
@(posedge clk);
clk);
cpa:
cpa: coverpoint
coverpoint avec
avec {{
bins
bins a1
a1 == {{ [0:63]
[0:63] };
}; How many bins in this
bins
bins a2 = { [64:127] };
a2 = { [64:127] }; ? covergroup cross c?
bins
bins a3
a3 == {{ [128:191]
[128:191] };
Question What are their names?
};
bins
bins a4
a4 == {{ [192:255]
[192:255] };}; }}
cpb:
cpb: coverpoint
coverpoint bvec
bvec {{ c1: 4
bins b1 = {0};
bins b1 = {0}; <a1,b1>, <a1,b2>,
bins
bins b2
b2 == {{ [1:84]
[1:84] };
}; <a1,b3>, <a1,b4>
bins
bins b3
b3 == {{ [85:169]
[85:169] };}; c2: 7
bins
bins b4 = { [170:255] };
b4 = { [170:255] }; }} <a2,b1>, <a2,b2>,
cc :: cross
cross cpa,
cpa, cpb
cpb {{ <a2,b3>, <a2,b4>,
<a1,b2>, <a3,b2>,
bins
bins c1
c1 == !! binsof(cpa)
binsof(cpa) intersect
intersect {[100:200]};
{[100:200]}; <a4,b2>
bins
bins c2
c2 == binsof(cpa.a2)
binsof(cpa.a2) || || binsof(cpb.b2);
binsof(cpb.b2);
bins
bins c3
c3 == binsof(cpa.a1)
binsof(cpa.a1) && && binsof(cpb.b4);
binsof(cpb.b4); }} c3: 1
<a1, b4>
endgroup
endgroup

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9. Queues and Dynamic Arrays

Match the array that best meets each design need:

1. I want to concisely code an RTL instruction A. Packed array

processor to strip the opcode, address and
data fields off the instruction word…
2. I need to validate the architecture of my E. Queue
processor stack…
3. I need to validate the architecture of my C. Dynamic array
packet data temporary storage…
4. I need to validate the architecture of my D. Associative array
instruction cache…
5. I want to perform matrix operations on fixed- B. Unpacked array
size “chunks” of data of the real type…

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10. Interprocess Synchronization

1. Where would you use the non-blocking event trigger?
 Use a non-blocking event trigger anywhere that a process can potentially
“wait” for the event at the same simulation moment that another process
triggers the event – thus causing a “race” condition.
2. True or False: Merging events creates a synchronization queue that contains the
processes from both previous synchronization queues.
 False: Merging events merges the event variables – not their
synchronization queues. Both events now use the previous RHS queue.
3. What does a blocking get() or peek() do if the message at the head of the
mailbox queue is the wrong type?
 This is a runtime error. You should instead use the non-blocking versions.
4. What happens if a process puts more keys in a semaphore than the process got
from the semaphore?
 The semaphore capacity increases. SystemVerilog does not check!

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11. Direct Programming Interface

1. Write a function import statement to import the exp2f function (from the cmath
library) with the base2exp SystemVerilog identifier. Assume the C function has
no side effects. The C function prototype is:
float exp2f(float x);
 import "DPI-C" pure exp2f = function shortreal base2exp
( input shortreal x ) ;
2. True or False: The standard supports import and export of class methods.
 False: The standard does not support import or export of class methods.
3. How do you make an imported task (implemented in C) consume time?
 The imported task calls an exported task (implemented in SystemVerilog)
that consumes time.
4. How does an imported function that calls an exported function detect and
acknowledged that the call to the imported function is disabled?
 The imported function detects its disabled state by calling
svIsDisabledState() and acknowledges it by calling
svAckDisabledState()
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12. Assertion Based Verification

1. What is an assertion?
 An assertion is a check embedded in, or bound to, a design unit.
2. True or False: Formal (static) verification tools can also utilize
assertions.
 True: Formal (static) verification tools can utilize your assertions.
3. What obvious incentive does an IP designer have for embedding
assertions?
 To indicate when the IP is being used incorrectly.

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13. Introduction to SVA

Code this property and assert it:
If the req…ack handshake occurs …
 gnt is true on only the 2nd cycle after the req…ack handshake

 end is true on only the 6th cycle after gnt is true

A1 : assert property ( @(posedge clk)
(req ##1 ack) |=>
(!gnt ##1 gnt ##1 (!gnt && !end)[*5] ##1 (!gnt && end)) );

clk
req
req
ack ack
gnt
gnt A data B
end
data
end

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Index

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auto (automatic coverage bins), 150

Symbols
##N clocking block delay, 53
B
##N cycle delay repetition, 210 bins, 150-158
##N sequence concatenation, 254-258 automatic, 150
$error, 29 default, 154, 156
$exit, 44 scalar, 151-153
$fatal, 29 vector, 152-154
$get_coverage, 163 break
$info, 29 in randsequence, 117
$load_coverage_db, 163
$note, 29
$set_coverage_db_name, 163 C
$urandom_range, 106 case
$urandom, 106 in randsequence, 116
$warning, 29 class, 73-97
$ infinity literal, 16, 147, 152, 175-178, 258 abstract, 93
@ in clocking block, 47-54 aggregate, 86-87
:: scope resolution operator, 35, 80, 84 constructor, 76, 81-82, 96, 88-90
[] vector coverage bins, 152-154 data hiding, 91
[] dynamic array declaration, 169 dot operator, 78, 84
-> constraint implication, 14, 112, 135, 137 extends (inheritance), 87-93
-> blocking event trigger, 189-190 garbage collection, 76
->> non-blocking event trigger, 188-190 handle, 76-77
:= distribution weights, 111, 115, 134 vs. C pointer, 77
:/ distribution weights, 134 inheritance, 87-93
|-> assertion implication, 253 instance, 76
|=> assertion implication, 254 local property, 91
method, 78, 80-81, 84, 92-93
A external, 80
static, 84
action block, 28-29, 43 virtual, 92-93
aggregate class, 86-87 new (constructor), 76, 81-82, 86, 88-90
array, 167-185 null (handle value), 76
associative, 171-174 object, 76
methods, 171-174 parameter, 94
dynamic, 169-170 polymorphism, 92
methods, 169-170 property, 78, 83, 86, 91
item (manipulation), 179-182 local, 91
manipulation methods, 179-182 protected, 91
locator methods, 180 static, 83
ordering methods, 181 protected property, 91
reduction methods, 182 randomization, 123-143
queue, 175-178 resolution operator, 80, 84
methods, 175-178 super, 89-90
with (manipulation), 179-182 this, 85
assert, 15, 245, 247, 251 virtual, 92-93
assertion, 12, 15, 230-261 class, 93
action block, 28-29, 43 method, 92-93
benefits, 238 vs. struct, 80
concurrent, 244-245 clocking block, 47-54, 66
coverage, 15, 259 cycle delay, 53
evaluation, 249-250 default, 51
immediate, 27-31 hierarchical expression, 54
implication, 253-254 in interface, 66
issues, 239 skew, 47-50
label, 245,247 synchronous drive, 53
property, 245-249 concurrent assertion, 244-245
sequence, 251-257 consecutive repetition, 257-258
severity, 29 constraint, 14, 104, 111, 131-137
associative array, 171-174 class, 131-143

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conditional, 112, 135 sequencing, 191

dist, 134 scheduler, 42-43
inside, 133 synchronization queue, 192
with, 111 triggering, 188-190
constraint_mode(), 138-139 non-blocking, 188-189
context task and function, 217, 221-222, 224-225 persistent trigger, 190
cover directive, 16 triggered property, 190
coverage, 144-167 variables, 192-194
bins, 150-158 null value, 194
automatic, 150 wait_order (sequencing), 191
default, 153, 157 event scheduler, 42-43, 204
ignore_bins, 153, 158 export
illegal_bins, 153, 158 DPI , 219-225
scalar, 151-154 extends, 87-93
vector, 152-154 extern
coverpoint, 149-159 C linkage, 250-251
implicit, 158 class method, 80
cross, 155-158
option, 159, 161
system tasks, 163 F
type_option, 159-160 final block, 45
covergroup, 144-166 foreach
coverpoint, 149-159 in constraint, 136
implicit, 155 fork-join, 32
cross (coverage), 155-158 fs (time literal), 25
function
D context, 247-248, 252
export, 250-253
default import, 244-249, 253
clocking block, 51 pure, 249
coverage bins, 154, 156
clocking block skew, 47-50
Direct Programming Interface (see “DPI”) G
disable garbage collection, 76
fork-join, 34
DPI handshake, 223-225
dist constraint, 134 H
DPI, 206-229
compilation, 226 handle (class), 76-77
-sv_lib, 226
-sv_liblist, 226 I
-sv_root, 226
context if-else
import function, 216-217, 222, 224 in constraint, 112, 135
import task, 216-217, 225 in randsequence, 116
disable handshake, 223-225 ignore_bins, 153, 158
svAckDisabledState(), 223-225 illegal_bins, 153, 158
svIsDisabledState(), 223-225 import
export, 219-225 DPI, 213-218, 222-225
import, 213-218, 222-225 in interface, 65
linkage name inheritance, 87-93
export, 220 input
import, 215 in clocking block, 47-49
pure imported function, 211-218 inside operator
svdpi.h, 211-215, 219-220, 222, 224-225 in constraints, 111, 133
type mapping, 211-212, 214 interface, 63-68
dynamic array, 169-170 clocking block, 66
modport, 65
virtual, 67-68
E
event, 188-194
merging, 193

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polymorphism, 93
J post_randomize(), 126
join_any, 32 pre_randomize(), 126
join_none, 32 process
synchronization, 186-205
with event, 188-194
L with mailbox, 195-199
with semaphore, 200-202
linkage name (DPI), 215, 220
local class property, 91 programs, 44
$exit, 44
property
M assertion, 242-261
class, 78, 83, 91
mailbox , 195-199 local, 91
methods, 196 protected, 91
parameters, 199 static, 83
methods protected class property, 91
array manipulation, 179-182 ps (time literal), 25
array locator, 180 pseudo-random, 105
array ordering, 181 pure function (DPI), 216-218
array reduction, 183
associative array, 171-174
class, Q
external, 80
static, 84 queue, 175-178
virtual, 92-93
dynamic array, 169-170 R
mailbox, 196
in a modport, 65-66 rand, 124
queue array, 187-190 rand_mode, 129-130
semaphore, 201 randc, 124
ms (time literal), 25 randcase, 113
random number generator, 105, 108
randomize(), 107, 125
N randomization
new $urandom(), 106
class, 76, 81, 87 $urandom_range(), 106
covergroup, 147, 149 class object, 122-143
dynamic array, 169-170 rand, 124
mailbox, 227 randc, 124
semaphore, 201 rand_mode(), 129-130
ns (time literal), 25 constraint, 14, 104, 111-112, 131-140
null conditional, 112, 135
class variable, 76-77 constraint_mode(), 138-139
event variable, 194 dist (distributions), 111, 134
virtual interface, 67 inside operator, 111, 133
inheritance, 132
iterative, 136
O solve-before, 137
weights, 111, 134
Object-Oriented (OO) design, 75 randomize(), 107, 125
option, 164, 166 random number generator, 105, 108
output seed, 110, 140
in clocking block, 47-49 stability, 108
scope variable, 98-112
P srandom(), 109, 140
randsequence, 115-122
parameter productions, 114-118
class type, 79, 94 break, 117
mailbox, 199 case, 116
module, 35, 182 if-else, 116
property, 247 passing values, 118
PLI, 216 repeat, 116

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return, 117-118 method, 92-93

terminal, 114
weights, 115
repeat W
in randsequence, 116 wait
repetition fork-join, 33
assertion cycle, 256 wait_order (event sequencing), 191
consecutive, 257-258 with constraint, 111
resolution operator (class), 80, 84
return
in randsequence, 1187-118

S
s (time literal), 25
scheduler (event) 42-43
scope randomization (variable), 98-121
semaphore , 200-202
methods, 201
sequence
repetition, 255-256
severity level, 29
skew, 48-49
solve-before, 137
srandom(), 109, 140
static
class method, 84
class property, 83
std, 107
step (time literal), 25
struct
vs. class, 79
string, 21-24
svdpi.h, 211-215, 219-220, 222, 224-225
synchronous drive, 53

T
task
context, 247-248, 252
Transaction Level Modeling (TLM), 58-72
transaction, 60
transaction based verification (TBV), 61
transaction verification model (TVM), 61
transactor, 61
as interface, 63-68
benefits, 69
transactor, 62-66
using interface, 63-66
triggered (event property), 190
type_option, 159-160

U
us (time literal), 25

V
virtual
class, 93
interface, 67-68

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