1.

2 GHz Clock Distribution IC, PLL Core,

Dividers, Delay Adjust, Eight Outputs
Data Sheet AD9510
FEATURES FUNCTIONAL BLOCK DIAGRAM
VS GND RSET CPRSET VCP
Low phase noise phase-locked loop core
Reference input frequencies to 250 MHz DISTRIBUTION AD9510 PLL
REF
REF
Programmable dual modulus prescaler REFIN
R DIVIDER PHASE
Programmable charge pump (CP) current REFINB FREQUENCY CHARGE
PUMP CP
N DIVIDER DETECTOR
Separate CP supply (VCPS) extends tuning range SYNCB,
FUNCTION RESETB
Two 1.6 GHz, differential clock inputs PDB PLL
SETTINGS
STATUS

8 programmable dividers, 1 to 32, all integers CLK1 CLK2

Phase select for output-to-output coarse delay adjust CLK1B

PROGRAMMABLE
CLK2B
DIVIDERS AND
4 independent 1.2 GHz LVPECL outputs PHASE ADJUST LVPECL
OUT0
Additive output jitter of 225 fs rms /1, /2, /3... /31, /32
OUT0B
4 independent 800 MHz low voltage differential signaling LVPECL
OUT1
(LVDS) or 250 MHz complementary metal oxide conductor /1, /2, /3... /31, /32
OUT1B

(CMOS) clock outputs LVPECL

OUT2
/1, /2, /3... /31, /32
Additive output jitter of 275 fs rms OUT2B
SCLK LVPECL
Fine delay adjust on 2 LVDS/CMOS outputs SDIO SERIAL OUT3
CONTROL /1, /2, /3... /31, /32
Serial control port SDO PORT OUT3B
CSB LVDS/CMOS
Space-saving 64-lead LFCSP OUT4
/1, /2, /3... /31, /32
OUT4B
APPLICATIONS LVDS/CMOS
OUT5
/1, /2, /3... /31, /32 ∆T
Low jitter, low phase noise clock distribution OUT5B
LVDS/CMOS
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, and OUT6
/1, /2, /3... /31, /32 ∆T
mixed-signal front ends (MxFEs) OUT6B
LVDS/CMOS
High performance wireless transceivers OUT7
/1, /2, /3... /31, /32

05046-001
High performance instrumentation OUT7B

Broadband infrastructure
Figure 1.
GENERAL DESCRIPTION
The AD9510 provides a multi-output clock distribution function Each output has a programmable divider that can be bypassed
along with an on-chip phase-locked loop (PLL) core. The design or set to divide by any integer up to 32. The phase of one clock
emphasizes low jitter and phase noise to maximize data converter output relative to another clock output can be varied by means
performance. Other applications with demanding phase noise of a divider phase select function that serves as a coarse timing
and jitter requirements also benefit from this device. adjustment. Two of the LVDS/CMOS outputs feature program-
The PLL section consists of a programmable reference divider mable delay elements with full-scale ranges up to 8 ns of delay.
(R); a low noise, phase frequency detector (PFD); a precision This fine tuning delay block has 5-bit resolution, giving 25
charge pump (CP); and a programmable feedback divider (N). possible delays from which to choose for each full-scale setting
By connecting an external voltage-controlled crystal oscillator (Register 0x36 and Register 0x3A = 00000b to 11000b).
(VCXO) or voltage-controlled oscillator (VCO) to the CLK2 The AD9510 is ideally suited for data converter clocking
and CLK2B pins, frequencies of up to 1.6 GHz can be synchronized applications where maximum converter performance is
to the input reference. achieved by encode signals with subpicosecond jitter.
There are eight independent clock outputs. Four outputs are low The AD9510 is available in a 64-lead LFCSP and can be operated
voltage positive emitter-coupled logic (LVPECL) at 1.2 GHz, from a single 3.3 V supply. An external VCO, which requires an
and four are selectable as either LVDS (800 MHz) or CMOS extended voltage range, can be accommodated by connecting
(250 MHz) levels. the charge pump supply (VCP) to 5.5 V. The temperature range
is −40°C to +85°C.

Rev. C Document Feedback

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AD9510 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Overall ......................................................................................... 28
Applications ....................................................................................... 1 PLL Section ................................................................................. 28
Functional Block Diagram .............................................................. 1 FUNCTION Pin ......................................................................... 32
General Description ......................................................................... 1 Distribution Section ................................................................... 32
Revision History ............................................................................... 2 CLK1 and CLK2 Clock Inputs.................................................. 32
Specifications..................................................................................... 4 Dividers........................................................................................ 32
PLL Characteristics ...................................................................... 4 Delay Block ................................................................................. 37
Clock Inputs .................................................................................. 5 Outputs ........................................................................................ 37
Clock Outputs ............................................................................... 6 Power-Down Modes .................................................................. 38
Timing Characteristics ................................................................ 6 Reset Modes ................................................................................ 38
Clock Output Phase Noise .......................................................... 8 Single-Chip Synchronization .................................................... 39
Clock Output Additive Time Jitter ........................................... 11 Multichip Synchronization ....................................................... 39
PLL and Distribution Phase Noise and Spurious ................... 13 Serial Control Port ......................................................................... 40
Serial Control Port ..................................................................... 13 Serial Control Port Pin Descriptions ....................................... 40
FUNCTION Pin ......................................................................... 14 General Operation of Serial Control Port ............................... 40
STATUS Pin ................................................................................ 14 The Instruction Word (16 Bits) ................................................ 41
Power ............................................................................................ 15 MSB/LSB First Transfers ........................................................... 41
Timing Diagrams ............................................................................ 16 Register Map and Description ...................................................... 44
Absolute Maximum Ratings .......................................................... 17 Summary Table ........................................................................... 44
Thermal Characteristics ............................................................ 17 Register Map Description ......................................................... 46
ESD Caution ................................................................................ 17 Power Supply ................................................................................... 53
Pin Configuration and Function Descriptions ........................... 18 Power Management.................................................................... 53
Typical Performance Characteristics ........................................... 20 Applications Information .............................................................. 54
Terminology .................................................................................... 24 Using the AD9510 Outputs for ADC Clock Applications .... 54
Typical Modes of Operation.......................................................... 25 CMOS Clock Distribution ........................................................ 54
PLL with External VCXO/VCO Followed by Clock LVPECL Clock Distribution ..................................................... 55
Distribution ................................................................................. 25 LVDS Clock Distribution .......................................................... 55
Clock Distribution Only ............................................................ 25 Power and Grounding Considerations and Power Supply
PLL with External VCO and Band-Pass Filter Followed by Rejection ...................................................................................... 55
Clock Distribution...................................................................... 26 Outline Dimensions ....................................................................... 56
Functional Description .................................................................. 28 Ordering Guide .......................................................................... 56

REVISION HISTORY
9/2016—Rev. B to Rev. C Added EPAD Row, Table 14 .......................................................... 19
Changes to STATUS Pin Section .................................................. 30 Changes to Figure 21...................................................................... 22
Changes to Ordering Guide .......................................................... 56 Changes to Delay Block Section, Figure 40, and Calculating the
Delay Section................................................................................... 37
9/2013—Rev. A to Rev. B Changes to Address 0x36[5:1] and Address 0x3A[5:1],
Changes to General Description Section ...................................... 1 Table 24 ............................................................................................ 44
Changes to Table 4 ............................................................................ 6 Changes to Address 0x36 and Address 0x3A, Table 25 ............. 49
Changes to Table 6 .......................................................................... 11 Updated Outline Dimensions ....................................................... 56
Added Table 13; Renumbered Sequentially ................................ 17 Changes to Ordering Guide .......................................................... 56
Changes to Figure 6 ........................................................................ 18
Rev. C | Page 2 of 56
Data Sheet AD9510
5/2005—Rev. 0 to Rev. A Changes to Calculating the Delay Section ................................... 38
Changes to Features .......................................................................... 1 Changes to Soft Reset via the Serial Port Section ....................... 41
Changes to Table 1 and Table 2 ....................................................... 5 Changes to Multichip Synchronization Section.......................... 41
Changes to Table 4 ............................................................................ 8 Changes to Serial Control Port Section ....................................... 42
Changes to Table 5 ............................................................................ 9 Changes to Serial Control Port Pin Descriptions Section ......... 42
Changes to Table 6 ..........................................................................14 Changes to General Operation of Serial
Changes to Table 8 and Table 9 .....................................................15 Control Port Section ....................................................................... 42
Changes to Table 11 ........................................................................16 Added Framing a Communication Cycle with CSB Section .... 42
Changes to Table 13 ........................................................................20 Added Communication Cycle—Instruction Plus
Changes to Figure 7 and Figure 10 ...............................................22 Data Section ..................................................................................... 42
Changes to Figure 19 to Figure 23 ................................................24 Changes to Write Section ............................................................... 42
Changes to Figure 30 and Figure 31 .............................................26 Changes to Read Section ................................................................ 42
Changes to Figure 32 ......................................................................27 Changes to The Instruction Word (16 Bits) Section .................. 43
Changes to Figure 33 ......................................................................28 Changes to Table 20 ........................................................................ 43
Changes to VCO/VCXO Clock Input—CLK2 Section ..............29 Changes to MSB/LSB First Transfers Section.............................. 43
Changes to A and B Counters Section .........................................30 Changes to Table 21 ........................................................................ 44
Changes to PLL Digital Lock Detect Section ..............................31 Added Figure 52; Renumbered Sequentially ............................... 45
Changes to PLL Analog Lock Detect Section ..............................32 Changes to Table 23 ........................................................................ 46
Changes to Loss of Reference Section ..........................................32 Changes to Table 24 ........................................................................ 49
Changes to FUNCTION Pin Section ...........................................33 Changes to Using the AD9510 Outputs for ADC Clock
Changes to RESETB: 58h<6:5> = 00b (Default) Section ...........33 Applications ..................................................................................... 57
Changes to SYNCB: 58h<6:5> = 01b Section ..............................33
Changes to CLK1 and CLK2 Clock Inputs Section ....................33 4/2005—Revision 0: Initial Version

Rev. C | Page 3 of 56
AD9510 Data Sheet

SPECIFICATIONS
Typical (typ) is given for VS = 3.3 V ± 5%, VS ≤ VCPS ≤ 5.5 V, TA = 25°C, RSET = 4.12 kΩ, CPRSET = 5.1 kΩ, unless otherwise noted.
Minimum (min) and maximum (max) values are given over full VS and TA (−40°C to +85°C) variation.
PLL CHARACTERISTICS
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
REFERENCE INPUTS (REFIN)
Input Frequency 0 250 MHz
Input Sensitivity 150 mV p-p
Self-Bias Voltage, REFIN 1.45 1.60 1.75 V Self-bias voltage of REFIN 1
Self-Bias Voltage, REFINB 1.40 1.50 1.60 V Self-bias voltage of REFINB1
Input Resistance, REFIN 4.0 4.9 5.8 kΩ Self-biased1
Input Resistance, REFINB 4.5 5.4 6.3 kΩ Self-biased1
Input Capacitance 2 pF
PHASE FREQUENCY DETECTOR (PFD)
PFD Input Frequency 100 MHz Antibacklash pulse width, Register 0x0D[1:0] = 00b
PFD Input Frequency 100 MHz Antibacklash pulse width, Register 0x0D[1:0] = 01b
PFD Input Frequency 45 MHz Antibacklash pulse width, Register 0x0D[1:0] = 10b
Antibacklash Pulse Width 1.3 ns Register 0x0D[1:0] = 00b (this is the default setting)
Antibacklash Pulse Width 2.9 ns Register 0x0D[1:0] = 01b
Antibacklash Pulse Width 6.0 ns Register 0x0D[1:0] = 10b
CHARGE PUMP (CP)
ICP Sink/Source Programmable
High Value 4.8 mA With CPRSET = 5.1 kΩ
Low Value 0.60 mA
Absolute Accuracy 2.5 % VCP = VCPS/2
CPRSET Range 2.7/10 kΩ
ICP Three-State Leakage 1 nA
Sink-and-Source Current Matching 2 % 0.5 < VCP < VCPS − 0.5 V
ICP vs. VCP 1.5 % 0.5 < VCP < VCPS − 0.5 V
ICP vs. Temperature 2 % VCP = VCPS/2 V
RF CHARACTERISTICS (CLK2) 2
Input Frequency 1.6 GHz Frequencies > 1200 MHz (LVPECL) or 800 MHz (LVDS)
require a minimum divide-by-2 (see the Distribution
Section)
Input Sensitivity 150 mV p-p
Input Common-Mode Voltage, VCM 1.5 1.6 1.7 V Self-biased, enables ac coupling
Input Common-Mode Range, VCMR 1.3 1.8 V With 200 mV p-p signal applied
Input Sensitivity, Single-Ended 150 mV p-p CLK2 ac-coupled, CLK2B capacitively bypassed to RF
ground
Input Resistance 4.0 4.8 5.6 kΩ Self-biased
Input Capacitance 2 pF
CLK2 VS. REFIN DELAY 500 ps Difference at PFD
PRESCALER (PART OF N DIVIDER) See the VCO/VCXO Feedback Divider—N (P, A, B) section
Prescaler Input Frequency
P = 2 DM (2/3) 600 MHz
P = 4 DM (4/5) 1000 MHz
P = 8 DM (8/9) 1600 MHz
P = 16 DM (16/17) 1600 MHz
P = 32 DM (32/33) 1600 MHz
CLK2 Input Frequency for PLL 300 MHz A, B counter input frequency

Rev. C | Page 4 of 56
Data Sheet AD9510
Parameter Min Typ Max Unit Test Conditions/Comments
NOISE CHARACTERISTICS
In-Band Noise of the Charge Pump/ Synthesizer phase noise floor estimated by measuring
Phase Frequency Detector (In-Band the in-band phase noise at the output of the VCO and
Means Within the LBW of the PLL) subtracting 20logN (where N is the N divider value)
At 50 kHz PFD Frequency −172 dBc/Hz
At 2 MHz PFD Frequency −156 dBc/Hz
At 10 MHz PFD Frequency −149 dBc/Hz
At 50 MHz PFD Frequency −142 dBc/Hz
PLL Figure of Merit −218 + dBc/Hz Approximation of the PFD/CP phase noise floor (in the
10 × log flat region) inside the PLL loop bandwidth; when
(fPFD) running closed loop this phase noise is gained up
by 20 × log(N) 3
PLL DIGITAL LOCK DETECT WINDOW 4 Signal available at STATUS pin when selected by
Register 0x08[5:2]
Required to Lock (Coincidence of Edges) Selected by Register 0x0D
Low Range (ABP 1.3 ns, 2.9 ns) 3.5 ns Bit[5] = 1b.
High Range (ABP 1.3 ns, 2.9 ns) 7.5 ns Bit[5] = 0b.
High Range (ABP 6 ns) 3.5 ns Bit[5] = 0b.
To Unlock After Lock (Hysteresis)4 Selected by Register 0x0D
Low Range (ABP 1.3 ns, 2.9 ns) 7 ns Bit[5] = 1b.
High Range (ABP 1.3 ns, 2.9 ns) 15 ns Bit[5] = 0b.
High Range (ABP 6 ns) 11 ns Bit[5] = 0b.
1
REFIN and REFINB self-bias points are offset slightly to avoid chatter on an open input condition.
2
CLK2 is electrically identical to CLK1; the distribution-only input can be used as differential or single-ended input (see the Clock Inputs section).
3
Example: −218 + 10 × log(fPFD) + 20 × log(N) gives the values for the in-band noise at the VCO output.
4
For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.

CLOCK INPUTS
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
CLOCK INPUTS (CLK1, CLK2) 1
Input Frequency 0 1.6 GHz
Input Sensitivity 150 2 mV p-p Jitter performance can be improved with higher slew
rates (greater swing)
Input Level 23 V p-p Larger swings turn on the protection diodes and can
degrade jitter performance
Input Common-Mode Voltage VCM 1.5 1.6 1.7 V Self-biased; enables ac coupling
Input Common-Mode Range VCMR 1.3 1.8 V With 200 mV p-p signal applied; dc-coupled
Input Sensitivity, Single-Ended 150 mV p-p CLK2 ac-coupled, CLK2B ac-bypassed to RF ground
Input Resistance 4.0 4.8 5.6 kΩ Self-biased
Input Capacitance 2 pF
1
CLK1 and CLK2 are electrically identical; each can be used as either a differential or a single-ended input.
2
With a 50 Ω termination, this is −12.5 dBm.
3
With a 50 Ω termination, this is +10 dBm.

Rev. C | Page 5 of 56
AD9510 Data Sheet
CLOCK OUTPUTS
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
LVPECL CLOCK OUTPUTS Termination = 50 Ω to VS − 2 V
OUT0, OUT1, OUT2, OUT3; Output level Register 0x3C, Register 0x3D,
Differential Register 0x3E, Register 0x3F[3:2] = 10b
Output Frequency 1200 MHz See Figure 21
Output High Voltage VOH VS − 1.22 VS − 0.98 VS − 0.93 V
Output Low Voltage VOL VS − 2.10 VS − 1.80 VS − 1.67 V
Output Differential Voltage VOD 660 810 965 mV
LVDS CLOCK OUTPUTS Termination = 100 Ω differential; default
OUT4, OUT5, OUT6, OUT7; Output level Register 0x40, Register 0x41,
Differential Register 0x42, Register 0x43[2:1] = 01b
3.5 mA termination current
Output Frequency 800 MHz See Figure 22
Differential Output Voltage VOD 250 360 450 mV
Delta VOD 25 mV
Output Offset Voltage VOS 1.125 1.23 1.375 V
Delta VOS 25 mV
Short-Circuit Current ISA, ISB 14 24 mA Output shorted to GND
CMOS CLOCK OUTPUTS
OUT4, OUT5, OUT6, OUT7 Single-ended measurements, B outputs:
inverted, termination open
Output Frequency 250 MHz With 5 pF load each output, see Figure 23
Output Voltage High VOH VS − 0.1 V At 1 mA load
Output Voltage Low VOL 0.1 V At 1 mA load

TIMING CHARACTERISTICS
Table 4.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
LVPECL Termination = 50 Ω to VS − 2 V; output level
Register 0x3C, Register 0x3D, Register 0x3E,
Register 0x3F[3:2] = 10b
Output Rise Time tRP 130 180 ps 20% to 80%, measured differentially
Output Fall Time tFP 130 180 ps 80% to 20%, measured differentially
PROPAGATION DELAY, CLK-TO-LVPECL OUT 1 tPECL
Divide = Bypass 335 490 635 ps
Divide = 2 − 32 375 545 695 ps
Variation with Temperature 0.5 ps/°C
OUTPUT SKEW, LVPECL OUTPUTS
OUT1 to OUT0 on Same Part 2 tSKP −5 +30 +85 ps
OUT2 to OUT3 on Same Part2 tSKP 15 45 80 ps
All LVPECL OUTs on Same Part2 tSKP 90 130 180 ps
All LVPECL OUTs Across Multiple Parts 3 tSKP_AB 275 ps
Same LVPECL OUT Across Multiple tSKP_AB 130 ps
Parts3
LVDS Termination = 100 Ω differential; output level
Register 0x40, Register 0x41, Register 0x42,
Register 0x43[2:1] = 01b; 3.5 mA termination
current
Output Rise Time tRL 200 350 ps 20% to 80%, measured differentially
Output Fall Time tFL 210 350 ps 80% to 20%, measured differentially

Rev. C | Page 6 of 56
Data Sheet AD9510
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
PROPAGATION DELAY, CLK-TO-LVDS OUT1 tLVDS Delay off on OUT5 and OUT6
OUT4, OUT5, OUT6, OUT7
Divide = Bypass 0.99 1.33 1.59 ns
Divide = 2 − 32 1.04 1.38 1.64 ns
Variation with Temperature 0.9 ps/°C
OUTPUT SKEW, LVDS OUTPUTS Delay off on OUT5 and OUT6
OUT4 to OUT7 on Same Part2 tSKV −85 +270 ps
OUT5 to OUT6 on Same Part2 tSKV −175 +155 ps
All LVDS OUTs on Same Part2 tSKV −175 +270 ps
All LVDS OUTs Across Multiple Parts3 tSKV_AB 450 ps
Same LVDS OUT Across Multiple Parts3 tSKV_AB 325 ps
CMOS B outputs are inverted, termination = open
Output Rise Time tRC 681 865 ps 20% to 80%; CLOAD = 3 pF
Output Fall Time tFC 646 992 ps 80% to 20%; CLOAD = 3 pF
PROPAGATION DELAY, CLK-TO-CMOS OUT1 tCMOS Delay off on OUT5 and OUT6
Divide = Bypass 1.02 1.39 1.71 ns
Divide = 2 − 32 1.07 1.44 1.76 ns
Variation with Temperature 1 ps/°C
OUTPUT SKEW, CMOS OUTPUTS Delay off on OUT5 and OUT6
All CMOS OUTs on Same Part2 tSKC −140 +145 +300 ps
All CMOS OUTs Across Multiple Parts3 tSKC_AB 650 ps
Same CMOS OUT Across Multiple Parts3 tSKC_AB 500 ps
LVPECL-TO-LVDS OUT Everything the same; different logic type
Output Skew tSKP_V 0.74 0.92 1.14 ns LVPECL to LVDS on same part
LVPECL-TO-CMOS OUT Everything the same; different logic type
Output Skew tSKP_C 0.88 1.14 1.43 ns LVPECL to CMOS on same part
LVDS-TO-CMOS OUT Everything the same; different logic type
Output Skew tSKV_C 158 353 506 ps LVDS to CMOS on same part
DELAY ADJUST 4 OUT5 (OUT6); LVDS and CMOS
Shortest Delay Range 5 Register 0x35, Register 0x39[5:1] = 11111b
Zero Scale 0.05 0.36 0.68 ns Register 0x36, Register 0x3A[5:1] = 00000b
Full Scale 0.57 0.95 1.32 ns Register 0x36, Register 0x3A[5:1] = 11000b
Linearity, DNL 0.5 LSB
Linearity, INL 0.8 LSB
Longest Delay Range5 Register 0x35, Register 0x39[5:1] = 00000b
Zero Scale 0.20 0.57 0.95 ns Register 0x36, Register 0x3A[5:1] = 00000b
Full Scale 7.0 8.0 9.2 ns Register 0x36, Register 0x3A[5:1] = 11000b
Linearity, DNL 0.3 LSB
Linearity, INL 0.6 LSB
Delay Variation with Temperature
Long Delay Range, 8 ns 6
Zero Scale 0.35 ps/°C
Full Scale −0.14 ps/°C
Short Delay Range, 1 ns6
Zero Scale 0.51 ps/°C
Full Scale 0.67 ps/°C
1
These measurements are for CLK1. For CLK2, add approximately 25 ps.
2
This is the difference between any two similar delay paths within a single device operating at the same voltage and temperature.
3
This is the difference between any two similar delay paths across multiple devices operating at the same voltage and temperature.
4
The maximum delay that can be used is a little less than one half the period of the clock. A longer delay disables the output.
5
Incremental delay; does not include propagation delay.
6
All delays between zero scale and full scale can be estimated by linear interpolation.

Rev. C | Page 7 of 56
AD9510 Data Sheet
CLOCK OUTPUT PHASE NOISE
Table 5.
Parameter Min Typ Max Unit Test Conditions/Comments
CLK1-TO-LVPECL ADDITIVE PHASE NOISE Distribution Section only, does not include
PLL or external VCO/VCXO
CLK1 = 622.08 MHz, OUT = 622.08 MHz Input slew rate > 1 V/ns
Divide Ratio = 1
At 10 Hz Offset −125 dBc/Hz
At 100 Hz Offset −132 dBc/Hz
At 1 kHz Offset −140 dBc/Hz
At 10 kHz Offset −148 dBc/Hz
At 100 kHz Offset −153 dBc/Hz
>1 MHz Offset −154 dBc/Hz
CLK1 = 622.08 MHz, OUT = 155.52 MHz
Divide Ratio = 4
At 10 Hz Offset −128 dBc/Hz
At 100 Hz Offset −140 dBc/Hz
At 1 kHz Offset −148 dBc/Hz
At 10 kHz Offset −155 dBc/Hz
At 100 kHz Offset −161 dBc/Hz
>1 MHz Offset −161 dBc/Hz
CLK1 = 622.08 MHz, OUT = 38.88 MHz
Divide Ratio = 16
At 10 Hz Offset −135 dBc/Hz
At 100 Hz Offset −145 dBc/Hz
At 1 kHz Offset −158 dBc/Hz
At 10 kHz Offset −165 dBc/Hz
At 100 kHz Offset −165 dBc/Hz
>1 MHz Offset −166 dBc/Hz
CLK1 = 491.52 MHz, OUT = 61.44 MHz
Divide Ratio = 8
At 10 Hz Offset −131 dBc/Hz
At 100 Hz Offset −142 dBc/Hz
At 1 kHz Offset −153 dBc/Hz
At 10 kHz Offset −160 dBc/Hz
At 100 kHz Offset −165 dBc/Hz
> 1 MHz Offset −165 dBc/Hz
CLK1 = 491.52 MHz, OUT = 245.76 MHz
Divide Ratio = 2
At 10 Hz Offset −125 dBc/Hz
At 100 Hz Offset −132 dBc/Hz
At 1 kHz Offset −140 dBc/Hz
At 10 kHz Offset −151 dBc/Hz
At 100 kHz Offset −157 dBc/Hz
>1 MHz Offset −158 dBc/Hz
CLK1 = 245.76 MHz, OUT = 61.44 MHz
Divide Ratio = 4
At 10 Hz Offset −138 dBc/Hz
At 100 Hz Offset −144 dBc/Hz
At 1 kHz Offset −154 dBc/Hz
At 10 kHz Offset −163 dBc/Hz
At 100 kHz Offset −164 dBc/Hz
>1 MHz Offset −165 dBc/Hz

Rev. C | Page 8 of 56
Data Sheet AD9510
Parameter Min Typ Max Unit Test Conditions/Comments
CLK1-TO-LVDS ADDITIVE PHASE NOISE Distribution Section only; does not include
PLL or external VCO/VCXO
CLK1 = 622.08 MHz, OUT= 622.08 MHz
Divide Ratio = 1
At 10 Hz Offset −100 dBc/Hz
At 100 Hz Offset −110 dBc/Hz
At 1 kHz Offset −118 dBc/Hz
At 10 kHz Offset −129 dBc/Hz
At 100 kHz Offset −135 dBc/Hz
At 1 MHz Offset −140 dBc/Hz
>10 MHz Offset −148 dBc/Hz
CLK1 = 622.08 MHz, OUT = 155.52 MHz
Divide Ratio = 4
At 10 Hz Offset −112 dBc/Hz
At 100 Hz Offset −122 dBc/Hz
At 1 kHz Offset −132 dBc/Hz
At 10 kHz Offset −142 dBc/Hz
At 100 kHz Offset −148 dBc/Hz
At 1 MHz Offset −152 dBc/Hz
>10 MHz Offset −155 dBc/Hz
CLK1 = 491.52 MHz, OUT = 245.76 MHz
Divide Ratio = 2
At 10 Hz Offset −108 dBc/Hz
At 100 Hz Offset −118 dBc/Hz
At 1 kHz Offset −128 dBc/Hz
At 10 kHz Offset −138 dBc/Hz
At 100 kHz Offset −145 dBc/Hz
At 1 MHz Offset −148 dBc/Hz
>10 MHz Offset −154 dBc/Hz
CLK1 = 491.52 MHz, OUT = 122.88 MHz
Divide Ratio = 4
At 10 Hz Offset −118 dBc/Hz
At 100 Hz Offset −129 dBc/Hz
At 1 kHz Offset −136 dBc/Hz
At 10 kHz Offset −147 dBc/Hz
At 100 kHz Offset −153 dBc/Hz
At 1 MHz Offset −156 dBc/Hz
>10 MHz Offset −158 dBc/Hz
CLK1 = 245.76 MHz, OUT = 245.76 MHz
Divide Ratio = 1
At 10 Hz Offset −108 dBc/Hz
At 100 Hz Offset −118 dBc/Hz
At 1 kHz Offset −128 dBc/Hz
At 10 kHz Offset −138 dBc/Hz
At 100 kHz Offset −145 dBc/Hz
At 1 MHz Offset −148 dBc/Hz
>10 MHz Offset −155 dBc/Hz

Rev. C | Page 9 of 56
AD9510 Data Sheet
Parameter Min Typ Max Unit Test Conditions/Comments
CLK1 = 245.76 MHz, OUT = 122.88 MHz
Divide Ratio = 2
At 10 Hz Offset −118 dBc/Hz
At 100 Hz Offset −127 dBc/Hz
At 1 kHz Offset −137 dBc/Hz
At 10 kHz Offset −147 dBc/Hz
At 100 kHz Offset −154 dBc/Hz
At 1 MHz Offset −156 dBc/Hz
>10 MHz Offset −158 dBc/Hz
CLK1-TO-CMOS ADDITIVE PHASE NOISE Distribution Section only, does not include
PLL or external VCO/VCXO
CLK1 = 245.76 MHz, OUT = 245.76 MHz
Divide Ratio = 1
At 10 Hz Offset −110 dBc/Hz
At 100 Hz Offset −121 dBc/Hz
At 1 kHz Offset −130 dBc/Hz
At 10 kHz Offset −140 dBc/Hz
At 100 kHz Offset −145 dBc/Hz
At 1 MHz Offset −149 dBc/Hz
>10 MHz Offset −156 dBc/Hz
CLK1 = 245.76 MHz, OUT = 61.44 MHz
Divide Ratio = 4
At 10 Hz Offset −122 dBc/Hz
At 100 Hz Offset −132 dBc/Hz
At 1 kHz Offset −143 dBc/Hz
At 10 kHz Offset −152 dBc/Hz
At 100 kHz Offset −158 dBc/Hz
At 1 MHz Offset −160 dBc/Hz
>10 MHz Offset −162 dBc/Hz
CLK1 = 78.6432 MHz, OUT = 78.6432 MHz
Divide Ratio = 1
At 10 Hz Offset −122 dBc/Hz
At 100 Hz Offset −132 dBc/Hz
At 1 kHz Offset −140 dBc/Hz
At 10 kHz Offset −150 dBc/Hz
At 100 kHz Offset −155 dBc/Hz
At 1 MHz Offset −158 dBc/Hz
>10 MHz Offset −160 dBc/Hz
CLK1 = 78.6432 MHz, OUT = 39.3216 MHz
Divide Ratio = 2
At 10 Hz Offset −128 dBc/Hz
At 100 Hz Offset −136 dBc/Hz
At 1 kHz Offset −146 dBc/Hz
At 10 kHz Offset −155 dBc/Hz
At 100 kHz Offset −161 dBc/Hz
>1 MHz Offset −162 dBc/Hz

Rev. C | Page 10 of 56
Data Sheet AD9510
CLOCK OUTPUT ADDITIVE TIME JITTER
Table 6.
Parameter Min Typ Max Unit Test Conditions/Comments
LVPECL OUTPUT ADDITIVE TIME JITTER Distribution Section only, does not include
PLL or external VCO/VCXO
CLK1 = 622.08 MHz 40 fs rms Bandwidth = 12 kHz − 20 MHz (OC-12)
Any LVPECL (OUT0 to OUT3) = 622.08 MHz
Divide Ratio = 1
CLK1 = 622.08 MHz 55 fs rms Bandwidth = 12 kHz − 20 MHz (OC-3)
Any LVPECL (OUT0 to OUT3) = 155.52 MHz
Divide Ratio = 4
CLK1 = 400 MHz 215 fs rms Calculated from signal-to-noise ratio (SNR) of
ADC method, fC = 100 MHz with AIN = 170 MHz
Any LVPECL (OUT0 to OUT3) = 100 MHz
Divide Ratio = 4
CLK1 = 400 MHz 215 fs rms Calculated from SNR of ADC method,
fC = 100 MHz with AIN = 170 MHz
Any LVPECL (OUT0 to OUT3) = 100 MHz
Divide Ratio = 4
All Other LVPECL = 100 MHz Interferer(s)
All LVDS (OUT4 to OUT7) = 100 MHz Interferer(s)
CLK1 = 400 MHz 222 fs rms Calculated from SNR of ADC method,
fC = 100 MHz with AIN = 170 MHz
Any LVPECL (OUT0 to OUT3) = 100 MHz
Divide Ratio = 4
All Other LVPECL = 50 MHz Interferer(s)
All LVDS (OUT4 to OUT7) = 50 MHz Interferer(s)
CLK1 = 400 MHz 225 fs rms Calculated from SNR of ADC method;
fC = 100 MHz with AIN = 170 MHz
Any LVPECL (OUT0 to OUT3) = 100 MHz
Divide Ratio = 4
All Other LVPECL = 50 MHz Interferer(s)
All CMOS (OUT4 to OUT7) = 50 MHz (B Outputs Off ) Interferer(s)
CLK1 = 400 MHz 225 fs rms Calculated from SNR of ADC method,
fC = 100 MHz with AIN = 170 MHz
Any LVPECL (OUT0 to OUT3) = 100 MHz
Divide Ratio = 4
All Other LVPECL = 50 MHz Interferer(s)
All CMOS (OUT4 to OUT7) = 50 MHz (B Outputs On) Interferer(s)
LVDS OUTPUT ADDITIVE TIME JITTER Distribution Section only, does not include
PLL or external VCO/VCXO
CLK1 = 400 MHz 264 fs rms Calculated from SNR of ADC method,
fC = 100 MHz with AIN = 170 MHz
LVDS (OUT4, OUT7) = 100 MHz
Divide Ratio = 4
CLK1 = 400 MHz 319 fs rms Calculated from SNR of ADC method,
fC = 100 MHz with AIN = 170 MHz
LVDS (OUT5, OUT6) = 100 MHz
Divide Ratio = 4

Rev. C | Page 11 of 56
AD9510 Data Sheet
Parameter Min Typ Max Unit Test Conditions/Comments
CLK1 = 400 MHz 395 fs rms Calculated from SNR of ADC method,
fC = 100 MHz with AIN = 170 MHz
LVDS (OUT4, OUT7) = 100 MHz
Divide Ratio = 4
All Other LVDS = 50 MHz Interferer(s)
All LVPECL = 50 MHz Interferer(s)
CLK1 = 400 MHz 395 fs rms Calculated from SNR of ADC method,
fC = 100 MHz with AIN = 170 MHz
LVDS (OUT5, OUT6) = 100 MHz
Divide Ratio = 4
All Other LVDS = 50 MHz Interferer(s)
All LVPECL = 50 MHz Interferer(s)
CLK1 = 400 MHz 367 fs rms Calculated from SNR of ADC method,
fC = 100 MHz with AIN = 170 MHz
LVDS (OUT4, OUT7) = 100 MHz
Divide Ratio = 4
All Other CMOS = 50 MHz (B Outputs Off ) Interferer(s)
All LVPECL = 50 MHz Interferer(s)
CLK1 = 400 MHz 367 fs rms Calculated from SNR of ADC method,
fC = 100 MHz with AIN = 170 MHz
LVDS (OUT5, OUT6) = 100 MHz
Divide Ratio = 4
All Other CMOS = 50 MHz (B Outputs Off ) Interferer(s)
All LVPECL = 50 MHz Interferer(s)
CLK1 = 400 MHz 548 fs rms Calculated from SNR of ADC method,
fC = 100 MHz with AIN = 170 MHz
LVDS (OUT4, OUT7) = 100 MHz
Divide Ratio = 4
All Other CMOS = 50 MHz (B Outputs On) Interferer(s)
All LVPECL = 50 MHz Interferer(s)
CLK1 = 400 MHz 548 fs rms Calculated from SNR of ADC method,
fC = 100 MHz with AIN = 170 MHz
LVDS (OUT5, OUT6) = 100 MHz
Divide Ratio = 4
All Other CMOS = 50 MHz (B Outputs On) Interferer(s)
All LVPECL = 50 MHz Interferer(s)
CMOS OUTPUT ADDITIVE TIME JITTER Distribution Section only, does not include
PLL or external VCO/VCXO
CLK1 = 400 MHz 275 fs rms Calculated from SNR of ADC method,
fC = 100 MHz with AIN = 170 MHz
Any CMOS (OUT4 to OUT7) = 100 MHz (B Output On)
Divide Ratio = 4
CLK1 = 400 MHz 400 fs rms Calculated from SNR of ADC method,
fC = 100 MHz with AIN = 170 MHz
Any CMOS (OUT4 to OUT7) = 100 MHz (B Output On)
Divide Ratio = 4
All LVPECL = 50 MHz Interferer(s)
All Other LVDS = 50 MHz Interferer(s)
CLK1 = 400 MHz 374 fs rms Calculated from SNR of ADC method,
fC = 100 MHz with AIN = 170 MHz
Any CMOS (OUT4 to OUT7) = 100 MHz (B Output On)
Divide Ratio = 4
All LVPECL = 50 MHz Interferer(s)
All Other CMOS = 50 MHz (B Output Off ) Interferer(s)

Rev. C | Page 12 of 56
Data Sheet AD9510
Parameter Min Typ Max Unit Test Conditions/Comments
CLK1 = 400 MHz 555 fs rms Calculated from SNR of ADC method,
fC = 100 MHz with AIN = 170 MHz
Any CMOS (OUT4 to OUT7) = 100 MHz (B Output On)
Divide Ratio = 4
All LVPECL = 50 MHz Interferer(s)
All Other CMOS = 50 MHz (B Output On) Interferer(s)
DELAY BLOCK ADDITIVE TIME JITTER 1 Incremental additive jitter1
100 MHz Output
Delay FS = 1 ns (1600 μA, 1C) Fine Adjust 00000 0.61 ps
Delay FS = 1 ns (1600 μA, 1C) Fine Adjust 11000 0.73 ps
Delay FS = 2 ns (800 μA, 1C) Fine Adjust 00000 0.71 ps
Delay FS = 2 ns (800 μA, 1C) Fine Adjust 11000 1.2 ps
Delay FS = 3 ns (800 μA, 4C) Fine Adjust 00000 0.86 ps
Delay FS = 3 ns (800 μA, 4C) Fine Adjust 11000 1.8 ps
Delay FS = 5 ns (400 μA, 4C) Fine Adjust 00000 1.2 ps
Delay FS = 5 ns (400 μA, 4C) Fine Adjust 11000 2.1 ps
Delay FS = 6 ns (200 μA, 1C) Fine Adjust 00000 1.3 ps
Delay FS = 6 ns (200 μA, 1C) Fine Adjust 11000 2.7 ps
Delay FS = 9 ns (200 μA, 4C) Fine Adjust 00000 2.0 ps
Delay FS = 9 ns (200 μA, 4C) Fine Adjust 00111 2.8 ps
1
This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, add the LVDS or CMOS output
jitter to this value using the root sum of the squares (RSS) method.

PLL AND DISTRIBUTION PHASE NOISE AND SPURIOUS

Table 7.
Parameter Min Typ Max Unit Test Conditions/Comments
PHASE NOISE AND SPURIOUS Depends on VCO/VCXO selection; measured at LVPECL
clock outputs, ABP = 6 ns; ICP = 5 mA; Ref = 30.72 MHz
VCXO = 245.76 MHz, fPFD = 1.2288 MHz, VCXO = Toyocom TCO-2112 245.76
R = 25, N = 200
245.76 MHz Output Divide by 1
Phase Noise at 100 kHz Offset <−145 dBc/Hz Dominated by VCXO phase noise
Spurious <−97 dBc First and second harmonics of fPFD; below measurement floor
61.44 MHz Output Divide by 4
Phase Noise at 100 kHz Offset <−155 dBc/Hz Dominated by VCXO phase noise
Spurious <−97 dBc First and second harmonics of fPFD; below measurement floor

SERIAL CONTROL PORT

Table 8.
Parameter Min Typ Max Unit Test Conditions/Comments
CSB, SCLK (INPUTS) Inputs have 30 kΩ internal pull-down
resistors
Input Logic 1 Voltage 2.0 V
Input Logic 0 Voltage 0.8 V
Input Logic 1 Current 110 µA
Input Logic 0 Current 1 µA
Input Capacitance 2 pF

Rev. C | Page 13 of 56
AD9510 Data Sheet
Parameter Min Typ Max Unit Test Conditions/Comments
SDIO (WHEN INPUT)
Input Logic 1 Voltage 2.0 V
Input Logic 0 Voltage 0.8 V
Input Logic 1 Current 10 nA
Input Logic 0 Current 10 nA
Input Capacitance 2 pF
SDIO, SDO (OUTPUTS)
Output Logic 1 Voltage 2.7 V
Output Logic 0 Voltage 0.4 V
TIMING
Clock Rate (SCLK, 1/tSCLK) 25 MHz
Pulse Width High, tPWH 16 ns
Pulse Width Low, tPWL 16 ns
SDIO to SCLK Setup, tDS 2 ns
SCLK to SDIO Hold, tDH 1 ns
SCLK to Valid SDIO and SDO, tDV 6 ns
CSB to SCLK Setup and Hold, tS, tH 2 ns
CSB Minimum Pulse Width High, tPWH 3 ns

FUNCTION PIN
Table 9.
Parameter Min Typ Max Unit Test Conditions/Comments
INPUT CHARACTERISTICS FUNCTION pin has 30 kΩ internal pull-down resistor;
normally, hold this pin high; do not leave unconnected
Logic 1 Voltage 2.0 V
Logic 0 Voltage 0.8 V
Logic 1 Current 110 µA
Logic 0 Current 1 µA
Capacitance 2 pF
RESET TIMING
Pulse Width Low 50 ns
SYNC TIMING
Pulse Width Low 1.5 High speed clock cycles High speed clock is CLK1 or CLK2, whichever is being used
for distribution

STATUS PIN
Table 10.
Parameter Min Typ Max Unit Test Conditions/Comments
OUTPUT CHARACTERISTICS When selected as a digital output (CMOS), there are other modes in
which the STATUS pin is not CMOS digital output; see Figure 37
Output Voltage High (VOH) 2.7 V
Output Voltage Low (VOL) 0.4 V
MAXIMUM TOGGLE RATE 100 MHz Applies when PLL mux is set to any divider or counter output, or PFD up/
down pulse; also applies in analog lock detect mode; usually debug mode
only; beware that spurs can couple to output when this pin is toggling
ANALOG LOCK DETECT
Capacitance 3 pF On-chip capacitance, used to calculate RC time constant for analog lock
detect readback; use a pull-up resistor

Rev. C | Page 14 of 56
Data Sheet AD9510
POWER
Table 11.
Parameter Min Typ Max Unit Test Conditions/Comments
POWER-UP DEFAULT MODE POWER DISSIPATION 550 600 mW Power-up default state, does not include power
dissipated in output load resistors; no clock
Power Dissipation 1.1 W All outputs on; four LVPECL outputs at 800 MHz, 4 LVDS
out at 800 MHz; does not include power dissipated in
external resistors
Power Dissipation 1.3 W All outputs on; four LVPECL outputs at 800 MHz, 4 CMOS
out at 62 MHz (5 pF load); does not include power
dissipated in external resistors
Power Dissipation 1.5 W All outputs on; four LVPECL outputs at 800 MHz, 4 CMOS
out at 125 MHz (5 pF load); does not include power
dissipated in external resistors
Full Sleep Power-Down 35 60 mW Maximum sleep is entered by setting Register 0x0A[1:0] =
01b and Register 0x58[4] = 1b; this powers off the PLL BG
and the distribution BG references; does not include
power dissipated in terminations
Power-Down (PDB) 60 80 mW Set the FUNCTION pin for PDB operation by setting
Register 0x58[6:5] = 11b; pull PDB low; does not include
power dissipated in terminations
POWER DELTA
CLK1, CLK2 Power-Down 10 15 25 mW
Divider, DIV 2 − 32 to Bypass 23 27 33 mW For each divider
LVPECL Output Power-Down (PD2, PD3) 50 65 75 mW For each output; does not include dissipation in
termination (PD2 only)
LVDS Output Power-Down 80 92 110 mW For each output
CMOS Output Power-Down (Static) 56 70 85 mW For each output; static (no clock)
CMOS Output Power-Down (Dynamic) 115 150 190 mW For each CMOS output, single-ended; clocking at
62 MHz with 5 pF load
CMOS Output Power-Down (Dynamic) 125 165 210 mW For each CMOS output, single-ended; clocking at
125 MHz with 5 pF load
Delay Block Bypass 20 24 60 mW Versus delay block operation at 1 ns fs with maximum
delay, output clocking at 25 MHz
PLL Section Power-Down 5 15 40 mW

Rev. C | Page 15 of 56
AD9510 Data Sheet

TIMING DIAGRAMS
tCLK1 DIFFERENTIAL

CLK1 80%

LVDS

20%
tPECL

05046-065
tRL tFL

tLVDS

05046-002
tCMOS

Figure 2. CLK1/CLK1B to Clock Output Timing, DIV = 1 Mode Figure 4. LVDS Timing, Differential

DIFFERENTIAL SINGLE-ENDED

80% 80%

LVPECL CMOS
3pF LOAD
20% 20%
05046-064

05046-066
tRP tFP tRC tFC

Figure 3. LVPECL Timing, Differential Figure 5. CMOS Timing, Single-Ended, 3 pF Load

Rev. C | Page 16 of 56
Data Sheet AD9510

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS
Table 12.
Parameter Value Thermal impedance measurements were taken on a 4-layer
board in still air in accordance with EIA/JESD51-7.
VS to GND −0.3 V to +3.6 V
VCP to GND −0.3 V to +5.8 V Table 13. Thermal Resistance
VCP to VS −0.3 V to +5.8 V Package θJA Unit
REFIN, REFINB to GND −0.3 V to VS + 0.3 V 64-Lead LFCSP 24 °C/W
RSET to GND −0.3 V to VS + 0.3 V
CPRSET to GND −0.3 V to VS + 0.3 V
CLK1, CLK1B, CLK2, CLK2B to GND −0.3 V to VS + 0.3 V ESD CAUTION
CLK1 to CLK1B −1.2 V to +1.2 V
CLK2 to CLK2B −1.2 V to +1.2 V
SCLK, SDIO, SDO, CSB to GND −0.3 V to VS + 0.3 V
OUT0, OUT1, OUT2, OUT3 to GND −0.3 V to VS + 0.3 V
OUT4, OUT5, OUT6, OUT7 to GND −0.3 V to VS + 0.3 V
FUNCTION to GND −0.3 V to VS + 0.3 V
STATUS to GND −0.3 V to VS + 0.3 V
Junction Temperature1 150°C
Storage Temperature −65°C to +150°C
Lead Temperature (10 sec) 300°C
1
See Thermal Characteristics for θJA
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.

Rev. C | Page 17 of 56
AD9510 Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CPRSET

OUT0B

OUT1B
OUT0

OUT1
RSET
GND

GND

GND
GND
VS

VS
VS

VS

VS
VS
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
REFIN 1 48 VS
REFINB 2 47 OUT4
GND 3 46 OUT4B
VS 4 45 VS
VCP 5 44 VS
CP 6 43 OUT5
GND 7 42 OUT5B
GND 8 AD9510 41 VS
VS 9 TOP VIEW 40 VS
CLK2 10 (Not to Scale) 39 OUT6
CLK2B 11 38 OUT6B
GND 12 37 VS
VS 13 36 VS
CLK1 14 35 OUT2
CLK1B 15 34 OUT2B
FUNCTION 16 33 VS
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
OUT7

OUT3
STATUS
SCLK
SDIO

GND
VS
OUT7B

VS
GND
OUT3B

VS
VS
GND
SDO
CSB

NOTES

05046-003
1. THE EXPOSED PADDLE ON THIS PACKAGE IS AN ELECTRICAL CONNECTION AS
WELL AS A THERMAL ENHANCEMENT. FOR THE DEVICE TO FUNCTION PROPERLY,
THE PADDLE MUST BE ATTACHED TO GROUND, GND.

Figure 6.

Table 14. Pin Function Descriptions

Pin No. Mnemonic Description
1 REFIN PLL Reference Input.
2 REFINB Complementary PLL Reference Input.
3, 7, 8, 12, 22, GND Ground.
27, 32, 49, 50,
55, 62
4, 9, 13, 23, 26, VS Power Supply (3.3 V) VS.
30, 31, 33, 36,
37, 40, 41, 44,
45, 48, 51, 52,
56, 59, 60, 64
5 VCP Charge Pump Power Supply VCPS. It must be greater than or equal to VS. VCPS can be set as high as 5.5 V for
VCOs requiring extended tuning range.
6 CP Charge Pump Output.
10 CLK2 Clock Input Used to Connect External VCO/VCXO to Feedback Divider, N. CLK2 also drives the distribution
section of the chip and can be used as a generic clock input when PLL is not used.
11 CLK2B Complementary Clock Input Used in Conjunction with CLK2.
14 CLK1 Clock Input that Drives Distribution Section of the Chip.
15 CLK1B Complementary Clock Input Used in Conjunction with CLK1.
16 FUNCTION Multipurpose Input Can Be Programmed as a Reset (RESETB), Sync (SYNCB), or Power-Down (PDB) Pin. This
pin is internally pulled down by a 30 kΩ resistor. If this pin is left NC, the part is in reset by default. To avoid
this, connect this pin to VS with a 1 kΩ resistor.
17 STATUS Output Used to Monitor PLL Status and Sync Status.
18 SCLK Serial Data Clock.
19 SDIO Serial Data I/O.
20 SDO Serial Data Output.
21 CSB Serial Port Chip Select.
24 OUT7B Complementary LVDS/Inverted CMOS Output.
25 OUT7 LVDS/CMOS Output.

Rev. C | Page 18 of 56
Data Sheet AD9510
Pin No. Mnemonic Description
28 OUT3B Complementary LVPECL Output.
29 OUT3 LVPECL Output.
34 OUT2B Complementary LVPECL Output.
35 OUT2 LVPECL Output.
38 OUT6B Complementary LVDS/Inverted CMOS Output. OUT6 includes a delay block.
39 OUT6 LVDS/CMOS Output. OUT6 includes a delay block.
42 OUT5B Complementary LVDS/Inverted CMOS Output. OUT5 includes a delay block.
43 OUT5 LVDS/CMOS Output. OUT5 includes a delay block.
46 OUT4B Complementary LVDS/Inverted CMOS Output.
47 OUT4 LVDS/CMOS Output.
53 OUT1B Complementary LVPECL Output.
54 OUT1 LVPECL Output.
57 OUT0B Complementary LVPECL Output.
58 OUT0 LVPECL Output.
61 RSET Current Set Resistor to Ground. Nominal value = 4.12 kΩ.
63 CPRSET Charge Pump Current Set Resistor to Ground. Nominal value = 5.1 kΩ.
EPAD Exposed Paddle. The exposed paddle on this package is an electrical connection as well as a thermal
enhancement. For the device to function properly, the paddle must be attached to ground, GND.

Rev. C | Page 19 of 56
AD9510 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

0.8 1.3

0.7 4 LVPECL + 4 LVDS (DIV ON)

4 LVPECL + 4 LVDS (DIV BYPASSED) 1.2
0.6

0.5
1.1
POWER (W)

POWER (W)
DEFAULT–3 LVPECL + 2 LVDS (DIV ON)
0.4 3 LVPECL + 4 CMOS (DIV ON)
4 LVDS ONLY (DIV ON)
1.0
0.3
4 LVPECL ONLY (DIV ON)
0.2
0.9
0.1
05046-060

05046-061
0 0.8
0 400 800 0 20 40 60 80 100 120
OUTPUT FREQUENCY (MHz) OUTPUT FREQUENCY (MHz)

Figure 7. Power vs. Frequency—LVPECL, LVDS (PLL Off) Figure 10. Power vs. Frequency—LVPECL, CMOS (PLL Off)

CLK1 (EVAL BOARD) REFIN (EVAL BOARD)

3GHz 5MHz 5GHz

3GHz

05046-062
05046-043

Figure 8. CLK1 Smith Chart (Evaluation Board) Figure 11. REFIN Smith Chart (Evaluation Board)

CLK2 (EVAL BOARD)

5MHz
3GHz
05046-044

Figure 9. CLK2 Smith Chart (Evaluation Board)

Rev. C | Page 20 of 56
Data Sheet AD9510
10 10

0 0

–10 –10

–20 –20

–30 –30

–40 –40

–50 –50

–60 –60

–70 –70

05046-059
05046-058
–80 –80

–90 –90
CENTER 245.75MHz 30kHz/ SPAN 300kHz CENTER 61.44MHz 30kHz/ SPAN 300kHz

Figure 12. Phase Noise, LVPECL, DIV 1, FVCXO = 245.76 MHz, Figure 15. Phase Noise, LVPECL, DIV 4, fVCXO = 245.76 MHz,
fOUT = 245.76 MHz, fPFD = 1.2288 MHz, R = 25, N = 200 fOUT = 61.44 MHz, fPFD = 1.2288 MHz, R = 25, N = 200

0 –135

PFD NOISE REFERRED TO PFD INPUT (dBc/Hz)

–10
–140
–20

–30 –145

–40
–150
–50
–155
–60

–70 –160

–80
–165

05046-057
05046-063

–90

100 –170
CENTER 1.5GHz 250kHz/ SPAN 2.5MHz 0.1 1 10 100
PFD FREQUENCY (MHz)

Figure 13. PLL Reference Spurs: VCO 1.5 GHz, fPFD = 1 MHz Figure 16. Phase Noise (Referred to CP Output) vs. PFD Frequency (fPFD)

5.0 5.0

4.5 4.5

4.0 4.0
CURRENT FROM CP PIN (mA)
CURRENT FROM CP PIN (mA)

3.5 3.5
PUMP DOWN PUMP UP PUMP DOWN PUMP UP
3.0 3.0

2.5 2.5

2.0 2.0

1.5 1.5

1.0 1.0
05046-042
05046-041

0.5 0.5

0 0
0 0.5 1.0 1.5 2.0 2.5 3.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VOLTAGE ON CP PIN (V) VOLTAGE ON CP PIN (V)

Figure 14. Charge Pump Output Characteristics at VCPs = 3.3 V Figure 17. Charge Pump Output Characteristics at VCPs = 5.0 V

Rev. C | Page 21 of 56
AD9510 Data Sheet
1.8

1.7

DIFFERENTIAL SWING (V p-p)

1.6

1.5

1.4

1.3

05046-053

05046-056
1.2
VERT 500mV/DIV HORIZ 500ps/DIV 100 600 1100 1600
OUTPUT FREQUENCY (MHz)

Figure 18. LVPECL Differential Output at 800 MHz Figure 21. LVPECL Differential Output Swing vs. Frequency

750

700

DIFFERENTIAL SWING (mV p-p)

650

600

550
05046-054

05046-050
500
VERT 100mV/DIV HORIZ 500ps/DIV 100 300 500 700 900
OUTPUT FREQUENCY (MHz)

Figure 19. LVDS Differential Output at 800 MHz Figure 22. LVDS Differential Output Swing vs. Frequency

3.5
2pF
3.0

2.5
OUTPUT (VPK)

10pF
2.0

1.5

1.0

20pF
0.5
05046-055

05046-047

0
VERT 500mV/DIV HORIZ 1ns/DIV 0 100 200 300 400 500 600
OUTPUT FREQUENCY (MHz)

Figure 20. CMOS Single-Ended Output at 250 MHz with 10 pF Load Figure 23. CMOS Single-Ended Output Swing vs. Frequency and Load

Rev. C | Page 22 of 56
Data Sheet AD9510
–110 –110

–120 –120

–130 –130
L(f) (dBc/Hz)

L(f) (dBc/Hz)
–140 –140

–150 –150

–160 –160

05046-051

05046-052
–170 –170
10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M
OFFSET (Hz) OFFSET (Hz)

Figure 24. Additive Phase Noise—LVPECL DIV 1, 245.76 MHz, Figure 27. Additive Phase Noise—LVPECL DIV1, 622.08 MHz
Distribution Section Only

–80 –80

–90 –90

–100 –100

–110 –110
L(f) (dBc/Hz)

L(f) (dBc/Hz)
–120 –120

–130 –130

–140 –140

–150 –150

–160 –160
05046-048

05046-049
–170 –170
10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M
OFFSET (Hz) OFFSET (Hz)

Figure 25. Additive Phase Noise—LVDS DIV 1, 245.76 MHz Figure 28. Additive Phase Noise—LVDS DIV2, 122.88 MHz

–100 –100

–110 –110

–120 –120
L(f) (dBc/Hz)

L(f) (dBc/Hz)

–130 –130

–140 –140

–150 –150

–160 –160
05046-045

05046-046

–170 –170
10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M
OFFSET (Hz) OFFSET (Hz)

Figure 26. Additive Phase Noise—CMOS DIV 1, 245.76 MHz Figure 29. Additive Phase Noise—CMOS DIV4, 61.44 MHz

Rev. C | Page 23 of 56
AD9510 Data Sheet

TERMINOLOGY
Phase Jitter and Phase Noise Time Jitter
An ideal sine wave has a continuous and even progression of Phase noise is a frequency domain phenomenon. In the time
phase with time from 0 to 360 degrees for each cycle. Actual domain, the same effect is exhibited as time jitter. When observing
signals, however, display a certain amount of variation from a sine wave, the time of successive zero crossings is seen to vary.
ideal phase progression over time. This phenomenon is called In a square wave, the time jitter is seen as a displacement of the
phase jitter. Although many causes can contribute to phase edges from their ideal (regular) times of occurrence. In both
jitter, one major cause is random noise, which is characterized cases, the variations in timing from the ideal are the time jitter.
statistically as being Gaussian (normal) in distribution. Since these variations are random in nature, the time jitter is
specified in units of seconds root mean square (rms) or 1 sigma
This phase jitter leads to a spreading out of the energy of the of the Gaussian distribution.
sine wave in the frequency domain, producing a continuous
power spectrum. This power spectrum is usually reported as a Time jitter that occurs on a sampling clock for a DAC or an
series of values whose units are dBc/Hz at a given offset in fre- ADC decreases the SNR and dynamic range of the converter.
quency from the sine wave (carrier). The value is a ratio, expressed A sampling clock with the lowest possible jitter provides the
in dB, of the power contained within a 1 Hz bandwidth with highest performance from a given converter.
respect to the power at the carrier frequency. For each measure- Additive Phase Noise
ment, the offset from the carrier frequency is also given. Additive phase noise is the amount of phase noise attributable
It is meaningful to integrate the total power contained within to the device or subsystem being measured. The phase noise of
some interval of offset frequencies (for example, 10 kHz to any external oscillators or clock sources is subtracted. This
10 MHz). This is called the integrated phase noise over that makes it possible to predict the degree to which the device
frequency offset interval and can be readily related to the time impacts the total system phase noise when used in conjunction
jitter due to the phase noise within that offset frequency interval. with the various oscillators and clock sources, each of which
contribute their own phase noise to the total. In many cases, the
Phase noise has a detrimental effect on the performance of phase noise of one element dominates the system phase noise.
analog-to-digital converters (ADCs), digital-to-analog
converters (DACs), and signal input (RF) mixers. It lowers the Additive Time Jitter
achievable dynamic range of the converters and mixers, Additive time jitter is the amount of time jitter attributable to
although they are affected in different ways. the device or subsystem being measured. The time jitter of any
external oscillators or clock sources is subtracted. This makes it
possible to predict the degree to which the device impacts the total
system time jitter when used in conjunction with the various
oscillators and clock sources, each of which contribute their
own time jitter to the total. In many cases, the time jitter of the
external oscillators and clock sources dominates the system
time jitter.

Rev. C | Page 24 of 56
Data Sheet AD9510

TYPICAL MODES OF OPERATION

PLL WITH EXTERNAL VCXO/VCO FOLLOWED BY CLOCK DISTRIBUTION ONLY
CLOCK DISTRIBUTION It is possible to use only the distribution section whenever the
This is the most common operational mode for the AD9510. PLL section is not needed. Save power by shutting off the PLL
An external oscillator (shown as VCO/VCXO) is phase locked block, and by powering down any unused clock channels (see
to a reference input frequency applied to REFIN. The loop filter the Register Map and Description section).
is usually a passive design. A VCO or a VCXO can be used. The In distribution mode, both the CLK1 and CLK2 inputs are available
CLK2 input is connected internally to the feedback divider, N. for distribution to outputs via a low jitter multiplexer (mux).
The CLK2 input provides the feedback path for the PLL. If the
VCO/VCXO frequency exceeds maximum frequency of the VREF PLL
AD9510 REF
output or outputs being used, an appropriate divide ratio must REFIN
be set in the corresponding divider or dividers in the Distribution R
CHARGE
PFD PUMP
Section. Save some power by shutting off unused functions and N

by powering down any unused clock channels (see the Register FUNCTION STATUS
Map and Description section). CLK1 CLK2
CLOCK CLOCK
INPUT 1 INPUT 2
LVPECL

DIVIDE
VREF PLL
AD9510 REF
LVPECL
REFIN
REFERENCE R
INPUT DIVIDE
PFD CHARGE LOOP
PUMP FILTER
N LVPECL
FUNCTION STATUS DIVIDE

CLK1 CLK2 LVPECL

VCXO,
VCO SERIAL
PORT DIVIDE
LVPECL
CLOCK
DIVIDE LVDS/CMOS OUTPUTS
DIVIDE
LVPECL

DIVIDE LVDS/CMOS

LVPECL
DIVIDE ∆T

DIVIDE LVDS/CMOS

LVPECL DIVIDE ∆T
SERIAL
PORT DIVIDE LVDS/CMOS
CLOCK

05046-011
LVDS/CMOS OUTPUTS DIVIDE

DIVIDE

LVDS/CMOS Figure 31. Clock Distribution Mode

DIVIDE ∆T

LVDS/CMOS

DIVIDE ∆T

LVDS/CMOS
05046-010

DIVIDE

Figure 30. PLL and Clock Distribution Mode

Rev. C | Page 25 of 56
AD9510 Data Sheet
PLL WITH EXTERNAL VCO AND BAND-PASS
FILTER FOLLOWED BY CLOCK DISTRIBUTION
An external band-pass filter (BPF) can be used to improve the
phase noise and spurious characteristics of the PLL output. This
option is most appropriate to optimize cost by choosing a less
expensive VCO combined with a moderately priced filter. Note
that the BPF is shown outside of the VCO-to-N divider path,
with the BP filter outputs routed to CLK1. Save some power by
shutting off unused functions, and by powering down any unused
clock channels (see the Register Map and Description section).

VREF PLL
AD9510 REF
REFIN
REFERENCE R
INPUT CHARGE LOOP
PFD
PUMP FILTER
N

FUNCTION STATUS

CLK1 CLK2
VCO

LVPECL

DIVIDE BPF

LVPECL

DIVIDE

LVPECL

DIVIDE

LVPECL
SERIAL
PORT DIVIDE
CLOCK
LVDS/CMOS OUTPUTS
DIVIDE

LVDS/CMOS

DIVIDE ∆T

LVDS/CMOS

DIVIDE ∆T

LVDS/CMOS
05046-012

DIVIDE

Figure 32. AD9510 with VCO and BPF Filter

Rev. C | Page 26 of 56
Data Sheet AD9510
VS GND RSET CPRSET VCP

DISTRIBUTION PLL
REF
AD9510 REF
REFIN
250MHz R DIVIDER PHASE
REFINB CHARGE
FREQUENCY PUMP CP
N DIVIDER DETECTOR
SYNCB,
FUNCTION RESETB,
PDB PLL STATUS
SETTINGS

CLK1 CLK2
1.6GHz 1.6GHz
CLK1B CLK2B
PROGRAMMABLE
DIVIDERS AND
PHASE ADJUST LVPECL
OUT0
/1, /2, /3... /31, /32
OUT0B
LVPECL
OUT1
/1, /2, /3... /31, /32
OUT1B
1.2GHz
LVPECL LVPECL
OUT2
/1, /2, /3... /31, /32
OUT2B
SCLK LVPECL
SDIO SERIAL OUT3
CONTROL /1, /2, /3... /31, /32
SDO PORT OUT3B
CSB LVDS/CMOS
OUT4
/1, /2, /3... /31, /32
OUT4B
LVDS/CMOS
OUT5
/1, /2, /3... /31, /32 ∆T 800MHz
OUT5B
LVDS
LVDS/CMOS
OUT6 250MHz
/1, /2, /3... /31, /32 ∆T CMOS
OUT6B
LVDS/CMOS
OUT7
/1, /2, /3... /31, /32

05046-013
OUT7B

Figure 33. Functional Block Diagram Showing Maximum Frequencies

Rev. C | Page 27 of 56
AD9510 Data Sheet

FUNCTIONAL DESCRIPTION
OVERALL PLL Reference Input—REFIN
Figure 33 shows a block diagram of the AD9510. The chip The REFIN/REFINB pins can be driven by either a differential
combines a programmable PLL core with a configurable clock or a single-ended signal. These pins are internally self-biased so
distribution system. A complete PLL requires the addition of a that they can be ac-coupled via capacitors. It is possible to dc-
suitable external VCO (or VCXO) and loop filter. This PLL can couple to these inputs. If REFIN is driven single-ended, decouple
lock to a reference input signal and produce an output that is the unused side (REFINB) via a suitable capacitor to a quiet
related to the input frequency by the ratio defined by the pro- ground. Figure 34 shows the equivalent circuit of REFIN.
grammable R and N dividers. The PLL cleans up some jitter VS

from the external reference signal, depending on the loop band- 10kΩ 12kΩ
REFIN
width and the phase noise performance of the VCO (VCXO). 150Ω

The output from the VCO (VCXO) can be applied to the clock REFINB
150Ω
distribution section of the chip, where it can be divided by any 10kΩ 10kΩ

integer value from 1 to 32. The duty cycle and relative phase of

05046-033
the outputs can be selected. There are four LVPECL outputs,
(OUT0, OUT1, OUT2, and OUT3) and four outputs that can be Figure 34. REFIN Equivalent Circuit
either LVDS or CMOS level outputs (OUT4, OUT5, OUT6, and VCO/VCXO Clock Input—CLK2
OUT7). Two of these outputs (OUT5 and OUT6) can also make
The CLK2 differential input is used to connect an external
use of a variable delay block.
VCO or VCXO to the PLL. Only the CLK2 input port has a
Alternatively, the clock distribution section can be driven directly connection to the PLL N divider. This input can receive up to
by an external clock signal, and the PLL can be powered off. 1.6 GHz. These inputs are internally self-biased and must be
Whenever the clock distribution section is used alone, there is ac-coupled via capacitors.
no clock cleanup. The jitter of the input clock signal is passed
Alternatively, CLK2 can be used as an input to the distribution
along directly to the distribution section and may dominate at
section. This is accomplished by setting Register 0x45[0] = 0b.
the clock outputs.
The default condition is for CLK1 to feed the distribution section.
PLL SECTION CLOCK INPUT
STAGE
The AD9510 consists of a PLL section and a distribution section. VS

If desired, the PLL section can be used separately from the

CLK
distribution section.
The AD9510 has a complete PLL core on-chip, requiring only CLKB

an external loop filter and VCO/VCXO. This PLL is based on 2.5kΩ 2.5kΩ

the ADF4106, a PLL noted for its superb low phase noise per- 5kΩ

formance. The operation of the AD9510 PLL is nearly identical 5kΩ

05046-016

to that of the ADF4106, offering an advantage to those with

experience with the ADF series of PLLs. Differences include the Figure 35. CLK1, CLK2 Equivalent Input Circuit
addition of differential inputs at REFIN and CLK2, a different
PLL Reference Divider—R
control register architecture. Also, the prescaler is changed to
allow N as low as 1. The AD9510 PLL implements the digital The REFIN/REFINB inputs are routed to reference divider, R,
lock detect feature somewhat differently than the ADF4106 which is a 14-bit counter. R can be programmed to any value
does, offering improved functionality at higher PFD rates. See from 1 to 16383 (a value of 0 results in a divide by 1) via its
the Register Map Description section. control register (Register 0x0B[5:0], Register 0x0C[7:0]). The
output of the R divider goes to one of the phase frequency
detector inputs. Do not exceed the maximum allowable frequency
into the phase frequency detector (PFD). This means that the
REFIN frequency divided by R must be less than the maximum
allowable PFD frequency. See Figure 34.

Rev. C | Page 28 of 56
Data Sheet AD9510
VCO/VCXO Feedback Divider—N (P, A, B) A and B Counters
The N divider is a combination of a prescaler, P (3 bits), and two The AD9510 B counter has a bypass mode (B = 1), which is not
counters, A (6 bits) and B (13 bits). Although the PLL of the available on the ADF4106. The B counter bypass mode is valid
AD9510 is similar to the ADF4106, the AD9510 has a redesigned only when using the prescaler in FD mode. The B counter is
prescaler that allows lower values of N. The prescaler has both bypassed by writing 1 to the B counter bypass bit (Register 0x0A[6]
a dual modulus (DM) and a fixed divide (FD) mode. The AD9510 = 1b). The valid range of the B counter is 3 to 8191. The default
prescaler modes are shown in Table 15. after a reset is 0, which is invalid.

Table 15. PLL Prescaler Modes Note that the A counter is not used when the prescaler is in
FD mode.
Mode
(FD = Fixed Divide, Value in Note also that the A/B counters have their own reset bit, which
DM = Dual Modulus) Register 0x0A[4:2] Divide By is primarily intended for testing. The A and B counters can also
FD 000 1 be reset using the shared reset bit of the R, A, and B counters
FD 001 2 (Register 0x09[0]).
P = 2 DM 010 P/P + 1 = 2/3
Determining Values for P, A, B, and R
P = 4 DM 011 P/P + 1 = 4/5
P = 8 DM 100 P/P + 1 = 8/9 When operating the AD9510 in a dual-modulus mode, the
P = 16 DM 101 P/P + 1 = 16/17 input reference frequency, fREF, is related to the VCO output
P = 32 DM 110 P/P + 1 = 32/33 frequency, fVCO.
FD 111 3 fVCO = (fREF/R) × (PB + A) = fREF × N/R
When using the prescaler in FD mode, the A counter is not When operating the prescaler in fixed divide mode, the A
used, and the B counter may need to be bypassed. The DM counter is not used and the equation simplifies to
prescaler modes set some upper limits on the frequency, which fVCO = (fREF/R) × (PB) = fREF × N/R
can be applied to CLK2. See Table 16.
By using combinations of dual modulus and fixed divide modes,
Table 16. Frequency Limits of Each Prescaler Mode the AD9510 can achieve values of N all the way down to N = 1.
Mode (DM = Dual Modulus) CLK2 Table 17 shows how a 10 MHz reference input can be locked to
P = 2 DM (2/3) <600 MHz any integer multiple of N. Note that the same value of N can be
P = 4 DM (4/5) <1000 MHz derived in different ways, as illustrated by N = 12.
P = 8 DM (8/9) <1600 MHz
P = 16 DM <1600 MHz
P = 32 DM <1600 MHz

Table 17. P, A, B, R—Smallest Values for N

fREF R P A B N fVCO Mode Notes
10 1 1 X 1 1 10 FD P = 1, B = 1 (Bypassed)
10 1 2 X 1 2 20 FD P = 2, B = 1 (Bypassed)
10 1 1 X 3 3 30 FD P = 1, B = 3
10 1 1 X 4 4 40 FD P = 1, B = 4
10 1 1 X 5 5 50 FD P = 1, B = 5
10 1 2 X 3 6 60 FD P = 2, B = 3
10 1 2 0 3 6 60 DM P/P + 1 = 2/3, A = 0, B = 3
10 1 2 1 3 7 70 DM P/P + 1 = 2/3, A = 1, B = 3
10 1 2 2 3 8 80 DM P/P + 1 = 2/3, A = 2, B = 3
10 1 2 1 4 9 90 DM P/P + 1 = 2/3, A = 1, B = 4
10 1 2 X 5 10 100 FD P = 2, B = 5
10 1 2 0 5 10 100 DM P/P + 1 = 2/3, A = 0, B = 5
10 1 2 1 5 11 110 DM P/P + 1 = 2/3, A = 1, B = 5
10 1 2 X 6 12 120 FD P = 2, B = 6
10 1 2 0 6 12 120 DM P/P + 1 = 2/3, A = 0, B = 6
10 1 4 0 3 12 120 DM P/P + 1 = 4/5, A = 0, B = 3
10 1 4 1 3 13 130 DM P/P + 1 = 4/5, A = 1, B = 3

Rev. C | Page 29 of 56
AD9510 Data Sheet
Phase Frequency Detector (PFD) and Charge Pump eliminates the dead zone around the phase-locked condition
The PFD takes inputs from the R counter and the N counter and thereby reduces the potential for certain spurs that can be
(N = BP + A) and produces an output proportional to the impressed on the VCO signal.
phase and frequency difference between them. Figure 36 is a STATUS Pin
simplified schematic. The PFD includes a programmable delay The output multiplexer on the AD9510 allows access to various sig-
element that controls the width of the antibacklash pulse. This nals and internal points on the chip at the STATUS pin. Figure 37
pulse ensures that there is no dead zone in the PFD transfer shows a block diagram of the STATUS pin section. The function
function and minimizes phase noise and reference spurs. Two of the STATUS pin is controlled by Register 0x8[5:2].
bits in Register 0x0D[1:0] control the width of the pulse.
VP
PLL Digital Lock Detect
CHARGE The STATUS pin can display two types of PLL lock detect:
PUMP
HI D1 Q1
UP digital (DLD) and analog (ALD). Whenever digital lock detect
U1 is desired, the STATUS pin provides a CMOS level signal, which
R DIVIDER can be active high or active low.
CLR1

PROGRAMMABLE
The digital lock detect has one of two time windows, as selected
U3 CP
DELAY
by Register 0x0D[5]. The default (Register 0x0D[5] = 0b) requires
ANTIBACKLASH the signal edges on the inputs to the PFD to be coincident within
PULSE WIDTH
9.5 ns to set the DLD true, which then must separate by at least
CLR2 DOWN
HI D2 Q2 15 ns to give DLD = false.
U2
N DIVIDER The other setting (Register 0x0D[5] = 1) makes these coinci-
dence times 3.5 ns for DLD = true and 7 ns for DLD = false.
05046-014

GND
The DLD can be disabled by writing 1 to Register 0x0D[6].
Figure 36. PFD Simplified Schematic and Timing (In Lock)
If the signal at REFIN goes away while DLD is true, the DLD
Antibacklash Pulse
does not necessarily indicate loss of lock. See the Loss of
The PLL features a programmable antibacklash pulse width that Reference section for more information.
is set by the value in Register 0x0D[1:0]. The default antiback-
lash pulse width is 1.3 ns (Register 0x0D[1:0] = 00b) and
normally does not need to be changed. The antibacklash pulse

OFF (LOW) (DEFAULT)

SYNC
DIGITAL LOCK DETECT (ACTIVE HIGH) DETECT VS
N DIVIDER OUTPUT
DIGITAL LOCK DETECT (ACTIVE LOW)
CONTROL FOR ANALOG
LOCK DETECT MODE

R DIVIDER OUTPUT
ANALOG LOCK DETECT (N-CHANNEL OPEN DRAIN)
A COUNTER OUTPUT
PRESCALER OUTPUT (NCLK) STATUS
PFD UP PULSE PIN
PFD DOWN PULSE
LOSS OF REFERENCE (ACTIVE HIGH)
TRISTATE
ANALOG LOCK DETECT (P-CHANNEL OPEN DRAIN)
LOSS OF REFERENCE OR LOCK DETECT (ACTIVE HIGH)
GND
LOSS OF REFERENCE OR LOCK DETECT (ACTIVE LOW) SYNC DETECT ENABLE
LOSS OF REFERENCE (ACTIVE LOW) 0x58[0]
05046-015

PLL MUX CONTROL

0x08[5:2]

Figure 37. STATUS Pin Circuit CLK1 Clock Input

Rev. C | Page 30 of 56
Data Sheet AD9510
PLL Analog Lock Detect The digital lock detect (DLD) block of the AD9510 requires a
An analog lock detect (ALD) signal can be selected. When ALD PLL reference signal to be present in order for the digital lock
is selected, the signal at the STATUS pin is either an open-drain detect output to be valid. It is possible to have a digital lock
P-channel (Register 0x08[5:2] = 1100) or an open-drain detect indication (DLD = true) that remains true even after a
N-channel (Register 0x08[5:2] = 0101b). loss of reference signal. For this reason, the digital lock detect
signal alone cannot be relied upon if the reference has been lost.
The analog lock detect signal is true (relative to the selected
To combine the DLD and the LREF into a single signal at the
mode) with brief false pulses. These false pulses shorten as the
STATUS pin, set Register 0x08[5:2] = [1101] to obtain a signal
inputs to the PFD are nearer to coincidence and longer as they
that is the logical OR of the loss of lock (inverse of DLD) and
are further from coincidence.
the loss of reference (LREF) active high. If an active low version
To extract a usable analog lock detect signal, an external resistor- of this same signal is desired, set Register 0x08[5:2] = [1110].
capacitor (RC) network is required to provide an analog filter
The reference monitor is enabled only after the DLD signal is high
with the appropriate RC constant to allow for the discrimina-
for the number of PFD cycles set by the value in Register 0x07[6:5].
tion of a lock condition by an external voltage comparator. A
This delay is measured in PFD cycles. The delay ranges from 3 PFD
1 kΩ resistor in parallel with a small capacitance usually fulfills
cycles (default) to 24 PFD cycles. When the reference goes away,
this requirement. However, some experimentation may be LREF goes true and the charge pump goes into tristate.
required to obtain the desired operation.
User intervention is required to take the part out of this state.
The analog lock detect function may introduce some spurious
First, Register 0x07[2] = 0b must be written to disable the loss
energy into the clock outputs. It is prudent to limit the use of
of reference circuit, taking the charge pump out of tristate and
the ALD when the best possible jitter/phase noise performance
causing LREF to go false. A second write of Register 0x07[2] = 1
is required on the clock outputs.
is required to reenable the loss of reference circuit.
Loss of Reference
The AD9510 PLL can warn of a loss of reference signal at PLL LOOP LOCKS
DLD GOES TRUE
REFIN. The loss of reference monitor internally sets a flag LREF IS FALSE
WRITE 0x07[2] = 0
called LREF. Externally, this signal can be observed in several LREF SET FALSE
CHARGE PUMP COMES
ways on the STATUS pin, depending on the PLL MUX control OUT OF TRISTATE n PFD CYCLES WITH
WRITE 0x07[2] = 1 DLD TRUE
settings in Register 0x08[5:2]. The LREF alone can be observed LOR ENABLED (n SET BY 0x07[6:5])
as an active high signal by setting Register 0x08[5:2] = [1010] or
as an active low signal by setting Register 0x08[5:2] = [1111].
The loss of reference circuit is clocked by the signal from the CHARGE PUMP CHECK FOR PRESENCE
GOES INTO TRISTATE. OF REFERENCE.
VCO, which means that there must be a VCO signal present to LREF SET TRUE. LREF STAYS FALSE IF
REFERENCE IS DETECTED.
MISSING

05046-034
detect a loss of reference. REFERENCE
DETECTED
Figure 38. Loss of Reference Sequence of Events

Rev. C | Page 31 of 56
AD9510 Data Sheet
FUNCTION PIN DISTRIBUTION SECTION
The FUNCTION pin (16) has three functions that are selected As previously mentioned, the AD9510 is partitioned into two
by the value in Register 0x58[6:5]. This pin is internally pulled operational sections: PLL and distribution. The PLL Section is
down by a 30 kΩ resistor. If this pin is left unconnected, the discussed previously in this data sheet. If desired, the distribution
part is in reset by default. To avoid this, connect this pin to VS section can be used separately from the PLL section.
with a 1 kΩ resistor.
CLK1 AND CLK2 CLOCK INPUTS
RESETB: Register 0x58[6:5] = 00b (Default) Either CLK1 or CLK2 can be selected as the input to the distri-
In its default mode, the FUNCTION pin acts as RESETB, which bution section. The CLK1 input can be connected to drive the
generates an asynchronous reset or hard reset when pulled low. distribution section only. CLK1 is selected as the source for the
The resulting reset writes the default values into the serial control distribution section by setting Register 0x45[0] = 1. This is the
port buffer registers as well as loading them into the chip control power-up default state.
registers. When the RESETB signal goes high again, a synchro-
CLK1 and CLK2 work for inputs up to 1600 MHz. A higher input
nous sync is issued (see the SYNCB: Register 0x58[6:5] = 01b
slew rate improves the jitter performance. The input level must
section) and the AD9510 resumes operation according to the
be between approximately 150 mV p-p to no more than 2 V p-p.
default values of the registers.
Anything greater may result in turning on the protection diodes
SYNCB: Register 0x58[6:5] = 01b on the input pins, which may degrade the jitter performance.
Using the FUNCTION pin causes a synchronization or See Figure 35 for the CLK1 and CLK2 equivalent input circuit.
alignment of phase among the various clock outputs. The These inputs are fully differential and self-biased. The signal
synchronization applies only to clock outputs that must be ac-coupled using capacitors. If a single-ended input
• Are not powered down must be used, this can be accommodated by ac-coupling to one
• The divider is not masked (no sync = 0b) side of the differential input only. Bypass the other side of the
• Are not bypassed (bypass = 0b) input to a quiet ac ground by a capacitor.
Power down the unselected clock input (CLK1 or CLK2) to
SYNCB is level and rising edge sensitive. When SYNCB is low,
eliminate any possibility of unwanted crosstalk between the
the set of affected outputs are held in a predetermined state,
selected clock input and the unselected clock input.
defined by the start high bit of each divider. On a rising edge,
the dividers begin after a predefined number of fast clock cycles DIVIDERS
(fast clock is the selected clock input, CLK1 or CLK2) as Each of the eight clock outputs of the AD9510 has its own
determined by the values in the phase offset bits of the divider. divider. The divider can be bypassed to obtain an output at the
The SYNCB application of the FUNCTION pin is always active, same frequency as the input (1×). When a divider is bypassed,
regardless of whether the pin is also assigned to perform reset it is powered down to save power.
or power-down. When the SYNCB function is selected, the All integer divide ratios from 1 to 32 can be selected. A divide
FUNCTION pin does not act as either RESETB or PDB. ratio of 1 is selected by bypassing the divider.
PDB: Register 0x58[6:5] = 11b Each divider can be configured for divide ratio, phase, and duty
The FUNCTION pin can also be programmed to work as an cycle. The phase and duty cycle values that can be selected
asynchronous full power-down, PDB. Even in this full power- depend on the divide ratio that is chosen.
down mode, there is still some residual VS current because Setting the Divide Ratio
some on-chip references continue to operate. In PDB mode,
The divide ratio is determined by the values written via the serial
the FUNCTION pin is active low. The chip remains in a power-
control port (SCP) to the registers that control each individual
down state until PDB is returned to logic high. The chip returns
output, OUT0 to OUT7. These are the even numbered registers
to the settings programmed prior to the power-down.
beginning at Register 0x48 and going through Register 0x56.
See the Chip Power-Down or Sleep Mode—PDB section for more Each of these registers is divided into bits that control the
details on what occurs during a PDB initiated power-down. number of clock cycles that the divider output stays high
(HIGH_CYCLES[3:0]) and the number of clock cycles that the
divider output stays low (LOW_CYCLES[7:4]). Each value is 4
bits and has the range of 0 to 15.
The divide ratio is set by
Divide Ratio = (HIGH_CYCLES + 1) + (LOW_CYCLES + 1)

Rev. C | Page 32 of 56
Data Sheet AD9510
Example 1: Although the second set of settings produces the same divide
Set the Divide Ratio = 2 ratio, the resulting duty cycle is not the same.

HIGH_CYCLES = 0 Setting the Duty Cycle

The duty cycle and the divide ratio are related. Different
LOW_CYCLES = 0
divide ratios have different duty cycle options. For example, if
Divide Ratio = (0 + 1) + (0 + 1) = 2 Divide Ratio = 2, the only duty cycle possible is 50%. If the
Example 2: Divide Ratio = 4, the duty cycle can be 25%, 50%, or 75%.
Set Divide Ratio = 8 The duty cycle is set by
HIGH_CYCLES = 3 Duty Cycle = (HIGH_CYCLES + 1)/((HIGH_CYCLES + 1)
LOW_CYCLES = 3 + (LOW_CYCLES + 1))

Divide Ratio = (3 + 1) + (3 + 1) = 8 See Table 18 for the values for the available duty cycles for each
divide ratio.
Note that a Divide Ratio of 8 can also be obtained by setting:
HIGH_CYCLES = 2
LOW_CYCLES = 4
Divide Ratio = (2 + 1) + (4 + 1) = 8

Table 18. Duty Cycle and Divide Ratio

Address 0x48 to Address 0x48 to
Address 0x56 Address 0x56
Divide Ratio Duty Cycle (%) LO[7:4] HI[3:0] Divide Ratio Duty Cycle (%) LO[7:4] HI[3:0]
2 50 0 0 9 33 5 2
3 67 0 1 9 78 1 6
3 33 1 0 9 22 6 1
4 50 1 1 9 89 0 7
4 75 0 2 9 11 7 0
4 25 2 0 10 50 4 4
5 60 1 2 10 60 3 5
5 40 2 1 10 40 5 3
5 80 0 3 10 70 2 6
5 20 3 0 10 30 6 2
6 50 2 2 10 80 1 7
6 67 1 3 10 20 7 1
6 33 3 1 10 90 0 8
6 83 0 4 10 10 8 0
6 17 4 0 11 55 4 5
7 57 2 3 11 45 5 4
7 43 3 2 11 64 3 6
7 71 1 4 11 36 6 3
7 29 4 1 11 73 2 7
7 86 0 5 11 27 7 2
7 14 5 0 11 82 1 8
8 50 3 3 11 18 8 1
8 63 2 4 11 91 0 9
8 38 4 2 11 9 9 0
8 75 1 5 12 50 5 5
8 25 5 1 12 58 4 6
8 88 0 6 12 42 6 4
8 13 6 0 12 67 3 7
9 56 3 4 12 33 7 3
9 44 4 3 12 75 2 8
9 67 2 5 12 25 8 2

Rev. C | Page 33 of 56
AD9510 Data Sheet
Address 0x48 to Address 0x48 to
Address 0x56 Address 0x56
Divide Ratio Duty Cycle (%) LO[7:4] HI[3:0] Divide Ratio Duty Cycle (%) LO[7:4] HI[3:0]
12 83 1 9 16 75 3 B
12 17 9 1 16 25 B 3
12 92 0 A 16 81 2 C
12 8 A 0 16 19 C 2
13 54 5 6 16 88 1 D
13 46 6 5 16 13 D 1
13 62 4 7 16 94 0 E
13 38 7 4 16 6 E 0
13 69 3 8 17 53 7 8
13 31 8 3 17 47 8 7
13 77 2 9 17 59 6 9
13 23 9 2 17 41 9 6
13 85 1 A 17 65 5 A
13 15 A 1 17 35 A 5
13 92 0 B 17 71 4 B
13 8 B 0 17 29 B 4
14 50 6 6 17 76 3 C
14 57 5 7 17 24 C 3
14 43 7 5 17 82 2 D
14 64 4 8 17 18 D 2
14 36 8 4 17 88 1 E
14 71 3 9 17 12 E 1
14 29 9 3 17 94 0 F
14 79 2 A 17 6 F 0
14 21 A 2 18 50 8 8
14 86 1 B 18 56 7 9
14 14 B 1 18 44 9 7
14 93 0 C 18 61 6 A
14 7 C 0 18 39 A 6
15 53 6 7 18 67 5 B
15 47 7 6 18 33 B 5
15 60 5 8 18 72 4 C
15 40 8 5 18 28 C 4
15 67 4 9 18 78 3 D
15 33 9 4 18 22 D 3
15 73 3 A 18 83 2 E
15 27 A 3 18 17 E 2
15 80 2 B 18 89 1 F
15 20 B 2 18 11 F 1
15 87 1 C 19 53 8 9
15 13 C 1 19 47 9 8
15 93 0 D 19 58 7 A
15 7 D 0 19 42 A 7
16 50 7 7 19 63 6 B
16 56 6 8 19 37 B 6
16 44 8 6 19 68 5 C
16 63 5 9 19 32 C 5
16 38 9 5 19 74 4 D
16 69 4 A 19 26 D 4
16 31 A 4 19 79 3 E

Rev. C | Page 34 of 56
Data Sheet AD9510
Address 0x48 to Address 0x48 to
Address 0x56 Address 0x56
Divide Ratio Duty Cycle (%) LO[7:4] HI[3:0] Divide Ratio Duty Cycle (%) LO[7:4] HI[3:0]
19 21 E 3 23 30 F 6
19 84 2 F 24 50 B B
19 16 F 2 24 54 A C
20 50 9 9 24 46 C A
20 55 8 A 24 58 9 D
20 45 A 8 24 42 D 9
20 60 7 B 24 63 8 E
20 40 B 7 24 38 E 8
20 65 6 C 24 67 7 F
20 35 C 6 24 33 F 7
20 70 5 D 25 52 B C
20 30 D 5 25 48 C B
20 75 4 E 25 56 A D
20 25 E 4 25 44 D A
20 80 3 F 25 60 9 E
20 20 F 3 25 40 E 9
21 52 9 A 25 64 8 F
21 48 A 9 25 36 F 8
21 57 8 B 26 50 C C
21 43 B 8 26 54 B D
21 62 7 C 26 46 D B
21 38 C 7 26 58 A E
21 67 6 D 26 42 E A
21 33 D 6 26 62 9 F
21 71 5 E 26 38 F 9
21 29 E 5 27 52 C D
21 76 4 F 27 48 D C
21 24 F 4 27 56 B E
22 50 A A 27 44 E B
22 55 9 B 27 59 A F
22 45 B 9 27 41 F A
22 59 8 C 28 50 D D
22 41 C 8 28 54 C E
22 64 7 D 28 46 E C
22 36 D 7 28 57 B F
22 68 6 E 28 43 F B
22 32 E 6 29 52 D E
22 73 5 F 29 48 E D
22 27 F 5 29 55 C F
23 52 A B 29 45 F C
23 48 B A 30 50 E E
23 57 9 C 30 53 D F
23 43 C 9 30 47 F D
23 61 8 D 31 52 E F
23 39 D 8 31 48 F E
23 65 7 E 32 50 F F
23 35 E 7
23 70 6 F

Rev. C | Page 35 of 56
AD9510 Data Sheet
Divider Phase Offset Table 19. Phase Offset—Start H/L Bit
The phase of each output can be selected, depending on the Phase Offset
(Fast Clock Address 0x49 to Address 0x57
divide ratio chosen. This is selected by writing the appropriate
Rising Edges) Phase Offset[3:0] Start H/L[4]
values to the registers which set the phase and start high/low bit
0 0 0
for each output. These are the odd numbered registers from
1 1 0
Register 0x49 to Register 0x57. Each divider has a 4-bit phase
2 2 0
offset [3:0] and a start high or low bit [4].
3 3 0
Following a sync pulse, the phase offset word determines how 4 4 0
many fast clock (CLK1 or CLK2) cycles to wait before initiating 5 5 0
a clock output edge. The Start H/L bit determines if the divider 6 6 0
output starts low or high. By giving each divider a different 7 7 0
phase offset, output-to-output delays can be set in increments of 8 8 0
the fast clock period, tCLK. 9 9 0
Figure 39 shows four dividers, each set for DIV = 4, 50% duty 10 10 0
cycle. By incrementing the phase offset from 0 to 3, each output 11 11 0
is offset from the initial edge by a multiple of tCLK. 12 12 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 13 13 0
CLOCK INPUT
CLK 14 14 0
tCLK 15 15 0
DIVIDER OUTPUTS
DIV = 4, DUTY = 50%
START = 0, 16 0 1
PHASE = 0
17 1 1
START = 0, 18 2 1
PHASE = 1
19 3 1
START = 0, 20 4 1
PHASE = 2
21 5 1
START = 0,
PHASE = 3 22 6 1
tCLK 23 7 1
2 × tCLK
24 8 1
05046-035

3 × tCLK
25 9 1
Figure 39. Phase Offset—All Dividers Set for DIV = 4, Phase Set from 0 to 3 26 10 1
For example: 27 11 1
28 12 1
CLK1 = 491.52 MHz
29 13 1
tCLK1 = 1/491.52 = 2.0345 ns 30 14 1
For DIV = 4 31 15 1

Phase Offset 0 = 0 ns The resolution of the phase offset is set by the fast clock period
(tCLK) at CLK1 or CLK2. As a result, every divide ratio does not
Phase Offset 1 = 2.0345 ns
have 32 unique phase offsets available. For any divide ratio, the
Phase Offset 2 = 4.069 ns number of unique phase offsets is numerically equal to the
Phase Offset 3 = 6.104 ns divide ratio (see Table 19):
The four outputs can also be described as: DIV = 4
OUT1 = 0° Unique Phase Offsets Are Phase = 0, 1, 2, 3
OUT2 = 90° DIV= 7
OUT3 = 180° Unique Phase Offsets Are Phase = 0, 1, 2, 3, 4, 5, 6
OUT4 = 270° DIV = 18
Setting the phase offset to Phase = 4 results in the same relative Unique Phase Offsets Are Phase = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
phase as the first channel, Phase = 0° or 360°. 10, 11, 12, 13, 14, 15, 16, 17
In general, by combining the 4-bit phase offset and the Start
H/L bit, there are 32 possible phase offset states (see Table 19).

Rev. C | Page 36 of 56
Data Sheet AD9510
Phase offsets can be related to degrees by calculating the phase Calculating the Delay
step for a particular divide ratio: The following values and equations are used to calculate the
Phase Step = 360°/(Divide Ratio) = 360°/DIV delay of the delay block.
Using some of the same examples, Value of Ramp Current Control Bits (Register 0x35 or
DIV = 4 Register 0x39 [2:0]) = IRAMP_BITS

Phase Step = 360°/4 = 90° IRAMP (µA) = 200 × (IRAMP_BITS + 1)

Unique Phase Offsets in Degrees Are Phase = 0°, 90°, No. of Caps = No. of 0s + 1 in Ramp Control Capacitor
180°, 270° (Register 0x35 or Register 0x39 [5:3]), that is, 101 = 1 + 1 =
2; 110 = 2; 100 = 2 + 1 = 3; 001 = 2 + 1 = 3; 111 = 0 + 1 = 1)
DIV = 7
DELAY_RANGE (ns) = 200 × ((No. of Caps + 3)/(IRAMP)) ×
Phase Step = 360°/7 = 51.43° 1.3286
Unique Phase Offsets in Degrees Are Phase = 0°, 51.43°,
 No.of Caps − 1 
102.86°, 154.29°, 205.71°, 257.15°, 308.57° Offset (ns ) = 0.34 + (1600 − I RAMP )× 10 −4 +  ×6

 I RAMP 
DELAY BLOCK
OUT5 and OUT6 (LVDS/CMOS) include an analog delay element DELAY_FULL_SCALE (ns) = DELAY_RANGE × (24/31) +
that can be programmed (from Register 0x34 to Register 0x3A) Offset
to give variable time delays (Δt) in the clock signal passing
FINE_ADJ = Value of Delay Fine Adjust (Register 0x36 or
through that output.
Register 0x3A[5:1]), that is, 11000 = 24
CLOCK INPUT
Delay (ns) = Offset + DELAY_RANGE × FINE_ADJ × (1/31)

÷N
OUTPUTS
ØSELECT
LVDS The AD9510 offers three different output level choices:
MUX

OUT5 LVPECL, LVDS, and CMOS. OUT0 to OUT3 are LVPECL only.
OUT6 ONLY ΔT OUTPUT
CMOS
DRIVER OUT4 to OUT7 can be selected as either LVDS or CMOS. Each
FINE DELAY ADJUST
output can be enabled or turned off as needed to save power.
05046-036

(25 STEPS)
FULL-SCALE: 1ns TO 8ns
The simplified equivalent circuit of the LVPECL outputs is
Figure 40. Analog Delay (OUT5 and OUT6)
shown in Figure 41.
The amount of delay that can be used is determined by the 3.3V
frequency of the clock being delayed. The amount of delay can
approach one-half cycle of the clock period. For example, for a
10 MHz clock, the delay can extend to the full 8 ns maximum of
which the delay element is capable. However, for a 100 MHz OUT
clock (with 50% duty cycle), the maximum delay is less than
5 ns (or half of the period). OUTB

OUT5 and OUT6 allow a full-scale delay in the range 1 ns to

8 ns. The full-scale delay is selected by choosing a combination
of ramp current and the number of capacitors by writing the
05046-037

appropriate values into Register 0x35 and Register 0x39. There GND

are 25 fine delay settings (Register 0x36 and Register 0x3A = Figure 41. LVPECL Output Simplified Equivalent Circuit
00000b to 11000b) for each full scale, set by Register 0x36 and
Register 0x3A.
3.5mA
This path adds some jitter greater than that specified for the
nondelay outputs. Therefore, use the delay function primarily
for clocking digital chips, such as FPGA, ASIC, DUC, and
OUT
DDC, rather than for data converters. The jitter is higher for OUTB
long full scales (~8 ns). This is because the delay block uses a
ramp and trip points to create the variable delay. A longer ramp
means more noise can be introduced.
05046-038

3.5mA

Figure 42. LVDS Output Simplified Equivalent Circuit

Rev. C | Page 37 of 56
AD9510 Data Sheet
POWER-DOWN MODES [00], it is possible for a low impedance load on that LVPECL
Chip Power-Down or Sleep Mode—PDB output to draw significant current during this power-down. If
the LVPECL power-down mode is set to [11], the LVPECL
The PDB chip power-down turns off most of the functions and
output is not protected from reverse bias and can be damaged
currents in the AD9510. When the PDB mode is enabled, a chip
under certain termination conditions.
power-down is activated by taking the FUNCTION pin to a logic
low level. The chip remains in this power-down state until PDB When combined with the PLL power-down, this mode results in
is brought back to logic high. When woken up, the AD9510 returns the lowest possible power-down current for the AD9510.
to the settings programmed into its registers prior to the power- Individual Clock Output Power-Down
down, unless the registers are changed by new programming Any of the eight clock distribution outputs can be powered down
while the PDB mode is active. individually by writing to the appropriate registers via the SCP.
The PDB power-down mode shuts down the currents on the The register map details the individual power-down settings for
chip, except the bias current necessary to maintain the LVPECL each output. The LVDS/CMOS outputs can be powered down,
outputs in a safe shutdown mode. This is needed to protect the regardless of their output load configuration.
LVPECL output circuitry from damage that can be caused by The LVPECL outputs have multiple power-down modes (see
certain termination and load configurations when tristated. Register Address 3C, Register Address 3D, Register Address 3E,
Because this is not a complete power-down, it is also called and Register Address 3F in Table 25). These give some flexibility in
sleep mode. dealing with various output termination conditions. When the
When the AD9510 is in a PDB power-down or sleep mode, the mode is set to [10], the LVPECL output is protected from reverse
chip is in the following state: bias to 2 VBE + 1 V. If the mode is set to [11], the LVPECL output
• The PLL is off (asynchronous power-down). is not protected from reverse bias and can be damaged under
certain termination conditions. This setting also affects the
• All clocks and sync circuits are off.
operation when the distribution block is powered down with
• All dividers are off.
Register 0x58[3] = 1b (see the Distribution Power-Down section).
• All LVDS/CMOS outputs are off.
• All LVPECL outputs are in safe off mode. Individual Circuit Block Power-Down
• The serial control port is active, and the chip responds to Many of the AD9510 circuit blocks (CLK1, CLK2, REFIN, and
commands. so on) can be powered down individually. This gives flexibility
in configuring the part for power savings whenever certain chip
If the AD9510 clock outputs must be synchronized to each
functions are not needed.
other, a SYNC (see the Single-Chip Synchronization section) is
required upon exiting power-down mode. RESET MODES
PLL Power-Down The AD9510 has several ways to force the chip into a reset
condition.
The PLL section of the AD9510 can be selectively powered
down. There are three PLL power-down modes, set by the Power-On Reset—Start-Up Conditions when VS is
values in Register 0x0A[1:0], as shown in Table 20. Applied
A power-on reset (POR) is issued when the VS power supply is
Table 20. Register 0x0A: PLL Power-Down turned on. This initializes the chip to the power-on conditions
[1] [0] Mode that are determined by the default register settings. These are
0 0 Normal Operation indicated in the default value column of Table 24.
0 1 Asynchronous Power-Down
1 0 Normal Operation
Asynchronous Reset via the FUNCTION Pin
1 1 Synchronous Power-Down As mentioned in the FUNCTION Pin section, a hard reset,
RESETB: Register 0x58[6:5] = 00b (Default), restores the chip
In asynchronous power-down mode, the device powers down to the default settings.
as soon as the registers are updated.
Soft Reset via the Serial Port
In synchronous power-down mode, the PLL power-down is The serial control port allows a soft reset by writing to
gated by the charge pump to prevent unwanted frequency Register 0x00[5] = 1b. When this bit is set, the chip executes
jumps. The device goes into power-down on the occurrence of a soft reset. This restores the default values to the internal
the next charge pump event after the registers are updated. registers, except for Register 0x00 itself.
Distribution Power-Down This bit is not self-clearing. The bit must be written to
The distribution section can be powered down by writing to Register 0x00[5] = 0b in order for the operation of the part
Register 0x58[3] = 1. This turns off the bias to the distribution to continue.
section. If the LVPECL power-down mode is normal operation
Rev. C | Page 38 of 56
Data Sheet AD9510
SINGLE-CHIP SYNCHRONIZATION Multichip synchronization is enabled by writing
SYNCB—Hardware SYNC Register 0x58[0] = 1 on the slave AD9510. When this bit is set,
the STATUS pin becomes the output for the SYNC signal. A low
The AD9510 clocks can be synchronized to each other at any
signal indicates an in-sync condition, and a high indicates an
time. The outputs of the clocks are forced into a known state
out-of-sync condition.
with respect to each other and then allowed to continue clocking
from that state in synchronicity. Before a synchronization is Register 0x58[1] selects the number of fast clock cycles that are
done, the FUNCTION Pin must be set to act as the SYNCB: the maximum separation of the slow clock edges that are con-
Register 0x58[6:5] = 01b input (Register 0x58[6:5] = 01b). sidered synchronized. When Register 0x58[1] = 0 (default), the
Synchronization is done by forcing the FUNCTION pin low, slow clock edges must be coincident within 1 to 1.5 high speed
creating a SYNCB signal and then releasing it. clock cycles. If the coincidence of the slow clock edges is closer
than this amount, the SYNC flag stays low. If the coincidence of
See the SYNCB: Register 0x58[6:5] = 01b section for a more
the slow clock edges is greater than this amount, the SYNC flag
detailed description of what happens when the SYNCB:
is set high. When Register 0x58[1] = 1b, the amount of coincidence
Register 0x58[6:5] = 01b signal is issued.
required is 0.5 fast clock cycles to 1 fast clock cycles.
Soft SYNC—Register 0x58[2]
Whenever the SYNC flag is set high, indicating an out-of-sync
A soft SYNC can be issued by means of a bit in Registers 0x58[2]. condition, a SYNCB signal applied simultaneously at the
This soft SYNC works the same as the SYNCB, except that the FUNCTION pins of both AD9510s brings the slow clocks into
polarity is reversed. A 1 written to this bit forces the clock outputs synchronization.
into a known state with respect to each other. When a 0 is
subsequently written to this bit, the clock outputs continue AD9510
MASTER
clocking from that state in synchronicity. FAST CLOCK OUTN
<1GHz
MULTICHIP SYNCHRONIZATION FUNCTION
SLOW CLOCK OUTM
(SYNCB)
The AD9510 provides a means of synchronizing two or more <250MHz FSYNC

AD9510s. This is not an active synchronization; it requires user

monitoring and action. The arrangement of two AD9510s to be SYNCB
CLK2 REFIN
synchronized is shown in Figure 43.
AD9510
Synchronization of two or more AD9510s requires a fast clock SLAVE SLOW FSYNC
CLOCK
and a slow clock. The fast clock can be up to 1 GHz and can be <250MHz OUTY
FAST CLOCK
the clock driving the master AD9510 CLK1 input or one of the CLK1 <1GHz
SYNC
DETECT
outputs of the master. The fast clock acts as the input to the

05046-039
distribution section of the slave AD9510 and is connected to its FUNCTION STATUS
(SYNCB) (SYNC)
CLK1 input. The PLL can be used on the master, but the slave
PLL is not used. Figure 43. Multichip Synchronization

The slow clock is the clock that is synchronized across the two
chips. This clock must be no faster than one-fourth of the fast
clock, and no greater than 250 MHz. The slow clock is taken
from one of the outputs of the master AD9510 and acts as the
REFIN (or CLK2) input to the slave AD9510. One of the outputs
of the slave must provide this same frequency back to the CLK2
(or REFIN) input of the slave.

Rev. C | Page 39 of 56
AD9510 Data Sheet

SERIAL CONTROL PORT

The AD9510 serial control port is a flexible, synchronous, serial set to 00, 01, or 10, see Table 21). In these modes, CSB can
communications port that allows an easy interface with many temporarily return high on any byte boundary, allowing time
industry-standard microcontrollers and microprocessors. The for the system controller to process the next byte. CSB can go
AD9510 serial control port is compatible with most synchronous high on byte boundaries only and can go high during either
transfer formats, including both the Motorola SPI® and Intel® part (instruction or data) of the transfer. During this period, the
SSR® protocols. The serial control port allows read/write access serial control port state machine enters a wait state until all data
to all registers that configure the AD9510. Single or multiple is sent. If the system controller decides to abort the transfer
byte transfers are supported, as well as MSB first or LSB first before all of the data is sent, the state machine must be reset by
transfer formats. The AD9510 serial control port can be either completing the remaining transfer or by returning the
configured for a single bidirectional input/output pin (SDIO CSB low for at least one complete SCLK cycle (but less than
only) or for two unidirectional input/output pins (SDIO/SDO). eight SCLK cycles). Raising the CSB on a nonbyte boundary
terminates the serial transfer and flushes the buffer.
SERIAL CONTROL PORT PIN DESCRIPTIONS
SCLK (serial clock) is the serial shift clock. This pin is an input. In the streaming mode (W1:W0 = 11b), any number of data bytes
SCLK is used to synchronize serial control port reads and can be transferred in a continuous stream. The register address
writes. Write data bits are registered on the rising edge of this is automatically incremented or decremented (see the MSB/LSB
clock, and read data bits are registered on the falling edge. This First Transfers section). CSB must be raised at the end of the
pin is internally pulled down by a 30 kΩ resistor to ground. last byte to be transferred, thereby ending the stream mode.

SDIO (serial data input/output) is a dual-purpose pin and acts Communication Cycle—Instruction Plus Data
as either an input only or as both an input/output. The AD9510 There are two parts to a communication cycle with the AD9510.
defaults to two unidirectional pins for input/output, with SDIO The first writes a 16-bit instruction word into the AD9510,
used as an input, and SDO as an output. Alternatively, SDIO coincident with the first 16 SCLK rising edges. The instruction
can be used as a bidirectional input/output pin by writing to the word provides the AD9510 serial control port with information
SDO enable register at Register 0x00[7] = 1b. regarding the data transfer, which is the second part of the
communication cycle. The instruction word defines whether
SDO (serial data out) is used only in the unidirectional input/
the upcoming data transfer is a read or a write, the number of
output mode (Register 0x00[7] = 0, default) as a separate output
bytes in the data transfer, and the starting register address for
pin for reading back data. The AD9510 defaults to this input/
the first byte of the data transfer.
output mode. Bidirectional input/output mode (using SDIO as
both input and output) can be enabled by writing to the SDO Write
enable register at Register 0x00[7] = 1. If the instruction word is for a write operation (I15 = 0b), the
CSB (chip select bar) is an active low control that gates the read second part is the transfer of data into the serial control port
and write cycles. When CSB is high, SDO and SDIO are in a buffer of the AD9510. The length of the transfer (1, 2, 3 bytes, or
high impedance state. This pin is internally pulled down by a streaming mode) is indicated by 2 bits (W1:W0) in the instruction
30 kΩ resistor to ground. Do not leave it unconnected or tied byte. CSB can be raised after each sequence of 8 bits to stall the
low. See the General Operation of Serial Control Port section bus (except after the last byte, where it ends the cycle). When
on the use of the CSB in a communication cycle. the bus is stalled, the serial transfer resumes when CSB is lowered.
Stalling on nonbyte boundaries resets the serial control port.
SCLK (PIN 18)
SDIO (PIN 19) AD9510 Since data is written into a serial control port buffer area, not
SERIAL
SDO (PIN 20)
05046-017

CONTROL
PORT
directly into the actual control registers of the AD9510, an addi-
CSB (PIN 21)
tional operation is needed to transfer the serial control port
Figure 44. Serial Control Port buffer contents to the actual control registers of the AD9510,
GENERAL OPERATION OF SERIAL CONTROL PORT thereby causing them to take effect. This update command
consists of writing to Register 0x5A[0] = 1b. This update bit is
Framing a Communication Cycle with CSB
self-clearing (it is not required to write 0 to it to clear it). Since
Each communications cycle (a write or a read operation) is any number of bytes of data can be changed before issuing an
gated by the CSB line. CSB must be brought low to initiate a update command, the update simultaneously enables all register
communication cycle. CSB must be brought high at the comple- changes since any previous update.
tion of a communication cycle (see Figure 52). If CSB is not
brought high at the end of each write or read cycle (on a byte Phase offsets or divider synchronization do not become
boundary), the last byte is not loaded into the register buffer. effective until a SYNC is issued (see the Single-Chip
Synchronization section).
CSB stall high is supported in modes where three or fewer bytes
of data (plus instruction data) are transferred (W1:W0 must be
Rev. C | Page 40 of 56
Data Sheet AD9510
Read A12:A0: These 13 bits select the address within the register map
If the instruction word is for a read operation (I15 = 1b), the that is written to or read from during the data transfer portion
next N × 8 SCLK cycles clock out the data from the address of the communications cycle. The AD9510 does not use all of
specified in the instruction word, where N is 1 to 4 as determined the 13-bit address space. Only Bits[A6:A0] are needed to cover
by W1:W0. The readback data is valid on the falling edge of SCLK. the range of the Address 0x5A registers used by the AD9510.
Bits[A12:A7] must always be 0b. For multibyte transfers, this
The default mode of the AD9510 serial control port is unidirec-
address is the starting byte address. In MSB first mode,
tional mode; therefore, the requested data appears on the SDO
subsequent bytes increment the address.
pin. It is possible to set the AD9510 to bidirectional mode by
writing the SDO enable register at Register 0x00[7] = 1b. In MSB/LSB FIRST TRANSFERS
bidirectional mode, the readback data appears on the SDIO pin. The AD9510 instruction word and byte data can be MSB first or
A readback request reads the data that is in the serial control LSB first. The default for the AD9510 is MSB first. Set the LSB
port buffer area, not the active data in the actual control first mode by writing 1b to Register 0x00[6]. This takes effect
registers of the AD9510. immediately (since it only affects the operation of the serial
control port) and does not require that an update be executed.
Immediately after the LSB first bit is set, all serial control port
CONTROL REGISTERS
REGISTER BUFFERS

operations are changed to LSB first order.

SCLK
SDIO
When MSB first mode is active, the instruction and data bytes
SDO must be written from MSB to LSB. Multibyte data transfers in
CSB UPDATE MSB first format start with an instruction byte that includes the
REGISTERS
0x5A[0] register address of the most significant data byte. Subsequent
SERIAL
05046-018

CONTROL AD9510 data bytes must follow in order from high address to low
PORT CORE
address. In MSB first mode, the serial control port internal
Figure 45. Relationship Between Serial Control Port Register Buffers and
Control Registers of the AD9510 address generator decrements for each data byte of the
multibyte transfer cycle.
The AD9510 uses Address 0x00 to Address 0x5A. Although the
AD9510 serial control port allows both 8-bit and 16-bit instruc- When LSB_FIRST = 1b (LSB first), the instruction and data bytes
tions, the 8-bit instruction mode provides access to five address must be written from LSB to MSB. Multibyte data transfers in
bits (A4 to A0) only, which restricts its use to the address space LSB first format start with an instruction byte that includes the
Address 0x00 to Address 0x01. The AD9510 defaults to 16-bit register address of the least significant data byte followed by mul-
instruction mode on power-up. The 8-bit instruction mode tiple data bytes. The serial control port internal byte address
(although defined for this serial control port) is not useful for the generator increments for each byte of the multibyte transfer cycle.
AD9510; therefore, it is not discussed further in this data sheet. The AD9510 serial control port register address decrements
from the register address just written toward Address 0x0000
THE INSTRUCTION WORD (16 BITS)
for multibyte input/output operations if the MSB first mode is
The MSB of the instruction word is R/W, which indicates whether active (default). If the LSB first mode is active, the serial control
the instruction is a read or a write. The next two bits, W1:W0, port register address increments from the address just written
indicate the length of the transfer in bytes. The final 13 bits are toward Address 0x1FFF for multibyte input/output operations.
the address (A12:A0) at which to begin the read or write operation.
Unused addresses are not skipped during multibyte input/output
For a write, the instruction word is followed by the number of operations; therefore, it is important to avoid multibyte input/
bytes of data indicated by Bits W1:W0, which is interpreted output operations that would include these addresses.
according to Table 21.

Table 21. Byte Transfer Count

W1 W0 Bytes to Transfer
0 0 1
0 1 2
1 0 3
1 1 Streaming mode

Rev. C | Page 41 of 56
AD9510 Data Sheet
Table 22. Serial Control Port, 16-Bit Instruction Word, MSB First
MSB LSB
I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0
R/W W1 W0 A12 = 0 A11 = 0 A10 = 0 A9 = 0 A8 = 0 A7 = 0 A6 A5 A4 A3 A2 A1 A0

CSB

SCLK DON'T CARE DON'T CARE

SDIO DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 DON'T CARE

05046-019
16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N – 1) DATA

Figure 46. Serial Control Port Write—MSB First, 16-Bit Instruction, 2 Bytes Data

CSB

SCLK

DON'T CARE DON'T CARE

SDIO R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

SDO DON'T CARE D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

05046-020
16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N – 1) DATA REGISTER (N – 2) DATA REGISTER (N – 3) DATA DON'T
CARE

Figure 47. Serial Control Port Read—MSB First, 16-Bit Instruction, 4 Bytes Data

tDS tHI
tS tCLK tH
tDH
CSB tLO

SCLK DON'T CARE DON'T CARE

SDIO DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 D4 D3 D2 D1 D0 DON'T CARE

05046-021
Figure 48. Serial Control Port Write−MSB First, 16-Bit Instruction, Timing Measurements

CSB

SCLK

tDV
05046-022

SDIO
SDO DATA BIT N DATA BIT N– 1

Figure 49. Timing Diagram for Serial Control Port Register Read

CSB

SCLK DON'T CARE DON'T CARE

SDIO DON'T CARE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 W0 W1 R/W D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 DON'T CARE

05046-023

16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N + 1) DATA

Figure 50. Serial Control Port Write—LSB First, 16-Bit Instruction, 2 Bytes Data

Rev. C | Page 42 of 56
Data Sheet AD9510
tS tH

CSB

tCLK
tHI tLO

tDS
SCLK

tDH

05046-040
SDIO BI N BI N + 1

Figure 51. Serial Control Port Timing—Write

Table 23. Serial Control Port Timing

Parameter Description
tDS Setup time between data and rising edge of SCLK
tDH Hold time between data and rising edge of SCLK
tCLK Period of the clock
tS Setup time between CSB and SCLK
tH Hold time between CSB and SCLK
tHI Minimum period that SCLK must be in a logic high state
tLO Minimum period that SCLK must be in a logic low state

CSB TOGGLE INDICATES

CYCLE COMPLETE

CSB tPWH

16 INSTRUCTION BITS + 8 DATA BITS 16 INSTRUCTION BITS + 8 DATA BITS

SCLK

SDIO COMMUNICATION CYCLE 1 COMMUNICATION CYCLE 2

05046-067

TIMING DIAGRAM FOR TWO SUCCESSIVE CUMMUNICATION CYCLES. NOTE THAT CSB MUST
BE TOGGLED HIGH AND THEN LOW AT THE COMPLETION OF A COMMUNICATION CYCLE.
Figure 52. Use of CSB to Define Communications Cycle

Rev. C | Page 43 of 56
AD9510 Data Sheet

REGISTER MAP AND DESCRIPTION

SUMMARY TABLE
Table 24. AD9510 Register Map
Def.
Addr Bit 0 Value
(Hex) Parameter Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Notes
00 Serial SDO inactive LSB_ Soft Long Not used 10
control port (bidirectional FIRST reset instruction
configuration mode)
01 Not used
02 Not used
03 Not used
PLL PLL starts
in power-
down
04 A counter Not used 6-Bit A counter[5:0] 00 N divider
(A)
05 B counter Not used 13-Bit B counter, Bits[12:8], MSB[4:0] 00 N divider
(B)
06 B counter 13-Bit B counter, Bits[7:0], LSB[7:0] 00 N divider
(B)
07 PLL 1 Not used LOR Not used LOR Not used 00
LOCK_DEL[6:5] enable
08 PLL 2 Not used PFD PLL mux select[5:2] signal on STATUS pin CP mode[1:0] 00
polarity
09 PLL 3 Not used CP current[6:4] Not Reset R Reset N Reset All 00
used counter counter counters
0A PLL 4 Not used B Not Prescaler P[4:2] Power-down[1:0] 01 N divider
bypass used (P)
0B R divider Not used 14-Bit R divider, Bits[13:8], MSB[5:0] 00 R divider
0C R divider 14-Bit R divider, Bits[13:8], MSB[7:0] 00 R divider
0D PLL 5 Not used Digital Digital Not used Antibacklash 00
lock lock pulse width[1:0]
det. det.
enable window
0E33 Not used
Fine delay Fine delays
adjust bypassed
34 Delay Not used Bypass 01 Bypass
Bypass 5 delay
35 Delay Full- Not used Ramp capacitor[5:3] Ramp current [2:0] 00 Max. delay
Scale 5 full-scale
36 Delay Fine Not used 5-bit fine delay[5:1] (00000b to 11000b) Must be 00 Min. delay
Adjust 5 0 value
37 Not used 04
38 Delay Not used Bypass 01 Bypass
Bypass 6 delay
39 Delay Full- Not used Ramp capacitor[5:3] Ramp current[2:0] 00 Max. delay
Scale 6 full-scale
3A Delay Fine Not used 5-bit fine delay[5:1] (00000b to 11000b) Not 00 Min. delay
Adjust 6 used value
3B Not used 04
Outputs
3C LVPECL OUT0 Not used Output level[3:2] Power-down[1:0] 0A Off
3D LVPECL OUT1 Not used Output level[3:2] Power-down[1:0] 08 On

Rev. C | Page 44 of 56
Data Sheet AD9510
Def.
Addr Bit 0 Value
(Hex) Parameter Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Notes
3E LVPECL OUT2 Not used Output level[3:2] Power-down[1:0] 08 On
3F LVPECL OUT3 Not used Output level[3:2] Power-down[1:0] 08 On
40 LVDS_CMOS Not used CMOS Logic Output level[2:1] Output 02 LVDS, on
OUT4 inverted select power
driver on
41 LVDS_CMOS Not used CMOS Logic Output level[2:1] Output 02 LVDS, on
OUT5 inverted select power
driver on
42 LVDS_CMOS Not used CMOS Logic Output level[2:1] Output 03 LVDS, off
OUT6 inverted select power
driver on
43 LVDS_CMOS Not used CMOS Logic Output level[2:1] Output 03 LVDS, off
OUT7 inverted select power
driver on
44 Not used
CLK1 and Input
CLK2 receivers
45 Clocks select, Not used CLKs in REFIN PD CLK to CLK2 CLK1 Select 01 All clocks
power-down PD PLL PD PD CLK IN on, select
(PD) options PD CLK1
46, Not used
47
Dividers
48 Divider 0 Low cycles[7:4] High cycles[3:0] 00 Divide by 2
49 Divider 0 Bypass No sync Force Start H/L Phase offset[3:0] 00 Phase = 0
4A Divider 1 Low cycles[7:4] High cycles[3:0] 00 Divide by 2
4B Divider 1 Bypass No sync Force Start H/L Phase offset[3:0] 00 Phase = 0
4C Divider 2 Low cycles[7:4] High cycles[3:0] 11 Divide by 4
4D Divider 2 Bypass No sync Force Start H/L Phase offset[3:0] 00 Phase = 0
4E Divider 3 Low cycles[7:4] High cycles[3:0] 33 Divide by 8
4F Divider 3 Bypass No sync Force Start H/L Phase offset[3:0] 00 Phase = 0
50 Divider 4 Low cycles[7:4] High cycles[3:0] 00 Divide by 2
51 Divider 4 Bypass No sync Force Start H/L Phase offset[3:0] 00 Phase = 0
52 Divider 5 Low cycles[7:4] High cycles[3:0] 11 Divide by 4
53 Divider 5 Bypass No sync Force Start H/L Phase offset[3:0] 00 Phase = 0
54 Divider 6 Low cycles[7:4] High cycles[3:0] 00 Divide by 2

55 Divider 6 Bypass No sync Force Start H/L Phase offset[3:0] 00 Phase = 0

56 Divider 7 Low cycles[7:4] High cycles[3:0] 00 Divide by 2
57 Divider 7 Bypass No sync Force Start H/L Phase offset[3:0] 00 Phase = 0
Function
58 FUNCTION Not used Set FUNCTION Pin PD sync PD all Sync Sync Sync 00 FUNCTION
Pin and sync ref. reg. select enable pin =
RESETB
59 Not used
5A Update Not used Update 00 Self-
registers registers clearing bit
END

Rev. C | Page 45 of 56
AD9510 Data Sheet
REGISTER MAP DESCRIPTION
Table 25 lists the AD9510 control registers by hexadecimal address. A specific bit or range of bits within a register is indicated by square
brackets. For example, [3] refers to Bit 3, while [5:2] refers to the range of bits from Bit 5 through Bit 2. Table 25 describes the
functionality of the control registers on a bit-by-bit basis. For a more concise (but less descriptive) table, see Table 24.

Table 25. AD9510 Register Descriptions

Reg.
Addr.
(Hex) Bit(s) Name Description
Serial control port Any changes to this register take effect immediately. Register 0x5A[0] update registers does not have to
configuration be written.
00 [3:0] Not used.
00 [4] Long instruction When this bit is set (1), the instruction phase is 16 bits. When this bit is clear (0), the instruction phase is
8 bits. The default, and only, mode for this part is long instruction (default = 1b).
00 [5] Soft reset When this bit is set (1), the chip executes a soft reset, restoring default values to the internal registers, except for
this register, Register 0x00. This bit is not self-clearing. A clear (0) must be written to it to clear it.
00 [6] LSB_FIRST When this bit is set (1), the input and output data is oriented as LSB first. Additionally, register addressing
increments. If this bit is clear (0), data is oriented as MSB first and register addressing decrements
(default = 0b, MSB first)
00 [7] SDO inactive When set (1), the SDO pin is tristate and all read data goes to the SDIO pin. When clear (0), the SDO is
(bidirectional active (unidirectional mode) (default = 0b).
mode)
Not used
01 [7:0] Not used.
02 [7:0] Not used.
03 [7:0] Not used.
PLL settings
04 [5:0] A counter 6-bit A counter[5:0].
04 [7:6] Not used.
05 [4:0] B counter MSBs 13-bit B counter MSB[12:8].
05 [7:5] Not used.
06 [7:0] B counter LSBs 13-bit B counter LSB[7:0].
07 [1:0] Not used.
07 [2] LOR enable 1 = enables the loss of reference (LOR) function (default = 0b).
07 [4:3] Not used.
07 [6:5] LOR initial lock LOR initial lock detect delay. Once a lock detect is indicated, this is the number of phase frequency
detect delay detector (PFD) cycles that occur prior to turning on the LOR monitor.
[6] [5] LOR Initial Lock Detect Delay
0 0 3 PFD cycles (default)
0 1 6 PFD cycles
1 0 12 PFD cycles
1 1 24 PFD cycles
07 [7] Not used.
08 [1:0] Charge pump mode
[1] [0] Charge Pump Mode
0 0 Tristated (default)
0 1 Pump-up
1 0 Pump-down
1 1 Normal operation

Rev. C | Page 46 of 56
Data Sheet AD9510
Reg.
Addr.
(Hex) Bit(s) Name Description
08 [5:2] PLL mux control
[5] [4] [3] [2] MUXOUT—Signal on STATUS Pin
0 0 0 0 Off (signal goes low) (default)
0 0 0 1 Digital lock detect (active high)
0 0 1 0 N divider output
0 0 1 1 Digital lock detect (active low)
0 1 0 0 R divider output
0 1 0 1 Analog lock detect (N channel, open-drain)
0 1 1 0 A counter output
0 1 1 1 Prescaler output (NCLK)
1 0 0 0 PFD up pulse
1 0 0 1 PFD down pulse
1 0 1 0 Loss of reference (active high)
1 0 1 1 Tristate
1 1 0 0 Analog lock detect (P channel, open-drain)
1 1 0 1 Loss of reference or loss of lock (inverse of DLD) (active high)
1 1 1 0 Loss of reference or loss of lock (inverse of DLD) (active low)
1 1 1 1 Loss of reference (active low)
MUXOUT is the PLL portion of the STATUS output MUX.
08 [6] Phase frequency 0 = negative (default), 1 = positive.
detector (PFD)
polarity
08 [7] Not used.
09 [0] Reset all counters 0 = normal (default), 1 = reset R, A, and B counters.
09 [1] N-counter reset 0 = normal (default), 1 = reset A and B counters.
09 [2] R-counter reset 0 = normal (default), 1 = reset R counter.
09 [3] Not used.
09 [6:4] Charge pump (CP)
current setting
[6] [5] [4] ICP (mA)
0 0 0 0.60
0 0 1 1.2
0 1 0 1.8
0 1 1 2.4
1 0 0 3.0
1 0 1 3.6
1 1 0 4.2
1 1 1 4.8
Default = 000b.
These currents assume: CPRSET = 5.1 kΩ.
Actual current can be calculated by: CP_LSB = 3.06/CPRSET.
09 [7] Not used.
0A [1:0] PLL power-down 01 = Asynchronous power-down (default).
[1] [0] Mode
0 0 Normal operation
0 1 Asynchronous power-down
1 0 Normal operation
1 1 Synchronous power-down

Rev. C | Page 47 of 56
AD9510 Data Sheet
Reg.
Addr.
(Hex) Bit(s) Name Description
0A [4:2] Prescaler value
(P/P + 1)
[4] [3] [2] Mode Prescaler Mode
0 0 0 FD Divide by 1
0 0 1 FD Divide by 2
0 1 0 DM 2/3
0 1 1 DM 4/5
1 0 0 DM 8/9
1 0 1 DM 16/17
1 1 0 DM 32/33
1 1 1 FD Divide by 3
DM = dual modulus, FD = fixed divide.
0A [5] Not used.
0A [6] B counter bypass Only valid when operating the prescaler in fixed divide (FD) mode. When this bit is set, the B counter is
divided by 1. This allows the prescaler setting to determine the divide for the N divider.
0A [7] Not used.
0B [5:0] 14-bit reference R divider MSB[13:8].
counter, R MSBs
0C [7:0] 14-bit reference R divider MSB[7:0].
counter, R LSBs
0D [1:0] Antibacklash pulse
width
[1] [0] Antibacklash Pulse Width (ns)
0 0 1.3 (default)
0 1 2.9
1 0 6.0
1 1 1.3
0D [4:2] Not used
0D [5] Digital lock detect
window
[5] Digital Lock Detect Window (ns) Digital Lock Detect Loss of Lock Threshold (ns)
0 (default) 9.5 15
1 3.5 7
If the time difference of the rising edges at the inputs to the PFD are less than the lock detect window
time, the digital lock detect flag is set. The flag remains set until the time difference is greater than the
loss of lock threshold.
0D [6] Lock detect disable 0 = normal lock detect operation (default), 1 = disable lock detect.
0D [7] Not used.
Unused
0E33 Not used.
Fine delay adjust
[0] Delay control Delay block control bit.
34 OUT5 Bypasses delay block and powers it down (default = 1b).
38 OUT6
34 [7:1] Not used.
38

Rev. C | Page 48 of 56
Data Sheet AD9510
Reg.
Addr.
(Hex) Bit(s) Name Description
[2:0] Ramp current
35 OUT5 The slowest ramp (200 µA) sets the longest full scale of approximately 10 ns.
39 OUT6
[2] [1] [0] Ramp Current (µA)
0 0 0 200
0 0 1 400
0 1 0 600
0 1 1 800
1 0 0 1000
1 0 1 1200
1 1 0 1400
1 1 1 1600
[5:3] Ramp capacitor Selects the number of capacitors in ramp generation circuit.
35 OUT5 More capacitors → slower ramp.
39 OUT6
[5] [4] [3] Number of Capacitors
0 0 0 4 (default)
0 0 1 3
0 1 0 3
0 1 1 2
1 0 0 3
1 0 1 2
1 1 0 2
1 1 1 1
[5:1] Delay fine adjust
36 OUT5 Sets delay within full scale of the ramp; there are 25 steps.
3A OUT6 00000 → zero delay (default).
11000 → maximum delay.
3C [1:0] Power-down
LVPECL
3D OUT0
3E OUT1
3F OUT2
OUT3
Mode [1] [0] Description Output
On 0 0 Normal operation. On
PD1 0 1 Test only—do not use. Off
PD2 1 0 Safe power-down. Partial power-down; use if output Off
has load resistors.
PD3 1 1 Total power-down. Use only if output has no Off
load resistors.
3C [3:2] Output level LVPECL
3D OUT0 Output single-ended voltage levels for LVPECL outputs.
3E OUT1
3F OUT2
OUT3
[3] [2] Output Voltage (mV)
0 0 500
0 1 340
1 0 810 (default)
1 1 660

Rev. C | Page 49 of 56
AD9510 Data Sheet
Reg.
Addr.
(Hex) Bit(s) Name Description
3C [7:4] Not used.
3D
3E
3F
40 [0] Power-down Power-down bit for both output and LVDS driver. 0 = LVDS/CMOS on (default), 1 = LVDS/CMOS power-down.
41 LVDS/CMOS
42 OUT4
43 OUT5
OUT6
OUT7
40 [2:1] Output current
level
41 LVDS
42 OUT4
43 OUT5
OUT6
OUT7
[2] [1] Current (mA) Termination (Ω)
0 0 1.75 100
0 1 3.5 (default) 100
1 0 5.25 50
1 1 7 50
40 [3] LVDS/CMOS select 0 = LVDS (default), 1 = CMOS.
41 OUT4
42 OUT5
43 OUT6
OUT7
[4] Inverted CMOS Effects output only when in CMOS mode.
driver 0 = disable inverted CMOS driver (default), 1 = enable inverted CMOS driver.
40 OUT4
41 OUT5
42 OUT6
43 OUT7
40 [7:5] Not used.
41
42
43
44 [7:0] Not used.
45 [0] Clock select 0: CLK2 drives distribution section, 1: CLK1 drives distribution section (default).
45 [1] CLK1 power-down 1 = CLK1 input is powered down (default = 0b).
45 [2] CLK2 power-down 1 = CLK2 input is powered down (default = 0b).
45 [3] Prescaler clock 1 = shut down clock signal to PLL prescaler (default = 0b).
power-down
45 [4] REFIN power-down 1 = power-down REFIN (default = 0b).
45 [5] All clock inputs 1 = power-down CLK1 and CLK2 inputs and associated bias and internal clock tree (default = 0b).
power-down
45 [7:6] Not used.
46 [7:0] Not used.
47 [7:0] Not used.

Rev. C | Page 50 of 56
Data Sheet AD9510
Reg.
Addr.
(Hex) Bit(s) Name Description
[3:0] Divider high Number of clock cycles divider output stays high.
48 OUT0
4A OUT1
4C OUT2
4E OUT3
50 OUT4
52 OUT5
54 OUT6
56 OUT7
[7:4] Divider low Number of clock cycles divider output stays low.
48 OUT0
4A OUT1
4C OUT2
4E OUT3
50 OUT4
52 OUT5
54 OUT6
56 OUT7
[3:0] Phase offset Phase offset (default = 0000b).
49 OUT0
4B OUT1
4D OUT2
4F OUT3
51 OUT4
53 OUT5
55 OUT6
57 OUT7
[4] Start Selects start high or start low (default = 0b).
49 OUT0
4B OUT1
4D OUT2
4F OUT3
51 OUT4
53 OUT5
55 OUT6
57 OUT7
[5] Force Forces individual outputs to the state specified in start (see the previous section of this table). This
function requires that Nosync (see the next section of this table) also be set (default = 0b).
49 OUT0
4B OUT1
4D OUT2
4F OUT3
51 OUT4
53 OUT5
55 OUT6
57 OUT7

Rev. C | Page 51 of 56
AD9510 Data Sheet
Reg.
Addr.
(Hex) Bit(s) Name Description
[6] Nosync Ignore chip-level sync signal (default = 0b).
49 OUT0
4B OUT1
4D OUT2
4F OUT3
51 OUT4
53 OUT5
55 OUT6
57 OUT7
[7] Bypass divider Bypass and power down divider logic; route clock directly to output (default = 0b).
49 OUT0
4B OUT1
4D OUT2
4F OUT3
51 OUT4
53 OUT5
55 OUT6
57 OUT7
58 [0] SYNC detect enable 1 = enable SYNC detect (default = 0b).
58 [1] SYNC select 1 = raise flag if slow clocks are out-of-sync by 0.5 to 1 high speed clock cycles.
0 (default) = raise flag if slow clocks are out-of-sync by 1 to 1.5 high speed clock cycles.
58 [2] Soft SYNC The Soft SYNC bit works the same as the FUNCTION pin when in SYNCB mode, except that the polarity of
this bit is reversed. That is, a high level forces selected outputs into a known state, and a high > low
transition triggers a sync (default = 0b).
58 [3] Dist ref 1 = power down the references for the distribution section (default = 0b).
power-down
58 [4] SYNC power-down 1 = power down the SYNC (default = 0b).
58 [6:5] FUNCTION pin
select
[6] [5] Function
0 0 RESETB (default)
0 1 SYNCB
1 0 Test only, do not use
1 1 PDB
58 [7] Not used.
59 [7:0] Not used.
5A [0] Update registers Writing a 1 to this bit updates all registers and transfers all serial control port register buffer contents to
the control registers on the next rising SCLK edge. This is a self-clearing bit; a 0 does not have to be
written to clear it.
5A [7:1] Not used.
End

Rev. C | Page 52 of 56
Data Sheet AD9510

POWER SUPPLY
The AD9510 requires a 3.3 V ± 5% power supply for VS. The The exposed metal paddle on the AD9510 package is an electrical
tables in the Specifications section give the performance expected connection, as well as a thermal enhancement. For the device
from the AD9510 with the power supply voltage within this to function properly, the paddle must be properly attached to
range. The absolute maximum range of −0.3 V − +3.6 V, with ground (GND). The PCB acts as a heat sink for the AD9510;
respect to GND, must never be exceeded on the VS pin. therefore, this GND connection must provide a good thermal path
Follow good engineering practice in the layout of power supply to a larger dissipation area, such as a ground plane on the PCB.
traces and the ground plane of the printed circuit board (PCB). See the layout of the AD9510 evaluation board (AD9510/PCBZ
Bypass the power supply on the PCB with adequate capacitance or AD9510-VCO/PCBZ) for a good example.
(>10 µF). Bypass the AD9510 with adequate capacitors (0.1 µF) POWER MANAGEMENT
at all power pins as close as possible to the part. The layout of the The power usage of the AD9510 can be managed to use only the
AD9510 evaluation board (AD9510/PCBZ or power required for the functions being used. Unused features
AD9510-VCO/PCBZ) is a good example. and circuitry can be powered down to save power. The following
The AD9510 is a complex part that is programmed for its desired circuit blocks can be powered down, or are powered down when
operating configuration by on-chip registers. These registers are not selected (see the Register Map and Description section):
not maintained over a shutdown of external power. This means
• The PLL section can be powered down if not needed.
that the registers can lose their programmed values if VS is lost
• Any of the dividers are powered down when bypassed—
long enough for the internal voltages to collapse. Careful bypassing
equivalent to divide-by-one.
protects the part from memory loss under normal conditions.
• The adjustable delay blocks on OUT5 and OUT6 are
Nonetheless, it is important that the VS power supply not become
powered down when not selected.
intermittent, or the AD9510 risks losing its programming.
• Any output can be powered down. However, LVPECL
The internal bias currents of the AD9510 are set by the RSET and outputs have both a safe and an off condition. When the
CPRSET resistors. These resistors must be as close as possible to LVPECL output is terminated, use only the safe shutdown
the values given as conditions in the Specifications section to protect the LVPECL output devices. This still consumes
(RSET = 4.12 kΩ and CPRSET = 5.1 kΩ). These values are standard some power.
1% resistor values, and are readily obtainable. The bias currents • The entire distribution section can be powered down when
set by these resistors determine the logic levels and operating not needed.
conditions of the internal blocks of the AD9510. The performance
figures given in the Specifications section assume that these Powering down a functional block does not cause the program-
resistor values are used. ming information for that block (in the registers) to be lost.
This means that blocks can be powered on and off without
The VCP pin is the supply pin for the charge pump (CP). The
otherwise having to reprogram the AD9510. However, synchro-
voltage at this pin (VCP) can be from VS up to 5.5 V, as required
nization is lost. A SYNC must be issued to resynchronize (see
to match the tuning voltage range of a specific VCO/VCXO.
the Single-Chip Synchronization section).
This voltage must never exceed the absolute maximum of 6 V.
Additionally, never allow VCP to be less than −0.3 V below VS or
GND, whichever is lower.

Rev. C | Page 53 of 56
AD9510 Data Sheet

APPLICATIONS INFORMATION
USING THE AD9510 OUTPUTS FOR ADC CLOCK The AD9510 features both LVPECL and LVDS outputs that
APPLICATIONS provide differential clock outputs, which enable clock solutions
that maximize converter SNR performance. Consider the input
Any high speed ADC is extremely sensitive to the quality of the requirements of the ADC (differential or single-ended, logic
sampling clock provided by the user. An ADC can be thought of level, termination) when selecting the best clocking/converter
as a sampling mixer; any noise, distortion, or timing jitter on solution.
the clock is combined with the desired signal at the analog-to-
digital output. Clock integrity requirements scale with the analog CMOS CLOCK DISTRIBUTION
input frequency and resolution, with higher analog input fre- The AD9510 provides four clock outputs (OUT4 to OUT7),
quency applications at ≥ 14-bit resolution being the most which are selectable as either CMOS or LVDS levels. When
stringent. The theoretical SNR of an ADC is limited by the selected as CMOS, these outputs provide for driving devices
ADC resolution and the jitter on the sampling clock. Considering requiring CMOS level logic at their clock inputs.
an ideal ADC of infinite resolution where the step size and Whenever single-ended CMOS clocking is used, follow some of
quantization error can be ignored, the available SNR can be the following general guidelines.
expressed approximately by
Point-to-point nets must be designed such that a driver has one
 1  receiver only on the net, if possible. This allows for simple termina-
SNR = 20 × log   tion schemes and minimizes ringing due to possible mismatched
 2πft j 
impedances on the net. Series termination at the source is generally
where: required to provide transmission line matching and/or to reduce
f is the highest analog frequency being digitized. current transients at the driver. The value of the resistor is
tj is the rms jitter on the sampling clock. dependent on the board design and timing requirements (typically
Figure 53 shows the required sampling clock jitter as a function 10 Ω to 100 Ω is used). CMOS outputs are limited in terms of
of the analog frequency and effective number of bits (ENOB). the capacitive load or trace length that they can drive. Typically,
trace lengths less than 3 inches are recommended to preserve
tj = 50fs
120 SNR = 20log10
1 signal rise/fall times and preserve signal integrity.
2πftj
18 60.4Ω
tj = 0.1ps 1.0 INCH
10Ω
100 16 CMOS
tj = 1ps
14
MICROSTRIP
SNR (dB)

80 5pF
ENOB

05046-025
tj = 10ps 12

10
GND
60
tj = 100ps
8
Figure 54. Series Termination of CMOS Output

40 6 Termination at the far end of the PCB trace is a second option.

tj = 1ns
The CMOS outputs of the AD9510 do not supply enough current
05046-024

4
20 to provide a full voltage swing with a low impedance resistive,
1 3 10 30 100
far-end termination, as shown in Figure 55. The far-end termi-
FULL-SCALE SINE WAVE ANALOG INPUT FREQUENCY (MHz)
nation network must match the PCB trace impedance and provide
Figure 53. ENOB and SNR vs. Analog Input Frequency the desired switching point. The reduced signal swing may still
See Application Note AN-756, Sampled Systems and the Effects meet receiver input requirements in some applications. This can
of Clock Phase Noise and Jitter, and Application Note AN-501, be useful when driving long trace lengths on less critical nets.
Aperture Uncertainty and ADC System Performance. VPULLUP = 3.3V

Many high performance ADCs feature differential clock inputs 50Ω 100Ω
10Ω
to simplify the task of providing the required low jitter clock on CMOS
3pF
a noisy PCB. (Distributing a single-ended clock on a noisy PCB OUT4, OUT5, OUT6, OUT7
SELECTED AS CMOS
100Ω

can result in coupled noise on the sample clock. Differential

05046-027

distribution has inherent common-mode rejection, which can

provide superior clock performance in a noisy environment.) Figure 55. CMOS Output with Far-End Termination

Rev. C | Page 54 of 56
Data Sheet AD9510
Because of the limitations of single-ended CMOS clocking, LVDS CLOCK DISTRIBUTION
consider using differential outputs when driving high speed Low voltage differential signaling (LVDS) is a second differential
signals over long traces. The AD9510 offers both LVPECL and output option for the AD9510. LVDS uses a current mode
LVDS outputs, which are better suited for driving long traces output stage with several user-selectable current levels. The
where the inherent noise immunity of differential signaling normal value (default) for this current is 3.5 mA, which yields
provides superior performance for clocking converters. 350 mV output swing across a 100 Ω resistor. The LVDS outputs
LVPECL CLOCK DISTRIBUTION meet or exceed all ANSI/TIA/EIA-644 specifications.
The low voltage, positive emitter-coupled, logic (LVPECL) A recommended termination circuit for the LVDS outputs is
outputs of the AD9510 provide the lowest jitter clock signals shown in Figure 58.
available from the AD9510. The LVPECL outputs (because they 3.3V 3.3V
are open emitter) require a dc termination to bias the output
transistors. A simplified equivalent circuit in Figure 41 shows 100Ω
LVDS 100Ω LVDS
DIFFERENTIAL (COUPLED)
the LVPECL output stage.
In most applications, a standard LVPECL far-end termination is

05046-032
recommended, as shown in Figure 56. The resistor network is
designed to match the transmission line impedance (50 Ω) and
Figure 58. LVDS Output Termination
the desired switching threshold (1.3 V).
3.3V See Application Note AN-586, LVDS Data Outputs for High-Speed
3.3V 3.3V
Analog-to-Digital Converters, for more information on LVDS.
50Ω 127Ω 127Ω
POWER AND GROUNDING CONSIDERATIONS AND
LVPECL
SINGLE-ENDED
LVPECL
POWER SUPPLY REJECTION
(NOT COUPLED)
Many applications seek high speed and performance under less
50Ω than ideal operating conditions. In these application circuits,
VT = VCC – 1.3V 83Ω 83Ω
the implementation and construction of the PCB is as important as
05046-030

the circuit design. Proper RF techniques must be used for device

Figure 56. LVPECL Far-End Termination selection, placement, and routing, as well as for power supply
bypassing and grounding to ensure optimum performance.
3.3V 3.3V
0.1nF

DIFFERENTIAL 100Ω
LVPECL (COUPLED) LVPECL
0.1nF

200Ω 200Ω
05046-031

Figure 57. LVPECL with Parallel Transmission Line

Rev. C | Page 55 of 56
AD9510 Data Sheet

OUTLINE DIMENSIONS
9.10
9.00 SQ 0.60 MAX
8.90 0.60
MAX PIN 1
49 64 INDICATOR
48 1

PIN 1
INDICATOR

8.85 0.50 EXPOSED *4.85

8.75 SQ BSC PAD
4.70 SQ
8.65 4.55

0.50
0.40 33 16
32 17
0.30
BOTTOM VIEW 0.25 MIN
TOP VIEW
7.50 REF
12° MAX 0.80 MAX
1.00
0.65 TYP FOR PROPER CONNECTION OF
0.85
0.05 MAX THE EXPOSED PAD, REFER TO
0.80 THE PIN CONFIGURATION AND
0.02 NOM
FUNCTION DESCRIPTIONS
SEATING 0.30 SECTION OF THIS DATA SHEET.
PLANE 0.20 REF
0.23
0.18

06-13-2012-A
*COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
EXCEPT FOR EXPOSED PAD DIMENSION
Figure 59. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
(CP-64-1)
Dimensions shown in millimeters

ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD9510BCPZ −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-1
AD9510BCPZ-REEL7 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-1
AD9510/PCBZ Evaluation Board Without VCO or VCXO or Loop Filter
1
Z = RoHS Compliant Part.

©2005–2016 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D05046-0-9/16(C)

Rev. C | Page 56 of 56