Analog IC Layout
Dr. David W. Graham
West Virginia University
Lane Department of Computer Science and Electrical Engineering
1
Overview
• CMOS processes are constructed from “mask”
sets
• Each mask represents the information for a
specific layer
• Each layer contains all the shapes of a specific
material (e.g. polysilicon, diffusion regions,
metal, etc.)
– Layers are stacked one on top of each other
– Layers will not touch other layers unless specified to
do so
• To create an actual design that can be
fabricated, we must specify/draw the shapes for
each layer
2
Layers
• Each layer represents a specific type of material
for a specific purpose
• Examples include
– Diffusion regions – for sources and drains
– Polysilicon – for gates
– Metal layers – for routing/interconnections (typically
several independent metal layers)
– Contacts – connecting MOSFET terminals to the
lowest metal layer (metal 1)
– Vias – connecting from one metal layer to the next
higher or lower metal layer
3
Design Rules
• Design rules specify minimum requirements to
ensure reliability when fabricated
• Examples include
– All contacts must be a specific size
– Minimum transistor W and L
– Minimum spacing between metal lines in the same
metal layer
• Design Rules Check (DRC) – IC design tools will
check to ensure that all minimum requirements
have been met
• Your design must pass DRC before a foundry
will fabricate your design
4
Extraction
• Netlist extraction will translate your design
shapes into actual components for
verification purposes
• Can use extracted layout to
– Resimulate your design
• Verify operation that it works
• Determination of parasitics
– For comparison with your schematic (layout
vs. schematic checks)
5
Layout vs. Schematic (LVS)
• Layout vs. Schematic (LVS) verification
– Comparison of your schematic with the netlist
extracted from your layout
– A critical verification step!
• This verification step can be time
consuming (if you have multiple errors in
your layout)
6
Unit Sizes
• Grid size/spacing
– Layout has a minimum size/resolution which can reliably be fabricated
on a specific process
– Smallest quantized size
– All drawn dimensions are scalar multiples of this size
– Similar to “snap-to”
• Exact dimension vs. lambda
– Layout can be specified in exact sizes (i.e. μm)
– Layout can be specified in relative sizes (i.e. λ)
– λ is used with “scalable” CMOS processes
• Provides general rules for all CMOS processes
• Moving a design to a new process requires no additional modification to the
design
• λ is mapped to a specific size for the process – everything else is scaled
accordingly
• Harder to use for submicron processes (too many “new” rules)
• Ex. minimum transistor length is 2λ (λ = 0.3μm in a 0.5μm process)
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nFET Layout
Active
Polysilicon
Contact
drain
Metal
gate W
L
source
Layout figures from Reid Harrison 8
nFET Cross Sectional View
drain
Across the Channel
gate
cross section
source
Metal
polysilicon
SiO2
p- substrate
9
nFET Cross Sectional View
gate
Along the Channel
cross section
source
drain
polysilicon
Metal SiO2 Metal
n+ n+
p- substrate
10
Substrate Connection
The bulk is the fourth terminal
Do not forget to tie down the bulk
cross section
substrate
Metal
p+
p- substrate
11
pFET Layout
Active
• pFET requires a drawn well and a
Polysilicon
well connection
Contact
• Otherwise, identical to an nFET
Metal
Well
drain
gate W
L
source
well
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pFET Cross Sectional Views
drain
gate
gate
cross section
source
cross section
drain
well
well source
polysilicon
Metal Metal SiO2 Metal Metal
polysilicon
+ + +
n p p
SiO2
n- well
p- substrate
n- well
p- substrate
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Poly-Poly Capacitors
Polysilicon (“poly”)
Second-layer Polysilicon (“poly2”)
Contact
• Some processes have two Metal
polysilicon layers for making linear
capacitors.
• Typical capacitance is 0.5-0.9 fF/μm2
• There is also a “bottom plate”
capacitance between the lower poly cross section
layer and the substrate that is
typically about 10% of the poly-poly2
capacitance
• If there is no poly2 layer, capacitors
are made from MOSCaps polysilicon
Metal
Metal
SiO2
SiO2
p- substrate
14
Example Layout
in out
Active
Polysilicon
Contact ground
Metal
in out
ground
15
Multiple Metal Layers
• Contacts connect bottom-layer metal
(metal1) to active (n+ or p+ regions),
poly, or poly2.
• Metal2 can be connected to metal1 Metal3
using a via. via2
• Metal3 can be connected to metal2
Metal2
using a via2.
via
• Thus, if we want to connect metal1 to polysilicon
metal3, we must go through metal2 Metal1 SiO2 Metal1
using a via and a via2. contact
• In some processes (including the one n+ n+
we use in this class), vias/contacts
p- substrate
may be stacked vertically. In other
processes, they must be offset from
one another.
• Neither contacts nor vias should be
placed over transistor gates.
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Mismatch
• One of the biggest concerns with analog layout
(often “rate limiting”)
• Systematic mismatch and random mismatch
• Caused by many, many processes
– Examples include
• Random edge distortion
• Corner-rounding distortion
• On-chip concentration gradients
• Under etching
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Concentration Gradients
• Due to fabrication non-idealities, concentration gradients arise in the
silicon wafer
• Systematic variation of parameters across a chip
– Ex. gate oxide thickness, diffusion doping concentration, temperature
• Designs must be robust to concentration gradients
– Direction of gradients are not known a priori
18
Rules of Thumb for Improved Matching
• Large Devices
• Close Proximity
• Same Orientation
• Multiple, equally sized devices
• Common-centroid layout
• Dummy elements for fringe effects
• Symmetry wherever possible
19
Large Sizes
• Large sizes minimizes edge distortion
• Edge distortion can be represented by dimension + Δ
• Larger dimensions reduce the effect of edge distortion by
– Averaging
– Smaller contribution of Δ to overall area (important for capacitors)
20
Devices with Same Orientation
• Keep matched devices close together
• Orient them in the same direction
• Current flow in the same direction
Good
Not as good
21
Equally Sized Devices
• CMOS processes are relatively good at
matching ratios, but not absolutes
• Use multiple “unit-sized” devices
Iin Iout
W W
=1 =4
L L
I in Iout
W
Each with =1
L
W
=1
L
22
Common-Centroid Layout
• Ensure that all devices that are being
matched have a “common centroid”
– Will remove the effects of linear gradients
– Will help with non-linear gradients, but not
completely remove
23
Common-Centroid Layout Examples
Let A=B. Match A and B.
A B B A
A B
B A
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Common-Centroid Layout Examples
A B B A
B A A B
B A A B
A B B A
25
Multiple “Fingers” for Transistors
• Reduces layout to multiple, identically sized devices
• Split transistors into M narrow transistors in parallel (but
maintain same length)
• Reduces series gate resistance (reduces noise)
• Can easily be used with common-centroid layout
• Ex. M = 2
S D S
26
Dummy Devices
• Place “dummy” devices surrounding your
devices so that they all “see” the same thing.
• Ex. Capacitors
A B
B A
27
Symmetric Layout
• It helps if all devices “see” the same thing
• Example for matching two transistors
Not Symmetric Symmetric
28
“Doughnut” Transistors
• Reduces
– Gate-to-drain overlap capacitance
– Drain-to-bulk junction capacitance
• Can improve speed of response
G
D
29
Parasitic BJTs
• Parasitic BJTs created by pn junctions inherent in a
CMOS process
– Substrate BJT (pnp)
• Emitter = p+ diffusion region (within an n-well)
• Base = n-well
• Collector = p- substrate
• Collector always connected to ground
– Lateral BJT
• Emitter = n+ diffusion region (source)
• Base = p- substrate
• Collector = n-well
• Base is always connected to ground
• Sometimes purposely used
– Temperature insenstive current sources
– Bias currents
30
Latchup
• Caused by parastic BJTs within a CMOS process
• Lateral and substrate BJTs combine to form a silicon-
controlled rectifier (SCR)
• Latchup typically contains two states
– High-current state
– Low-voltage state
• Can cause an IC to no longer work
• Can cause permanent damage
• Caused by a large current flowing over larger
resistances to ground Æ produces a large voltage drop
• Solution Æ Reduce these resistances to ground
• Use ground/well tie downs liberally!!!
31
Wide-Output Range OTA
32
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Common-Centroid Layout (Bias Current Mirror)
34
Common-Centroid Layout (2 Current Mirrors)
35
Input Pair
Drain N0
Gate N0
36
pFET Current Mirrors
37
All Transistors
“Guard Rings”
for bulk/well
tie-downs
38
Final Cell Layout
39
Analog Layout Summary
A paranoid person makes for a very good
analog layout designer.
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