LAYOUT DESIGN
CMOS Design
PLANAR MOSFET, FINFET
SYNOPSYS
LAYOUT DESIGN ENGINEER
CMOS basic layout concept
Layout
INVERTER, NOR, NAND, 6T SRAM
Candidate: Ngo Hai Huy
Layout Design Engineer
CMOS DESIGN
CMOS - Complementary Metal Oxide Semiconductor is
a term for a type of technology used to make integrated
circuits. CMOS uses complementary and symmetrical
pairs of p-type and n-type MOSFETs for logic functions.
CMOS technology is used for constructing integrated
circuit chips, including microprocessors, microcontrollers,
memory chips (including CMOS BIOS), and other digital
logic circuits. CMOS technology is also used for analog
circuits such as image sensors (CMOS sensors), data Figure 1:
Invert circuit
converters, RF circuits (RF CMOS), and highly integrated
transceivers for many types of communication.
Layout Design Engineer
CMOS DESIGN
PLANAR MOSFET
MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is
semiconductor device. It is used as a switch and amplifier of signals in
electronic circuits. It is also widely used in integrated circuits.
Figure 2: MOSFET Structure Figure 3: N-MOSFET symbol
MOSFET is four terminal device with S (source), G (gate), D (drain)
and B (body). Body terminal is normally internal connected to source
making to appear as a three terminal device in circuits.
Layout Design Engineer
CMOS DESIGN
PLANAR MOSFET
Classification of MOSFETs: Depending on the type of materials used
in the construction, and the type of operation, the MOSFETs are
classified as in the following figure.
ENHANCEMENT
N - CHANNEL
DEPLETION
MOSFET
ENHANCEMENT
P - CHANNEL
DEPLETION
Figure 4: Classification of MOSFETs
Layout Design Engineer
CMOS DESIGN
PLANAR MOSFET
When positive voltage is applied to
the gate it provides electric field that
repels holes from P-Type Substrate.
The positive voltage also attracts
electrons from source and drain. The
electron rich channel or N-Channel is
formed.
The gate voltage controls the
concentration of electrons in n-
Figure 5: N-MOSFET channel. Higher gate voltage will
increase the current between the
source and the drain.
Layout Design Engineer
CMOS DESIGN
FINFET
FinFET (Fin Field Effect Transistor) is a multigate device, a MOSFET
built on a substrate where the gate is placed on two, or three sides of the
channel or wrapped around the channel, forming a double or even multi
gate structure.
They called "FinFET" because
the source/drain region forms fins
on the silicon surface.
FinFET has the same family of
transistors with Planar MOSFET,
but its 3D construct differently and
have a different level of scalability. Figure 6: 3D FinFET Structure
Layout Design Engineer
CMOS DESIGN
FINFET
Figure 7: FINFET Structure
This form of gate structure provides improved electrical control over
the channel, and it helps reduce leakage current levels and overcomes
some other short-channel effects.
The FinFET devices have significantly faster switching times and
higher current density than planar MOSFET.
Layout Design Engineer
CMOS DESIGN
PLANAR MOSFET AND FINFET
PLANAR MOSFET FINFET
Structure Planar 3D
Static leakage current High Reduce 90%
Power High Low
Short-channel effects Yes No
Subthreshold slope, Low High
voltage gain
Operating speed Low High
Figure 8: MOSFET and FINFET
Layout Design Engineer
CMOS LAYOUT DESIGN CONCEPT
The process of creating an accurate physical representation of an
engineering drawing (netlist) that conforms to constraints imposed by the
manufacturing process, the design flow, and the performance requirements
shown to be feasible by simulation.
Netlist
Manufacturing
Design rules
process
Accurate
LAYOUT Constraint
DESIGN
physical Design flow Guidelines
representation
Performance
requirements
Figure 9: Layout Design
Layout Design Engineer
CMOS LAYOUT DESIGN CONCEPT
Define Power Grid and Global Signals
Position, width requirements, and global
connections.
Define Floorplan Define Signals
Interface location and width as well as
critical and special cases
Implement the Design
Consider Special Design Requirements
Symmetrical layout cells, guard banding,
Layout Verification noise and latch up protection.
Approximate Size and Hierarchy
Final Step Floorplan components and signals
estimate total size and check against
budget
Figure 10: Layout Planning Arrange for Audit Engineering and
Layout Sanity Check
Layout Design Engineer
CMOS LAYOUT DESIGN CONCEPT
Design and/or Place Components
Create and place components as required
using the floorplan and layout
Define Floorplan guidelines.
Consider Special Design Requirements
Implement the Design
Consider critical and methodology
elements and refine the placement of
Layout Verification cells
Complete Interconnect
Final Step Complete all connections usually
addressing critical items first
Figure 11: Layout Implement
Layout Design Engineer
CMOS LAYOUT DESIGN CONCEPT
Design Rule Check (DRC)
Checks process design rules and
supplementary rules
Define Floorplan
Layout versus Schematic (LVS)
Implement the Design Checks that layout connectivity as
identical to schematic connectivity
Layout Verification
Electrical Rules Check (ERC)
Check for connectivity problems
Final Step
Visual Inspection
Figure 12: Layout Planning Plot the design and inspect Check against
layout guidelines and special rules
Layout Design Engineer
CMOS LAYOUT DESIGN CONCEPT
Define Floorplan
Implement the Design
Layout Verification
Engineering and Layout Audit
Final Step
Extraction and Resimulation
Figure 13: Final step
Layout Design Engineer
LAYOUT
Layered Representation of Layout: The layer representation of layout
converts the masks used in CMOS into a simple layout levels that are
easier to visualise by the designers. The CMOS design layouts are based
on following components :
- Substrates or Wells
- Diffusion regions
Figure 14: NMOS Layout
- Polysilicon layers
- Metal interconnects layers
- Contact and Via layers
Figure 15: PMOS Layout
Layout Design Engineer
LAYOUT
INVERTER LAYOUT
Stick Diagram
VDD
D S
x x
DL
Figure 16: Inverter gate
IN
OUT
x x
GND S D
Figure 17: Inverter stick diagram
19: Inverter Layout
Figure 18:
Layout Design Engineer
LAYOUT
NAND LAYOUT
VDD
D Sx S Dx
x
DL OUT
x x
S D S D
GND
A B
Figure 21: NAND stick diagram
Figure
Figure Figure
22:Figure
N24: 25:
– well
Metal
23: Viaactive
and layer
layer
Poly for area
layer VDD,layer
FigureGND
26:and
Figure NAND
20: OUT
NANDlayerGate
Layout Design Engineer
LAYOUT
NOR LAYOUT
VDD
S D Sx
xD
DL OUT
x x x
S D D S
GND
A B
Figure 28: NOR stick diagram
Figure 29: NOR Layout
Figure 27: NOR Gate
Figure 30: NOR Layout
Layout Design Engineer
LAYOUT
6T SRAM LAYOUT
VDD
S D D Sx ~B
B x
x
DL
x
x x x x x
D S D S S D S D
GND
WL
S
Figure 32: NOR stick diagram
Figure 33: 6T SRAM Layout
Figure 31: 6T SRAM
Layout Design Engineer
REFERENCE
[1] https://www.electricaltechnology.org/2021/06/mosfet.html
[2] https://hoanghapc.vn/14nm-10nm-7nm-5nm-thuc-ra-con-so-nay-do-cai-gi-
tren-con-chip
[3]https://semiengineering.com/knowledge_centers/manufacturing/process/
issues/short-channel-effects/
[4]https://inderjitsingh87.weebly.com/uploads/2/1/1/4/21144104/
cmos_design_rules___layout.pdf
[5]https://www.electronics-tutorial.net/Digital-CMOS-Design/
CMOS-Layout-Design/Layout-Design-Rules/
[6] “CMOS IC Layout” Book
[7] https://en.wikipedia.org/
[8]https://resources.system-analysis.cadence.com/blog/msa2021-using-finfets-
vs-mosfets-for-ic-design
THANK YOU
