8 Logic Families

Introduction
A group of compatible ICs with the same logic levels and supply voltages fabricated for
performing various logic functions (OR, AND and NOT) are referred to as logic families.

Classification of logic families:

Fig. 8.1 Classification of Logic Families

y Logic circuits which are operated in the 1. Propagation delay: It is the time required
saturation region are called saturated to get a valid output after applying input.
It is expressed in nanoseconds. It should
logic families.
be as minimum as possible.
y Logic circuits that are operated in active
It depends on the storage time of the
and cut-off regions are called unsaturated transistor and the RC time constant.
logic families.
Example 1:
Specifications of logic families:
The important specifications of logic families
are:
1. Propagation delay
2. Power dissipation
3. Figure of merit
4. Fan-out
5. Noise margin Fig. 8.2

Logic Families 177

 Truth table: Where,
ICH + ICL
IC(avg ) =
Input Q Output 2
3. Figure of merit: It is the product of propagation
0 OFF 1 (VCC)
delay (tpd) and power dissipation (Pdiss).
1 ON 0 (0 Volt) It should be as minimum as possible. It is
Table 8.1
expressed in Pico Joules.
FOM = tpd ×Pdiss (Pico Joules)
This circuit shows the characteristics of an 4. Fan-out: It is the maximum number of
inverter. In this circuit whenever we give the gate inputs we can connect to the output
input, the output changes its states from of another gate. It should be as maximum
‘ON’ to ‘OFF’ and ‘OFF’ to ‘ON’, (i.e., saturation as possible. It depends on the current
to cut-off and cut off to saturation). So, it sinking and current sourcing.
requires some time to change its states. Current sourcing: When the logic output
Similarly, if some load is applied to this circuit is in logic ‘1’, the output transistor is in
and load contains some capacitance. So, the off condition and gate acts like a current
capacitance requires some time to charge source to the external gates connected.
and discharge through this capacitance Current sinking: When the logic output
load. So, based on the switching time of is in logic ‘0’, the output transistor is in
the capacitor and RC time constant, some on condition and gate acts like a sink to
time is required to get the valid output after the incoming currents from external gates
applying the input. So, this delay is called connected.
propagation delay.

Timing diagram of inverter due to propagation

delay:

Fig. 8.4 Sinking and Sourcing Current

y When input is ‘0’, the transistor goes to

Fig. 8.3 Timing Diagram the ‘OFF’ state, and output will become
In general, propagation delay of the transistor logic ‘1’. The current flows from source to
is- the inverter output and the gate acts like a
current source to all other external gates
tPLH > tPHL
connected in output. So the maximum
So, the propagation delay is- current provided will be-
t + tPLH
tpd = PHL
2 VCC
ICmax =
2. Power dissipation: It is the average power RC
dissipated by one gate. It is expressed in y When input is ‘1’, transistor goes to the
milliwatts. It should be as minimum as ‘ON’ state and the output will become
possible for any logic gate. logic ‘0’. So, the gate acts like a sink for all
Power dissipation in transistor the incoming current of the other external
Pdiss = IC(avg) × VCC gates connected in the circuit. But here

178 Logic Families

 in this circuit, it cannot sink any current
because to stay in saturation region, IC< Previous Years’ Questions
βIb.
When the output is ‘High’: Given that for a logic family,
VOH is the minimum output high-level
voltage.
VOL is the maximum output low-level
voltage.
VIH is the minimum acceptable input
high-level voltage.
VIL is the maximum acceptable input
low-level voltage.
Fig. 8.5 High Output The correct relationship is-
(A) VIH > VOH > VIL > VOL
IOH
High state fan-out (FOH) = (B) VOH > VIH > VIL > VOL
IIH (C) VIH > VOH > VOL > VIL
(D) VOH > VIH > VOL > VIL
Solution: (B)

When the output is ‘Low’ IOL

Low state fan-out (FOL) =
IIL
So, fan-out = min(FOH, FOL)

5. Noise margin: It is the maximum amount

of noise that can be added at the input
of the logic gate, which cannot affect the
output logic. It should be as maximum as
possible.
Fig. 8.6 Low Output

Fig. 8.7 Noise Margin Range

So, VOH > VIH > VIL > VOL

Then, noise margin = min {(N.M)H, (N.M)L}

Logic Families 179

 voltage (VIH) = 3V, maximum guaranteed
Previous Years’ Questions output low voltage (VOL) = 1.5V and maximum
accepted input low voltage (VIL) = 2.5V.
A logic family has threshold voltage The noise margin based on the above
VR = 2V, minimum guaranteed output high specifications will be?
voltage VOH = 4V, minimum accepted (A) 0.5V (B) 1V
input high voltage VIH = 3V, maximum (C) 3V (D) 2.5V
guaranteed output low voltage VOL = 1V
and maximum accepted input low Solution: (B)
voltage VIL = 1.5V. Its noise margin is: (NM)H = VOH –VIH = 6 – 3 = 3V
(A) 2V (B) 1V
(NM)L = VIL –VOL = 2.5 – 1.5 = 1V
(C) 1.5V (D) 0.5V
Solution: (D) So, noise margin = min{(NM)H, (NM)L}
Noise margin = min{3, 1}
Example 2:
Noise margin = 1V
A logic family has the following specifications:
Correct answer is (B).
Minimum guaranteed output high voltage
(VOH) = 6V, minimum accepted input high

Previous Years’ Questions

The inverter 74ALS01 has the following specifications:

IOHmax = –0.4 mA, IOLmax = 8 mA
IIHmax = 20 μA, IILmax = –0.1 mA
The fan-out based on the above data will be:
(A) 10 (B) 20
(C) 60 (D) 100
Solution:

Resistor Transistor Logic (RTL) In transistor, if the base current ib = 0, then

the transistor acts like an open circuit. So,
Transistor is called as a current-controlled no current will flow from collector to emitter.
device, it means that the base current (ib) in If ib≠ 0, then the transistor goes into the ON-
the transistor controls the transistor. state. So, the transistor acts like a short
circuit, and the collector current (ic) flows to
the emitter terminal.

Fig. 8.8 RTL

Fig. 8.9 Collector to Emitter

180 Logic Families

If ib = 0, then the transistor is in a cut-off Truth Table:
state, and no current flows from collector to
Input Output
emitter.
A Y
If ib≠0, then the transistor goes into the ON-
state, and current (ic) flows from collector to 0 (Low) 1 (High)
emitter. 1 (High) 0 (Low)
Table 8.2
Inverter:
The above truth table shows the inverter
operation. So, the given circuit is an inverter
or NOT gate.

Buffer:

Fig. 8.10 Inverter Mode

In the given circuit, if input = 0 (A = low (or)

logic ‘0’) then no current flows from the base
terminal (ib= 0). So, the transistor acts like an
open circuit and supply voltage +VCC appears Fig. 8.13 Buffer

at the output terminal (output = VCC (or) In the given circuit, if input (A) is logic ‘low’
Y = logic ‘1’). (or, A = 0), then the base current (ib = 0) is
zero. So, the transistor acts like an open
circuit and the output goes into the low state
(Y = logic ‘0’).

Fig. 8.11 Open Circuited

If input = 1 (logic ‘high’ (or) A = 1), then the

Fig. 8.14 Open Circuited
base current ib≠ 0 and transistor act like a
short circuit and the logic ‘low’ appears at If input (A) is logic ‘high’ (or, A = 1), then
the output terminal (Y = logic ‘0’). the base current (ib ≠ 0) flows through the
transistor. So, the transistor goes into the
ON-state and output becomes logic ‘high’
(or, Y = 1).

Fig. 8.12 Short Circuited

Fig. 8.15 Short Circuited

Logic Families 181

 Previous Years’ Questions

The logic functionality realised by the

circuit shown below is

Fig. 8.18 For both Input Low

If input A is low (logic ‘0’) and B is high

Fig. 8.16 (logic ‘1’), then only the transistor T2 goes
into ON-state. So, the output (Y) becomes
(A) OR (B) XOR
‘high’ (logic ‘1’).
(C) NAND (D) AND
Solution: (D)

Truth table:

Input Output

A Y

0 (Low) 0 (Low)

1 (High) 1 (High)
Table 8.3 Fig. 8.19 For One Input High and One Input Low

The above truth table shows the buffer If input A is high (logic ‘1’) and B is low
operation. So, the given circuit is a buffer (logic ‘0’), then the transistor T1 goes into the
circuit. ON-state. So, the output (Y) becomes ‘high’
(logic ‘1’).
NAND gate:

Fig. 8.20 For One Input High and One Input Low

Fig. 8.17 NAND Gate If input A is high (logic ‘1’) and input B is high
(logic ‘1’), then the transistors T1 and T2 both
In the above circuit, if both input A and B are go into ON-state. So, the output (Y) becomes
‘low’ (logic ‘0’), then both transistors T1 and ‘low’ (logic ‘0’).
T2 go into OFF-state (open circuit). So, the
output (Y) becomes ‘high’ (logic ‘1’).

182 Logic Families

 y If input A = 0 (low) and B = 0 (low), then
both the transistors T1 and T2 go into the
OFF-state. So, the output becomes ‘high’
(Y = 1).
y If input A = 0 (low) and B = 1 (high), then
the transistor T1 goes into the OFF-state
and transistor T2 goes into the ON-state.
So, the output becomes ‘low’ (Y = 0).
y If input A = 1 (high) and B = 0 (low), then
the transistor T1 goes into the ON-state
and transistor T2 goes into the OFF-state.
So, the output becomes ‘low’ (Y = 0).
y If input A = 1 (high) and B = 1 (high), then
both the transistors go into the ON-state
and the output becomes ‘low’ (Y=0).
Fig. 8.21 For Both Input High

Truth table: Previous Years’ Questions

Input Output
In the circuit shown, what are the values
A B Y of F for EN = 0 and EN = 1, respectively?
Low (0) Low (0) High (1)
Low (0) High (1) High (1)
High (1) Low (0) High (1)
High (1) High (1) Low (0)
Table 8.4

The above truth table shows the NAND

operation. So, the given circuit is NAND gate.

NOR gate:
Fig. 8.23
(A) 0 and 1
(B) Hi-Z and D
(C) Hi-Z and D
(D) 0 and D
Solution: (B)

Truth table:

Input Output
A B Y
Low (0) Low (0) High (1)
Fig. 8.22 NOR Gate Low (0) High (1) Low (0)

Logic Families 183

 Input Output Truth table:

A B Y Input Output
High (1) Low (0) Low (0) A B X Y=X
High (1) High (1) Low (0)
0 0 1 0
Table 8.5
0 1 0 1
The above truth table shows the NOR
1 0 0 1
operation. So, the given circuit is NOR circuit.
1 1 0 1
Example 3: Table 8.6
In the given circuit, what will be the So, X = AB
expression for Y? Which gate is realised by
the given circuit? X= A + B
Output, Y=X
Y= A + B
Y = (A+B)
Hence, the given circuit is OR gate and
expression Y = (A+B).
Specifications of RTL:
y RTL supports wired AND operation
Fig. 8.24 y Propagation relay (tpd) = 50 nsec
y Power dissipation (Pdiss) = 10 mW
Solution: y Figure of merit (FOM) = 500 pJ
y Noise margin (NM) = 0.2 V
Given circuit,
y Fan-out = 3

Logic Gates Implementation Using Diodes:

In an ideal diode, if the anode voltage (VA) is
more than the cathode voltage (VC), then the
diode is in forward bias and acts like a short
circuit.
If the anode voltage (VA) is less than the
cathode voltage (VC), then the diode is in
Fig. 8.25
reverse bias and acts like an open circuit.

Let X be the output of circuit-1 and Y be the

output of circuit-2.
The given circuit-2 is an inverter circuit. So
Y=X Fig. 8.26 Diode

If VA>VC, diode is in forward bias (short

circuit)
If VA<VC, diode is in reverse bias (open circuit)

184 Logic Families

 y If inputs applied are A = 0 and B = 1,
Previous Years’ Questions then diode D1 becomes forward bias
(short circuit) and D2 becomes reverse
bias (open circuit), and the output of the
In the circuit shown below, Q1 has
circuit becomes logic ‘0’ (or, Y = 0).
negligible collector-to-emitter saturation
voltage, and the diode drops negligible
voltage across it under forward bias. If
VCC is +5V, X and Y are digital signals with
0V as logic 0 and VCC as logic 1, then the
Boolean expression for Z is:

Fig. 8.30 One Diode Forward Biased and One Diode

Reverse Biased.

y If inputs applied are A = 1 and B = 0,

then diode D1 becomes reverse bias
(open circuit) and D2 becomes forward
bias (short circuit) and the output of the
circuit becomes logic ‘0’ (or, Y = 0).
Fig. 8.27

(A) XY (B) XY
(C) XY (D) XY
Solution: (B)

AND gate using diodes:

Fig. 8.31 One Diode Forward Biased and One Diode
Reverse Biased.

y If inputs applied are A = 1 and B = 1, then

both the diodes D1 and D2 become open
circuit (reverse bias). So the output of the
circuit becomes logic ‘1’ (or, Y = 1).
Fig. 8.28 AND Gate Using Diodes

y The given circuit is of AND gate. If inputs

applied are A = 0 and B = 0, then both the
diodes D1 and D2 become forward bias.
So, the diodes act as short circuits and
the output of the circuit becomes logic ‘0’
(or, Y = 0).
Fig. 8.32 Both Diodes are Reverse Biased

Fig. 8.29 Both Diode Forward Biased

Logic Families 185

 Truth table: Solution:

Inputs Output Truth table:

A B Y A B C D1 D2 D3 Y
0 0 0 Forward Forward Forward
0 0 0 0
0 1 0 bias bias bias

1 0 0 Forward Forward Reverse

0 0 1 0
bias bias bias
1 1 1
Forward Reverse Forward
Table 8.7 0 1 0 0
bias bias bias

Forward Reverse Reverse

Previous Years’ Questions 0 1 1 0
bias bias bias

Reverse Forward Forward

In the circuit shown, diodes D1, D2 and 1 0 0 0
bias bias bias
D3 are ideal, and the inputs E1, E2 and
E3 are ‘0 V’ for logic ‘0’ and ‘10 V’ for Reverse Forward Reverse
logic ‘1’. Which logic gate does the circuit 1 0 1 0
bias bias bias
represent?
Reverse Reverse Forward
1 1 0 0
bias bias bias

Reverse Reverse Reverse

1 1 1 1
bias bias bias
Table 8.8

So, the output of the circuit Y = ABC.

Fig. 8.33 OR Gate using diodes:

(A) 3-input OR gate
(B) 3-input NOR gate
(C) 3-input AND gate
(D) 3-input XOR gate
Solution: (C)

Example 4: Fig. 8.35 OR Gate Using Diodes

Specify the operation of the circuit having y If inputs applied are A = 0 and B = 0,
inputs A, B and C, and output Y. then both the diodes D1 and D2 become
reverse bias (open circuit), and the output
of the circuit becomes logic ‘0’ (or, Y=0).

Fig. 8.34 Fig. 8.36 OR Gate Using Diodes

186 Logic Families

y If inputs applied are A = 0 and B = 1, then Example 5:
diode D1 becomes reverse bias (open
Find the expression for Y as shown in the
circuit) and diode D2 becomes forward
figure.
bias (short circuit), and the output of the
circuit becomes logic ‘1’ (or, Y = 1).

Fig. 8.37 OR Gate Using Diodes

y If inputs applied are A = 1 and B = 0, then

diode D1 becomes forward bias (short Fig. 8.40
circuit) and the diode D2 becomes reverse
bias (open circuit) and the output of the Solution:
circuit becomes logic ‘1’ (or, Y = 1). Given circuit,

Fig. 8.38 OR Gate Using Diodes

y If inputs applied are A = 1 and B = 1, then

both the diodes D1 and D2 become forward
bias (short circuit), and the output of the
circuit becomes logic ‘1’ (or, Y = 1).
Fig. 8.41

Previous Years’ Questions

Among the digital IC-families, ECL, TTL

Fig. 8.39 OR Gate Using Diodes and CMOS:
(A) ECL has the least propagation delay
Truth table:
(B) TTL has the largest fan-out
Inputs Output (C) CMOS has the biggest noise margin
A B Y (D) TTL has the least power consumption
0 0 0 Solution: (A)
0 1 1
The given circuit is a combination of three
1 0 1
circuits, where circuit-1 and circuit-2 are AND
1 1 1 gate, and circuit-3 is the diode representation
Table 8.9 of OR Gate.

Logic Families 187

 Output of circuit-1 → X1 = AB Truth table:
Output of circuit-2 → X2 = CD
Input Output
Output of circuit-3 → Y = X1+X2
Y = AB+CD A Y

0 1
Transistor Transistor Logic (TTL)
1 0
The transistor logic circuit uses transistors
Table 8.10
to perform logic functions. TTL logic circuits
have three different configurations-
1. Open collector output TTL
Previous Years’ Questions
2. Tri-state output TTL
3. Totem pole output TTL
The figure shows the internal schematic
of a TTL AND-OR-Invert (AOI) gate. For
1. Open collector output TTL:
the inputs shown in the figure, the
output Y is

Fig. 8.43

(A) 0 (B) 1
(C) AB (D) AB
Solution: (A)
Fig. 8.42 Open Collector Output TTL
In the TTL circuit, if suddenly some transient
In the above TTL circuit, if we take input A=0,
occurs in the network, then the base current
then the emitter terminal of the transistor
becomes very high, which can damage the
(T1) becomes logic ‘0’ (or 0 volt) and the
transistor (T1). So, to eliminate the drawback
base voltage is ‘high’. So, diode D1 becomes
of this circuit, we use a diode (D) at the
forward bias and diode D2 becomes reverse
emitter terminal of transistor (T1).
bias. Current flows from base to emitter
terminal and no current flows from base to
collector terminal (D2 is reverse bias). So, the
transistor (T2) becomes OFF (base current of
T2 is ib = 0) and the output of the TTL circuit
will become logic ‘1’ (or, Y = 1).
If input A = 1, then diode D1 becomes reverse
bias and diode D2 becomes forward bias.
So, the transistor (T2) goes into the ON-state Fig. 8.44
and the output of the TTL circuit becomes
logic ‘0’ (or Y = 0).
VCC −  −5
ib =
1
RB

188 Logic Families

 VCC + 5 a) 
In a tri-state logic circuit, if E = 0 and
ib =
1 RB A = 0, then transistor T2 will become
OFF (open circuit) and T1 will become
ON (short circuit), transistor T3 will
also become OFF (base current = 0).
So, the output of the tri-state circuit
goes into the ‘High impedance state’.
b) 
If E = 1 and A = 0, then transistor T2
will be in ON-state, T1 will be in OFF-
state (reverse bias) and T3 will be in
Fig. 8.45
OFF-state. So, the output of the tri-
state circuit becomes logic ‘1’ (or Y = 1).
Base current of the transistor should be low c) 
If E = 1 and A = 1, then transistor T2
(in order of mA), but here the base current will be in ON-state, T1 will be in ON-
(ib1) is very high. state and T3 will be in ON-state. So,
a) When –ve spikes occurs: the output of the tri-state circuit
 Diode (D) becomes short circuit and becomes logic ‘0’ (or Y = 0).
emitter terminal gets connected to Truth table:
the ground (0 V).
V −0
1
( )
So, Base current ib = CC
RB E A Y

b) When +ve spikes occurs: 0 X High-impedance state

 Diode (D) becomes open circuit and
1 0 1
emitter terminal voltage of transistor
T1 will become +5 volt. 1 1 0
VCC − ( −5 )
So, Base current ib =
1
( ) RB
Table 8.11

3. Totem pole output/active pull-up stage

c) Diode (D) is called as a clamping diode. TTL:
2. Tri-state output TTL:
Tri-state logic provides high-speed
operation with wired logic. It has three
states: low, high and high impedance state.

Fig. 8.47 Totel Pole Output TTL

Totem pole configuration of the TTL circuit

consists of three sections. Transistor T1 is
Fig. 8.46 Tri-State Output TTL included in the input section, transistor T2

Logic Families 189

 is included in the phase shifter section and 1. If base current of transistor (T2), i.e., ib2 =
transistor T3 is included in totem pole section 0, then the transistors T2 and T4 goes into
(active pull-up element). the OFF-state and the transistor (T3) goes
into the ON-state (base current, ib3 ≠ 0).
Input section: So, the output (Y) becomes logic ‘1’ (or, Y
In input section of the totem pole = 1).
configuration, there are three emitter 2. If base current of transistor (T2), i.e., ib2 ≠
terminals A, B and C. So, we can replace 0, then the transistors T2 and T4 go into
every base to emitter junction with diodes the ON-state and transistor (T3) goes into
D1, D2 and D3. the OFF-state (base current, ib3 = 0). So,
the output (Y) becomes logic ‘0’ (or Y = 0)
for input A = B = C = 1.
Truth table:

A B C T1 T2 T3 T4 Y
(Output)

Fig. 8.48 0 0 0 ON OFF ON OFF 1 (High)

1. If any one of the inputs (A, B and C) is 0 0 1 ON OFF ON OFF 1 (High)
logic ‘0’ (low), then the corresponding
diodes (D1 or D2 or D3) act as forward bias 0 1 0 ON OFF ON OFF 1 (High)
(short circuit), and no current will flow 0 1 1 ON OFF ON OFF 1 (High)
through diode D4 (ib=0).
2. If all the three inputs (A = B = C = 1) are 1 0 0 ON OFF ON OFF 1 (High)
logic ‘1’ (high), then all the three diodes 1 0 1 ON OFF ON OFF 1 (High)
(D1, D2 and D3) act as reverse bias (open
circuit), and current will flow through the 1 1 0 ON OFF ON OFF 1 (High)
diode D4 (ib ≠ 0). 1 1 1 OFF ON OFF ON 0 (Low)
Output section (phase shifter + totem pole): Table 8.12
The output section of the totem pole Advantages of totem pole configuration:
configuration takes the current from the
input section, and that current (ib) becomes y Higher speed of operation
the base current for the transistor (T2). y Higher fan-out
y Low power dissipation
Specifications of TTL:
y Propagation delay (tpd) = 10 nsec
y Power dissipation (Pdiss) = 10 mW
y Fan-out = 10
y Figure of merit (FOM) = 100 pJ
y Noise margin (NM) = 0.4 V

Emitter Coupled Logic (ECL)

y ECL transistors are operated between
cutoff and active region. Hence, it is a
non-saturated logic family.
Fig. 8.49
y Fastest among all the logic families.

190 Logic Families

y In ECL, RTL and DCTL, floating inputs will collector junction of transistor T1 becomes
act as logic ‘0’. reverse bias (open circuit). So, the output
y ECL logic family provides wired OR of T1 becomes zero (X = 0), which makes
operation. the transistor T2 OFF (open circuit), and
y ECL works on negative logic system. the output of the circuit becomes logic ‘1’
(Y = –5.2V).
y If input A = 1 (logic ‘1’), then the base-
emitter junction of transistor T1 becomes
forward bias (short circuit) and base-
collector junction of transistor T1 becomes
forward bias (short circuit). So, the output
of T1 becomes ‘1’ (X = 1), which makes the
transistor T2 ON (short circuit), and the
output of the circuit Y becomes logic ‘0’
(Y = 0-V).
Truth table:

Input Output

A Y

0 1
Fig. 8.50 ECL
1 0
Table 8.13
Previous Years’ Questions y ECL uses negative power supply. Due to
this power supply ripples (or) spikes will
In the circuit shown, A and B are the not affect the operation.
inputs and F is the output. What is the y In ECL, common collector output is used
functionality of the circuit? to improve fan-out.
Specifications of ECL
y Propagation delay (tpd) = 1n sec
y Power dissipation (Pdiss) = 55 mW
y Figure of merit (FOM) = 55 pJ
y Fan-out = 25
y Noise margin (NM) = 0.3 V

Mos Logic Families

Fig. 8.51 MOS logic family is easy to fabricate and

occupies a very small space. It does not
(A) X NOR (B) XOR require resistors and diodes. Because of
(C) Latch (D) SRAM Cell its ease of fabrication and lower power
Solution: (A) dissipation, it is widely used in LSI, VLSI and
ULSI. Because of the very high impedance
y If input A = 0 (logic ‘0’), then the base-
present at MOSFET’s input, the MOS logic
emitter junction of transistor T1 becomes
families are more susceptible to static
forward bias (short circuit), and base-
charge damage.

Logic Families 191

 The MOSFETs are of two types:
1. NMOS (N-Type MOSFET) Previous Years’ Questions
2. PMOS (P-Type MOSFET)
a) The speed of NMOS is three times that In the figure, Boolean expression for the
of PMOS. So, NMOS is widely used in output in terms of inputs A, B and C
fabrication. when the clock ‘Ck’ is high, is:
b) Symbols of NMOS

Fig. 8.52 MOSFET Symbol

VGS > 0 → NMOS is in ON-state → short

circuit
VGS < 0 → NMOS is in OFF-state →
open circuit Fig. 8.55
c) In MOSFET, if gate and drain are shorted, (A) A(B+C) (B) C(B+A)
then MOSFET behaves as a resistor. (C) B(A+C) (D) ABC
Solution: (B)

NMOS NAND Gate

Fig. 8.53

NMOS NOT gate:

Fig. 8.54 NMOS NOT Gate

y If A = 0, then the MOSFET (M2) will be Fig. 8.56 NMOS NAND Gate
in OFF-state, and the output of NMOS
circuit will be logic ‘1’ (Y = 1). y If A = 0 and B = 0, then the MOSFETs
y If A = 1, then the MOSFET (M2) will be in M2 and M3 will be in OFF-state, and the
ON-state, and the output of NMOS circuit output of NMOS circuit will be logic ‘1’ (Y
will be logic ‘0’ (Y = 0). = 1).
y If A = 0 and B = 1, then the MOSFET M2
Truth table: will be in OFF-state and M3 will be in ON-
state and the output of NMOS circuit will
A M2 Y be logic ‘1’ (Y = 1).
y If A = 1 and B = 0, then the MOSFET M2
0 OFF 1
will be in ON-state and M3 will be in OFF-
1 ON 0 state and the output of NMOS circuit will
be logic ‘1’ (Y = 1).
Table 8.14

192 Logic Families

y If A = 1 and B = 1, then the MOSFETs M2 NMOS NOR GATE
and M3 will be ON-state and the output of
NMOS circuit will be logic ‘0’ (Y = 0).

Previous Years’ Questions

For the NMOS logic gate shown in figure,

the logic function implemented is:

Fig. 8.58 NMOS NOR Gate

y If A = 0 and B = 0, then the MOSFETs

M2 and M3 will be in OFF-state, and the
output of NMOS circuit will be logic ‘1’ (Y
= 1).
y If A = 0 and B = 1, then the MOSFET M2
will be in OFF-state, and M3 will be in ON-
state, and the output of NMOS circuit will
be logic ‘0’ (Y = 0).
y If A = 1 and B = 0, then the MOSFET M2
will be in ON-state and M3 will be in OFF-
Fig. 8.57 state and the output of NMOS circuit will
be logic ‘0’ (Y = 0).
(A) ABCDE
y If A = 1 and B = 1, then the MOSFETs
(B) (AB + C)(D + E) M2 and M3 will be in ON-state and the
(C) A(B + C) + DE output of NMOS circuit will be logic ‘0’
(D) (A + B) C + DE (Y = 0).

Solution: (C) Truth table:

A B M2 M3 Y
Truth table:
0 0 OFF OFF 1
A B M2 M3 Y
0 1 OFF ON 0
0 0 OFF OFF 1
1 0 ON OFF 0
0 1 OFF ON 1
1 1 ON ON 0
1 0 ON OFF 1
Table 8.16
1 1 ON ON 0

Table 8.15

Logic Families 193

 Truth table:
Previous Years’ Questions
A B M1 M2 X M3 Y
The output (Y) of the circuit shown in the
0 0 OFF OFF 1 ON 0
figure is:
0 1 OFF ON 1 ON 0

1 0 ON OFF 1 ON 0

1 1 ON ON 0 OFF 1
Table 8.17

So, the output expression, Y = AB.

Example 6:
Find the expression for Y in the given MOSFET
circuit.
Fig. 8.59

(A) A + B + C
(B) A + BC + AC
(C) A + B + C
(D) ABC
Solution: (A)

Example 5:
Fig. 8.62
Find the expression for Y in the given MOSFET
circuit. Solution:

Fig. 8.63
Fig. 8.60

Truth table:
Solution:
A B M1 M2 X M3 Y
0 0 OFF OFF 1 ON 0
0 1 OFF ON 0 OFF 1
1 0 ON OFF 0 OFF 1
1 1 ON ON 0 OFF 1
Table 8.18
Fig. 8.61

194 Logic Families

So, the output expression, Y = A+B. Solution:

Example 7: Method 1:
Find the expression for Y in the given MOSFET
circuit.

Fig. 8.66
Fig. 8.64

Previous Years’ Questions

Previous Years’ Questions
The full forms of the abbreviations TTL
For the circuit shown in the figure, P and and CMOS in reference to logic families
Q are the inputs and Y is the output. are
(A) Triple Transistor logic and Chip Metal
Oxide Semiconductor.
(B) Tristate Transistor Logic and Chip
Metal Oxide Semiconductor.
(C) Transistor Transistor Logic and
Complementary Metal Oxide
Semiconductor.
(D) Tristate Transistor Logic and
Complementary Metal Oxide Silicon.
Solution: (C)

Fig. 8.65

The logic implemented by the circuit is-

(A) XNOR (B) XOR
(C) NOR (D) OR
Solution: (B)

Logic Families 195

 Truth table:

A B C D M1 M2 M3 M4 Y

0 0 0 0 OFF OFF OFF OFF 1

0 0 0 1 OFF OFF OFF ON 1

0 0 1 0 OFF OFF ON OFF 1

0 0 1 1 OFF OFF ON ON 0

0 1 0 0 OFF ON OFF OFF 1

0 1 0 1 OFF ON OFF ON 1

0 1 1 0 OFF ON ON OFF 1

0 1 1 1 OFF ON ON ON 0

1 0 0 0 ON OFF OFF OFF 1

1 0 0 1 ON OFF OFF ON 1

1 0 1 0 ON OFF ON OFF 1

1 0 1 1 ON OFF ON ON 0

1 1 0 0 ON ON OFF OFF 0

1 1 0 1 ON ON OFF ON 0

1 1 1 0 ON ON ON OFF 0

1 1 1 1 ON ON ON ON 0
Table 8.19

Y = ∑m(0, 1, 2, 4, 5, 6, 8, 9, 10) Method 2:

or Y = πM(3, 7, 11, 12, 13, 14, 15)
Realisation using K-map

Fig. 8.67
Fig. 8.68
Y= ( )(
A +B . C +D )

196 Logic Families

Here, X1 = AB PMOS NOR Gate
X2 = CD
Y X 1 + X2
=

Y AB + CD
=
Y = AB . CD
Y= ( )(
A +B . C +D )
PMOS Logic

Fig. 8.71 PMOS NOR Gate

y If A = 0 and B = 0, then the MOSFETs M2

Fig. 8.69 p Channel MOSFET
and M3 will be in ON-state and the output
voltage of PMOS circuit will be 0 volt (Y =
VGS £ 0 → PMOS is in ON-state → short circuit logic ‘1’).
VGS > 0 → PMOS is in OFF-state → open y If A = 0 and B = 1, then the MOSFET M2
circuit will be in ON-state and M3 will be in OFF-
state, and the output voltage will be –VDD
PMOS NOT Gate:
(Y = logic ‘0’).
y If A = 1 and B = 0, then the MOSFET M2 will
be in OFF-state and M3 will be ON-state
and the output voltage will be –VDD (Y =
logic ‘0’).
y If A = 1 and B = 1, v then the MOSFETs
M2 and M3 will be in OFF-state and the
output voltage of PMOS circuit will be –
VDD (Y = logic ‘0’).
Truth table:
Fig. 8.70 PMOS NOT Gate

y If A = 0, then the MOSFET M1 will be in A B Output Voltage Y

ON-state and the output voltage of PMOS
will be 0 volt (Y = logic ‘1’, because supply 0 0 0 Volt 1 (logic ‘1’)
is –VDD). 0 1 –VDD 0 (logic ‘0’)
y If A = 1, then the MOSFET M1 will be in
OFF-state and the output voltage of 1 0 –VDD 0 (logic ‘0’)
PMOS will be –VDD (Y = logic ‘0’, because 1 1 –VDD 0 (logic ‘0’)
supply is –VDD).
Table 8.21
Truth Table:
Cmos Logic
A M1 Output Voltage Y CMOS logic family uses both PMOS and
0 ON 0V 1 (logic ‘1’) NMOS in the same circuit to realise several
advantages over the PMOS and NMOS
1 OFF –VDD 0 (logic ‘0’) families.
Table 8.20

Logic Families 197

 CMOS NAND Gate

Fig. 8.72

CMOS NOT Gate

Fig. 8.74 CMOS NAND Gate

y If A = 0 and B = 0, then the MOSFETs

Fig. 8.73 CMOS NOT Gate M1 and M2 will be in ON-state, MOSFETs
M3 and M4 will be in OFF-state and the
y If A = 0, then the MOSFET M1 (PMOS) will
output will be logic ‘1’ (Y=1).
be in ON-state and M2 (NMOS) will be in
y If A = 0 and B = 1, then the MOSFETs M1
OFF-state, and the output will be logic ‘1’
and M4 will be in ON-state, MOSFETs
(Y = 1).
M2 and M3 will be in OFF-state and the
y If A = 1, then the MOSFET M1 (PMOS) will
output will be logic ‘1’ (Y=1).
be in OFF-state and M2 (NMOS) will be in
y If A = 1 and B = 0, then the MOSFETs M1
ON-state and the output will be logic ‘0’
and M4 will be in OFF-state, MOSFETs M2
(Y = 0).
and M3 will be ON-state and the output
Truth table: will be logic ‘1’ (Y=1).
y If A = 1 and B = 1, then the MOSFETs M1
A M1 (PMOS) M2 (NMOS) Y and M2 will be in OFF-state, MOSFETs M3
and M4 will be in ON-state and the output
0 ON OFF 1 will be logic ‘0’. (Y = 0).
1 OFF ON 0
Table 8.22

198 Logic Families

Truth table:

A B M1 M2 M3 M4 Y

0 0 ON ON OFF OFF 1

0 1 ON OFF OFF ON 1

1 0 OFF ON ON OFF 1

1 1 OFF OFF ON ON 0

Table 8.23

CMOS NOR Gate Truth table:

A B M1 M2 M3 M4 Y

0 0 ON ON OFF OFF 1

0 1 ON OFF OFF ON 0

1 0 OFF ON ON OFF 0

1 1 OFF OFF ON ON 0
Table 8.24

CMOS transmission gate:

y CMOS transmission gate consists of
one NMOS and one PMOS transistor,
connected in parallel.
y It is a bilateral switch which can be
controlled by externally applied logic
Fig. 8.75 CMOS NOR Gate
levels.
y If A = 0 and B = 0, then the MOSFETs
M1 and M2 will be in ON-state, MOSFETs
M3 and M4 will be in OFF-state and the
output will be logic ‘1’ (Y = 1).
y If A = 0 and B = 1, then the MOSFETs M1
and M4 will be in ON-state, MOSFETs
M2 and M3 will be in OFF-state and the
output will be logic ‘0’ (Y = 0).
y If A = 1 and B = 0, then the MOSFETs M1
and M4 will be in OFF-state, MOSFETs M2
Fig. 8.76 CMOS Symbol
and M3 will be in ON-state and the output
will be logic ‘0’ (Y = 0). y In a transmission gate, if enable E = 0,
y If A = 1 and B = 1, then the MOSFETs M1 then NMOS and PMOS both will be in OFF-
and M2 will be in OFF-state, MOSFETs M3 state. So, irrespective of inputs (logic ‘0’
and M4 will be in ON-state and the output or logic ‘1’), the output of the circuit will
will be logic ‘0’ (Y = 0). be in high-impedance state.

Logic Families 199

 y If enable E = 1 and A = 0, then NMOS and y If select line S=0, then transmission gate-
PMOS both will be in ON-state. So, the 1 (TG1) will be in ON-state and TG2 will be
output of the circuit will be the same as in OFF-state. So, the output of the 2×1
the input (works as a short circuit) means MUX will be I0(Y=I0).
Y = 0. y If select line S=1, then transmission gate-
y If enable E = 1 and A = 1, then NMOS and 2 (TG2) will be in ON-state and TG1 will be
PMOS both will be in ON-state. So, the in OFF-state. So, the output of the 2×1
output of the circuit will be Y=1. MUX will be I1(Y=I1).
Truth table: Truth table:

E A Y S Y

0 X High-impedance state 0 I0

1 0 0 1 I1

1 1 1 Table 8.26

Table 8.25 We know that using a multiplexer, we can

implement different gates (AND gate, OR
y 2×1 MUX using transmission gate:
gate, NOR gate, NAND gate etc,). That is why
a multiplexer is called as a universal logic
gate. So, we can say that by using CMOS
transmission gate we can implement any
logic gate.

Fig. 8.77 2×1 MUX Using Transmission Gate

Chapter Summary

y In logic families propagation delay, power dissipation and figure of merit should be as
minimum as possible.
y Fan-out and noise margin should be as maximum as possible.
y Current source: When logic gate output is ‘1’ (transistor off), then the driving gate
supplies current to the load gate at a high state.
y Current sink: When logic gate output is ‘0’ (transistor ON), then the driving gate
receives current from the load gate in a low state.
y HTL is the modified form of DTL.
y RTL and DTL have low speed, low fan-out and high power dissipation.
y HTL has an excellent noise margin and the largest voltage swing.
y ECL is the fastest in the logic families.
y Any floating input in the TTL circuit is considered as logic ‘1’.
y DTL provides wired AND logic.

200 Logic Families

 y DTL provides wired AND logic.
y ECL provides wired OR logic.
y PMOS is called as ‘pull up’ network, and NMOS is called as ‘pull down’ network.
y CMOS is the slowest logic familiy.
y CMOS is also used in a monostable multivibrator.
y Comparison of logic families

Parameter TTL ECL NMOS CMOS

tpd (ns) 10 1 250 70

Pdiss(mW) 10 55 1 0.01

FOM(pJ) 100 55 250 0.7

NM(V) 0.4 0.3 1.5 VDD 2

Fan-out 10 25 5 50
Table 8.27

Practice Questions

1. The open collector of the gates is (C) Switching between cut-off and
connected together as shown in the saturation region
given figure. The logic expression for Y (D) None of the above
will be:
3. Consider the following statements:
I. 
TTL has high switching speed and
good fan-out capability
II. ECL has least propagation delay
III. I2L uses multi-collector transistor
Fig. 8.78 IV. NMOS has more silicon area
(A) (A + B)(C + D) Which of the above statements are
(B) (A +B) + (C +D) correct?
(C) AB + CD (A) I, II and III
(D) A +B + C +D (B) II and IV
(C) I, III and IV
2. ‘ECL’ has very high switching speed (D) I, II, III and IV
because the transistors are:
(A) Switching between active and
4. The circuit with inputs A and B shown in
saturation region
the given figure performs:
(B) Switching between cut-off and active
region

Logic Families 201

 Fig. 8.79

(A) AND Operation (A) Y =( A + B)( A + C )(B + C )

(B) NAND Operation
(B) Y = (B + C ) . A + ( A + C ) B
(C) OR Operation
(D) NOR Operation ( A BC )(B + AC )
(C) Y =+

5. A logic family has threshold voltage VR ( AB + C )( AC + B)

(D) Y =
= 1V, minimum guaranteed output high
voltage VOH = 4V, minimum accepted 7. Match List 1 (logic gates) with List 2
input high voltage VIH = 2V, maximum (operations) and select the correct
guaranteed output low voltage VOL = 0.5 answer using the codes given below:
and maximum accepted input low voltage List 1 List 2
VIL = 1.5 V. Its noise margin is ______ volt. A. TTL I. More logical swing
6. Find the expression for Y in the given B. ECL II. Low power dissipation
MOSFET circuit. C. DCTL III. Current hogging
D. CMOS IV. NOR/OR output
V. Totem-pole output
Codes:
A B C D
(A) III II V I
(B) III II IV V
(C) II III IV V
(D) V IV III II

Fig. 8.80

Practice Solutions

1. Solution: (C) 2. Solution: (B) 3. Solution: (B) 4. Solution: (D)

5. Solution: 1 6. Solution: (A) 7. Solution: (D)

202 Logic Families