CODE: GR22A2067 GR 22 SET - 1
GR11D5104
II B.Tech I Semester Regular Examinations, January/February 2024
GR11D5104
Digital Logic Design
GR11D5104
(Common to CSE, IT, AIML & DS)
GR11D5104
Time: 3 hours Max Marks: 60
GR11D5104
Instructions:
1. Question paper comprises of Part-A and Part-B
2. Part-A (for 10 marks) must be answered at one place in the answer book.
3. Part-B (for 50 marks) consists of five questions with internal choice, answer all questions.
4. CO means Course Outcomes. BL means Blooms Taxonomy Levels.
PART – A
(Answer ALL questions. All questions carry equal marks )
10 * 1 = 10 Marks
1. a) Using 10’s complement subtract 3456-53243 1M CO1 BL4
b) Convert (10101011)2 to its hexadecimal equivalent. 1M CO1 BL3
c) Explain about Universal gates. 1M CO2 BL2
d) Define Maxterm and give an example for 2 variables. 1M CO2 BL1
e) Discuss about Multiplexer 1M CO3 BL2
f) Write truth table for half adder 1M CO3 BL1
g) Give Excitation tale for D Flip-Flop 1M CO4 BL2
h) What is shift register. 1M CO4 BL1
i) What is RAM. 1M CO5 BL1
j) Draw the block diagram of memory cell. 1M CO5 BL1
PART – B
(Answer ALL questions. All questions carry equal marks)
5 * 10 = 50 Marks
2. a) What are various logic gates give representation along with truth tables. 5M CO1 BL1
b) Determine single error Hamming code for the information 10111110. 5M CO1 BL3
OR
3. a) Perform the following using BCD arithmetic 5M CO1 BL2
i) (1263)10 +(9687)10 ii) (7672)10+(3378)10
b) Solve the following using 2`s complement subtraction 5M CO1 BL3
11010-1101
Page1 of 2
CODE: GR22A2067 GR 22 SET - 1
GR11D5104
4. a) Express the following function as a sum of min terms ad product of max 5M CO2 BL3
GR11D5104
terms f(a,b,c,d): a’b+ab’d+c’d
GR11D5104
b) Simplify using K-map f(A,B,C,D): m(0,6,8,13,14)+d(2,4,10) 5M CO2 BL2
GR11D5104
GR11D5104 OR
5. a) Implement the following with NAND gates F(X,Y,Z): m(1,2,3,4,5,7) 5M CO2 BL4
b) Reduce the expression using K-Map F(x,y,z,w)= x(y+z’) (x+y’) 5M CO2 BL3
(y+z+w’)
6. a) Explain carry look a head adder with neat diagram 5M CO3 BL2
b) Implement Boolean function with multiplexer f(X,Y,Z):m(2,4,6) 5M CO3 BL4
OR
7. a) Define full adder design full adder with two half adders 5M CO3 BL1
b) Draw and explain the operation of 3 x 8 decoder 5M CO3 BL1
8. a) Write SR filp-flop,JK flip-flop,T flip-flop characteristic table 5M CO4 BL2
b) Design 4 bit synchronous counter using T Flip-Flops 5M CO4 BL4
OR
9. a) Explain about Universal shift register 5M CO4 BL2
b) Discuss about 4 bit Ripple counter 5M CO4 BL2
10. a) Design a PLA for the following logical functions. 5M CO5 BL4
Y1 = AB + A’CB’; Y2 = AB’C + AB + AC’; Y3 = AB + BC + CA
b) What is HDL write HDL for 4*1 Mux 5M CO5 BL3
OR
11. a) Write short notes on i)FPGA ii)PROM 5M CO5 BL1
b) Draw the block diagram of RAM and ROM chips 5M CO5 BL2
*****
Page2 of 2
