Spring-23 (solve)

Group A
1 a) Discuss the clocking methodology for datapath
implementation.
Ans:
1b) Suppose you are given an instruction sub
Ss2,$12,513. Describe the complete operation of the
datapath using the instruction with a figure.
Ans:
Description:
1. The instruction is fetched, and the PC is incremented.
2. Two registers, $t2 and $t3, are read from the register file and the main control
unit computes the setting of the control lines during this step also.
3. The ALU operates on the data read from the register file, using the function
code (bits 5:0, which is the funct field, of the instruction) to generate the ALU
function.
4. The result from the ALU is written into the register file using bits 15:11 of the
instruction to select the destination register ($t1).

Or

Suppose you are given an instruction Iw Ss1,100(Ss3).

Describe the complete operation of the datapath using
the instruction with a figure.
Ans: Same as previous one

1c) What are the advantages of multicycle

implementation over single cycle?
Ans:
Despite the performance advantage of single-cycle implementations, there are several
benefits to using a multicycle implementation, especially for simpler or less resource-
intensive systems:
 1. Simpler Hardware Design:

 Multicycle designs require fewer functional units and control logic compared to single-
cycle implementations. This is because the instruction execution is divided into smaller,
independent stages.
 The simpler design makes it easier to implement and debug, particularly for smaller
systems where resources and budget might be limited.

2. Lower Cost:

 Due to the simpler design and fewer components, multicycle implementations are
typically less expensive to manufacture than single-cycle counterparts.
 This cost advantage is especially beneficial for budget-constrained projects or mass-
produced devices.

3. Increased Flexibility:

 Multicycle design allows for more flexibility in adapting to different instruction types and
functionalities.
 By adding or modifying individual stages, the data path can be easily customized to
support additional features or instruction sets.

4. Lower Power Consumption:

 As multicycle implementations involve fewer active components and shorter execution

times, they typically consume less power than single-cycle designs.
 This is a significant advantage for battery-powered devices or systems where energy
efficiency is a critical concern.

2a) Design a single cycle data path for handling R-type

instruction of MIPS.

Ans:
Fig: Design of a single cycle datapath.
Or,
Design a multi-cycle data path for handling basic
instruction of MIPS.
2b) Describe all temporary register and multiplexors of
Multicycle Datapath.
Ans:
Temporary Registers:

1. Instruction Register (IR):

● Holds the fetched instruction after it's retrieved from memory.

● Used by the control unit to decode the instruction and determine the next
steps.

● Typically doesn't change its content throughout the execution cycle.

2. Memory Data Register (MDR):

● Stores data transferred between the CPU and memory.

● Acts as a buffer during read and write operations.

● Content changes depending on the data being transferred.

3. A Register and B Register:

● Hold the operands retrieved from the register file for the ALU operation.

● Content changes in each cycle based on the instructions being processed.

4. ALU Output Register (ALUOut):

● Stores the result of the ALU operation.

● Used by other components like the memory or register file in subsequent

cycles.

● Content changes with each ALU operation.

5. Program Counter (PC):

● Stores the address of the next instruction to be fetched.

● Updated in each cycle based on the instruction being executed.

● Plays a crucial role in controlling the flow of program execution.

Multiplexers: 1. Memory Address Multiplexer:

● Selects the address of data to be read or written from/to memory.

● Can receive inputs from the PC (for instruction fetch), ALUOut (for data address
calculation), or other registers depending on the instruction.

2. ALU Input Multiplexer:

● Selects the first operand for the ALU operation.

● Can receive inputs from the A register, sign-extended immediate value, or other
sources depending on the instruction.

3. ALU Second Operand Multiplexer:

● Similar to the ALU Input Multiplexer, it selects the second operand for the ALU
operation.

● Receives inputs from the B register, sign-extended immediate value, or other

sources depending on the instruction.

4. Register Write Multiplexer:

● Selects the data to be written to the register file.

● Can receive inputs from the ALUOut, MDR, or other sources depending on the
instruction.
 2c) Do you think that the functions of memory data
register and instruction register are the same? If not then
how?

Ans:
No, the functions of the memory data register (MDR) and the instruction
register (IR) are not the same. While both play crucial roles in CPU
operation, they serve distinct purposes:

MDR:

 Function: Stores data being transferred between the CPU and memory.
 Data type: Data (e.g., integers, characters)
 Source of data: Memory or CPU
 Destination of data: Memory or CPU
 Role in CPU cycle: Memory fetch and store stages

IR:

 Function: Stores the current instruction that the CPU is about to execute.
 Data type: Instructions (machine code)
 Source of data: Memory
 Destination of data: Control unit
 Role in CPU cycle: Decode and execute stages
 Or,

Why a single-cycle implementation is not used? justify

the answer.

Ans:
 Group B

3a)Does any Pipeline Stall arise here for the following

instructions-
MUL R1,R2,R3
SUB R3,R1,R4
ADD R4,R5,R6
Ans:
 3b) What do you mean by pipelining? Describe
advantages of pipelining architecture.
Ans:
Pipelining is a technique in computer architecture that overlaps the
execution of different instructions to improve the overall performance of the
processor. It works by breaking down the execution of an instruction into
smaller, independent stages and then executing each stage simultaneously
for different instructions. This allows the processor to keep multiple
instructions in various stages of execution, maximizing the utilization of its
resources and reducing idle time.

Advantages of Pipelining Architecture:

 Increased performance: By overlapping instruction execution, pipelining

can significantly improve the performance of the processor, often by 50%
or more.
 Improved throughput: Pipelining increases the number of instructions
executed per unit time, leading to higher throughput.
 Reduced idle time: By keeping the functional units busy with different
stages of various instructions, pipelining reduces idle time and improves
resource utilization.
 Increased clock speed: Pipelined architectures can allow for higher clock
speeds because the critical path (the longest stage) of each instruction is
shorter.
 Simplified control logic: Pipelined designs often require simpler control logic
compared to non-pipelined designs, making them easier to implement.
 3c) Dynamic pipelining is more complecated than the
traditional or static pipelining - why?

Ans:
Dynamic pipelining is more complex than static pipelining because it
requires additional hardware and control logic to dynamically determine the
execution flow of instructions based on runtime conditions. This complexity
stems from the need to:

 Identify data dependencies between instructions at runtime to avoid

pipeline stalls.
 Predict branch outcomes to avoid flushing the pipeline and re-fetching
instructions when a branch is taken.
 Speculatively execute instructions based on predicted branch outcomes,
potentially leading to wasted work if the prediction is incorrect.

4a) Write short note on structural hazard.

Ans:
A structural hazard occurs in a pipelined processor when two or more
instructions in the pipeline need to access the same resource at the same
time. This can cause a stall in the pipeline as the instructions compete for
the resource, preventing further instructions from being executed until the
conflict is resolved.
 Or,

Write short note on memory hierarchy.

Ans:
The memory hierarchy is a layered system that organizes memory based
on its speed and capacity. It aims to provide a balance between the fast
access needed for frequently used data and the large storage capacity
required for all data.

4b) Explain interrupt and its classes with necessary

diagram.

Ans:
Interrupt: An interrupt is a signal that temporarily suspends the current
execution of a program and directs the processor's attention to a higher-
priority event. This event could be:

 Hardware interrupt: Generated by a hardware device, such as a keyboard,

timer, or network card, requiring immediate attention.
 Software interrupt: Generated by a program itself, typically for system calls
or other internal requests.

Classes of Interrupts:

Interrupts can be classified into different categories based on their source

and characteristics:
 External vs. Internal:
o External: Generated by external devices connected to the processor.
o Internal: Generated by software within the processor.
 Synchronous vs. Asynchronous:
o Synchronous: Occur at predictable times and are often related to the
program's execution or the system clock.
o Asynchronous: Occur at unpredictable times and are not related to the
program's execution.
 Maskable vs. Non-maskable:
o Maskable: Can be temporarily disabled by the processor to prevent them
from interrupting the current program.
o Non-maskable: Cannot be disabled and will always interrupt the current
program.

Interrupt Handling:

1. Interrupt Recognition: The processor receives the interrupt signal and

determines its source and priority.
2. Interrupt Acknowledgement: The processor sends an acknowledgement
signal to the interrupting device.
3. Interrupt Service Routine (ISR): The current program's execution is saved,
and a special program called the ISR is loaded and executed to handle the
interrupt.
4. Interrupt Return: After the ISR finishes, the processor restores the saved
state of the interrupted program and resumes its execution.
Diagram:

+----------+
| Interrupt |
+----------+
|
v
+---------------------+
| Processor |
+---------------------+
| |
v v
+--------------------+ +--------------------+
| Control Unit | | Interrupt Logic |
+--------------------+ +--------------------+
| | |
v v v
+---------+ +---------+ +---------+ +---------+
| ALU | | Registers | | Memory | | I/O Devices
|
+---------+ +---------+ +---------+ +---------+

Or,
What is TLB? Discuss the operation of paging and TLB
using flow diagram?
Ans:
TLB (Translation Lookaside Buffer) is a small, high-speed memory cache
that stores recent virtual-to-physical address translations used by the
paging memory management technique. By storing these translations, TLB
significantly improves the performance of address translation, which is a
crucial step in memory access.
 Paging is a memory management technique that divides the logical
address space of a program into fixed-size blocks called pages. These
pages are then mapped to physical memory frames, which are also fixed-
size blocks. This allows for more efficient memory utilization and facilitates
processes sharing memory without interfering with each other.

TLB Operation:

1. When a process references a memory address, the processor first checks

the TLB to see if a translation for that address is already present.
2. If a translation is found (TLB hit), the physical address is retrieved from the
TLB and used to access memory directly. This avoids the need to access
the slower page table, significantly reducing the time required for memory
access.
3. If a translation is not found (TLB miss), the processor must consult the
page table to find the corresponding physical address. This involves a
multi-level lookup process, which is much slower than accessing the TLB.
4. Once the physical address is found in the page table, it is stored in the TLB
for future reference. This helps to improve the performance of subsequent
address translations for the same page.

Flow Diagram:

+--------------------------------------+
| Memory Address Reference |
+--------------------------------------+
|
v
+-------+ +---------+ +-------+
| TLB | ----> | Page Table | ----> | Memory |
+-------+ +---------+ +-------+
| |
v v
+-----+ +-----+
| Hit | ----> | Miss |
+-----+ +-----+
| |
v v
+-------------+ +---------+
| Physical Address | ----> | Memory Access |
+-------------+ +---------+
4c) What is DMA controller? Describe the configuration
of DMA controller.
Ans:
Direct Memory Access (DMA) controller is a specialized hardware device that
allows Input/Output (I/O) devices to access main memory directly, bypassing the
CPU. This significantly improves the efficiency of data transfer by freeing up the
CPU for other tasks.
Configuration of a DMA Controller: The configuration of a DMA controller
typically includes the following components:
1. DMA registers: These registers store information about the DMA transfer, such
as the source address, destination address, transfer size, and control information.
2. Counter: This counter keeps track of the number of bytes transferred during
the DMA operation.
3. Burst mode control: This feature allows the controller to transfer data in bursts,
improving efficiency by minimizing bus overhead.
4. Arbitration logic: This logic resolves conflicts when multiple devices request to
use the DMA controller simultaneously.
5. Transfer modes: Several transfer modes may be available, including block
mode, cycle stealing mode, and burst mode. These modes determine how the
DMA controller accesses the memory and interacts with the CPU.
6. Interrupt generation: The DMA controller generates interrupts to notify the
CPU when the transfer is complete or if any errors occur.
7. Bus interface: This interface allows the DMA controller to communicate with
the memory and other components on the system bus
5a) Discuss the clocking methodology with relevant
diagram.

Ans:

A clocking methodology defines when signals can be

read and when they can be written. It is important to
specify the timing of reads and writes because, if a signal
is written at the same time it is read, the value of the
read could correspond to the old value, the newly
written value, or even some mix of the two! Needless to
say, computer designs cannot tolerate such
unpredictability. A clocking methodology is designed to
prevent this circumstance.

Clocking methodology is the approach used to

determine when data is valid and stable relative to the
clock.
Clocking Methodology Diagram:

+----------------+
| Clock Source |
+----------------+
|
v
+---------+
| Clock Driver |
+---------+
|
v
+--------+ +--------+ +--------+
| Clock | ----> | Circuit 1 | ----> | Output 1 |
+--------+ +--------+ +--------+
| | |
v v v
+--------+ +--------+ +--------+
| Clock | ----> | Circuit 2 | ----> | Output 2 |
+--------+ +--------+ +--------+
| | |
v v v
...

5b) Explain the handshaking protocol with diagram.

Ans:
 Or
Explain the direct mapped cache system with figure.