1.

Capture the schematic of 2-input CMOS NOR gate having similar delay as that of CMOS
inverter computed in experiment above. Verify the functionality of NOR gate and also find
out the delay td for all four possible combinations of input vectors. Table the results. Increase
the drive strength to 2X and tabulate the results.

2. Construct the schematic of the Boolean Expression Y = AB+CD + E using CMOS Logic.
Verify the functionality of the expression find out the delay td for some combination of input
vectors. Tabulate the results.

3. Construct the schematic of CMOS inverter with load capacitance of 0.1pF and set the widths
of inverter with Wn = Wp, length at selected technology. Carry out the following:
1. Set the input signal to a pulse with rise time, fall time of 1ns and pulse width of 10ns and
the time period of 20ns and plot the input voltage and output voltage of designed
inverter?
2. From the simulation result compute tpHL, tpLH and td and tabulate.
3. Draw layout of inverter with Wp/Wn = 40/20, use optimum layout methods. Verify for
DRC and LVS, extract parasitic and perform post layout simulations, compare the results
with pre layout simulations and compare the results.

4. Construct the schematic of the Boolean Expression Y = AB+CD + E using CMOS Logic.
Verify the functionality of the expression find out the delay td for some combination of input
vectors. Tabulate the results.

5. Construct the schematic of CMOS inverter with load capacitance of 0.1pF and set the widths
of inverter with Wn = 2Wp, length at selected technology. Carry out the following:
1. Set the input signal to a pulse with rise time, fall time of 1ns and pulse width of 10ns and
the time period of 20ns and plot the input voltage and output voltage of designed
inverter?
2. From the simulation result compute tpHL, tpLH and td and tabulate.
3. Draw layout of inverter with Wp/Wn = 40/20, use optimum layout methods. Verify for
DRC and LVS, extract parasitic and perform post layout simulations, compare the results
with pre layout simulations and compare the results.

6. Capture the schematic of 2-input CMOS NOR gate having similar delay as that of CMOS
inverter computed in experiment above. Verify the functionality of NOR gate and also find
out the delay td for all four possible combinations of input vectors. Table the results. Increase
the drive strength to 2X and tabulate the results.

7. Construct the schematic of CMOS inverter with load capacitance of 0.1pF and set the widths
of inverter with Wn = Wp/2, length at selected technology. Carry out the following:
1. Set the input signal to a pulse with rise time, fall time of 1ns and pulse width of 10ns and
the time period of 20ns and plot the input voltage and output voltage of designed
inverter?
2. From the simulation result compute tpHL, tpLH and td and tabulate.
3. Draw layout of inverter with Wp/Wn = 40/20, use optimum layout methods. Verify for
DRC and LVS, extract parasitic and perform post layout simulations, compare the results
with pre layout simulations and compare the results.

8. Capture the schematic of 2-input CMOS NOR gate having similar delay as that of CMOS
inverter computed in experiment above. Verify the functionality of NOR gate and find out the
delay td for all four possible combinations of input vectors. Table the results. Increase the
drive strength to 4X and tabulate the results.
1. Capture the schematic of 2-input CMOS NOR gate having similar delay as that of CMOS
inverter computed in experiment above. Verify the functionality of NOR gate and also find
out the delay td for all four possible combinations of input vectors. Table the results. Increase
the drive strength to 4X and tabulate the results.

2. Construct the schematic of the Boolean Expression Y = AB+CD + E using CMOS Logic.
Verify the functionality of the expression find out the delay td for some combination of input
vectors. Tabulate the results.

3. Construct the schematic of CMOS inverter with load capacitance of 0.1pF and set the widths
of inverter with Wn = Wp, length at selected technology. Carry out the following:
1. Set the input signal to a pulse with rise time, fall time of 1ns and pulse width of 10ns and
the time period of 20ns and plot the input voltage and output voltage of designed
inverter?
2. From the simulation result compute tpHL, tpLH and td and tabulate.
3. Draw layout of inverter with Wp/Wn = 40/20, use optimum layout methods. Verify for
DRC and LVS, extract parasitic and perform post layout simulations, compare the results
with pre layout simulations and compare the results.

4. Construct the schematic of the Boolean Expression Y = AB+CD + E using CMOS Logic.
Verify the functionality of the expression find out the delay td for some combination of input
vectors. Tabulate the results.

5. Construct the schematic of CMOS inverter with load capacitance of 0.1pF and set the widths
of inverter with Wn = 2Wp, length at selected technology. Carry out the following:
1. Set the input signal to a pulse with rise time, fall time of 1ns and pulse width of 10ns and
the time period of 20ns and plot the input voltage and output voltage of designed
inverter?
2. From the simulation result compute tpHL, tpLH and td and tabulate.
3. Draw layout of inverter with Wp/Wn = 40/20, use optimum layout methods. Verify for
DRC and LVS, extract parasitic and perform post layout simulations, compare the results
with pre layout simulations and compare the results.

6. Capture the schematic of 2-input CMOS NOR gate having similar delay as that of CMOS
inverter computed in experiment above. Verify the functionality of NOR gate and also find
out the delay td for all four possible combinations of input vectors. Table the results. Increase
the drive strength to 2X and tabulate the results.

7. Construct the schematic of CMOS inverter with load capacitance of 0.1pF and set the widths
of inverter with Wn = Wp/2, length at selected technology. Carry out the following:
1. Set the input signal to a pulse with rise time, fall time of 1ns and pulse width of 10ns and
the time period of 20ns and plot the input voltage and output voltage of designed
inverter?
2. From the simulation result compute tpHL, tpLH and td and tabulate.
3. Draw layout of inverter with Wp/Wn = 40/20, use optimum layout methods. Verify for
DRC and LVS, extract parasitic and perform post layout simulations, compare the results
with pre layout simulations and compare the results.

8. Capture the schematic of 2-input CMOS NOR gate having similar delay as that of CMOS
inverter computed in experiment above. Verify the functionality of NOR gate and find out the
delay td for all four possible combinations of input vectors. Table the results. Increase the
drive strength to 4X and tabulate the results.
1. Write a Verilog description for a 4-Bit Adder, Verify the Functionality using Test-
bench, Synthesize the design by setting proper constraints and generate the gate level
netlist. From the report generated identify Critical path, Maximum delay, Total
number of cells, Power requirement and Total area required

2. Write Verilog code for 4-Bit Shift and add Multiplier and Verify the Functionality
using Test-bench. Synthesize the design by setting proper constraints and obtain the
gate level netlist. From the report generated identify Critical path, Maximum delay,
Total number of cells, Power requirement and Total area required.

3. Write verilog code for 32-bit ALU supporting four logical and four arithmetic
operations Verify functionality using Test-bench Synthesize the design targeting
suitable library and by setting area and timing constraints, Tabulate the Area, Power
and Delay for the Synthesized netlist Identify Critical path.

4. Write the Verilog description for Flip-Flops (SR and JK ) Verify the Functionality
using Test-bench, Synthesize the design by setting proper constraints and obtain the
gate level netlist. From the report gate level netlist identify Critical path, Maximum
delay, Total number of cells, Power requirement and Total area required. Verify the
functionality using Gate level netlist and compare the results at RTL and gate level
netlist.

5. Write Verilog Code for Four bit Synchronous MOD-N counter with Asynchronous
reset, Verify functionality using Test-bench, Synthesize the design targeting suitable
library and by setting area and timing constraints and Tabulate the Area, Power and
Delay for the Synthesized netlist.

6. Construct the schematic of Common Source Amplifier with PMOS Current Mirror
Load and find its transient response and AC response? Measure the Unit Gain
Bandwidth (UGB), amplification factor by varying transistor geometries, study the
impact of variation in width to UGB.
b) Draw Layout of common source amplifier, use optimum layout methods. Verify for
DRC & LVS, extract parasitic and perform post layout simulations, compare the
results with prelayout simulations. Record the observations.

7. Construct the schematic of two-stage operational amplifier and measure the

following: i.Unity gain Bandwidth ii. dB Bandwidth iii. Gain Margin and phase
margin with and without coupling capacitance iv. Use the op-amp in the inverting and
non-inverting configuration and verify its functionality. v. Study the UGB, 3dB
bandwidth, gain and power requirement in op-amp by varying the stage wise
transistor geometries and record the observations.
1. Write a Verilog description for a 4-Bit Adder, Verify the Functionality using Test-
bench, Synthesize the design by setting proper constraints and generate the gate level
netlist. From the report generated identify Critical path, Maximum delay, Total
number of cells, Power requirement and Total area required

2. Write Verilog code for 4-Bit Shift and add Multiplier and Verify the Functionality
using Test-bench. Synthesize the design by setting proper constraints and obtain the
gate level netlist. From the report generated identify Critical path, Maximum delay,
Total number of cells, Power requirement and Total area required.

3. Write verilog code for 32-bit ALU supporting four logical and four arithmetic
operations Verify functionality using Test-bench Synthesize the design targeting
suitable library and by setting area and timing constraints, Tabulate the Area, Power
and Delay for the Synthesized netlist Identify Critical path.

4. Write the Verilog description for Flip-Flops (SR and D ) Verify the Functionality
using Test-bench, Synthesize the design by setting proper constraints and obtain the
gate level netlist. From the report gate level netlist identify Critical path, Maximum
delay, Total number of cells, Power requirement and Total area required. Verify the
functionality using Gate level netlist and compare the results at RTL and gate level
netlist.

5. Write Verilog Code for Four bit Synchronous MOD-N counter with Asynchronous
reset, Verify functionality using Test-bench, Synthesize the design targeting suitable
library and by setting area and timing constraints and Tabulate the Area, Power and
Delay for the Synthesized netlist.

6. Construct the schematic of Common Source Amplifier with PMOS Current Mirror
Load and find its transient response and AC response? Measure the Unit Gain
Bandwidth (UGB), amplification factor by varying transistor geometries, study the
impact of variation in width to UGB.
b) Draw Layout of common source amplifier, use optimum layout methods. Verify for
DRC & LVS, extract parasitic and perform post layout simulations, compare the
results with prelayout simulations. Record the observations.

7. Construct the schematic of two-stage operational amplifier and measure the

following: i.Unity gain Bandwidth ii. dB Bandwidth iii. Gain Margin and phase
margin with and without coupling capacitance iv. Use the op-amp in the inverting and
non-inverting configuration and verify its functionality. v. Study the UGB, 3dB
bandwidth, gain and power requirement in op-amp by varying the stage wise
transistor geometries and record the observations.
1. Write a Verilog description for a 4-Bit Adder, Verify the Functionality using Test-
bench, Synthesize the design by setting proper constraints and generate the gate level
netlist. From the report generated identify Critical path, Maximum delay, Total
number of cells, Power requirement and Total area required

2. Write Verilog code for 4-Bit Shift and add Multiplier and Verify the Functionality
using Test-bench. Synthesize the design by setting proper constraints and obtain the
gate level netlist. From the report generated identify Critical path, Maximum delay,
Total number of cells, Power requirement and Total area required.

3. Write verilog code for 32-bit ALU supporting four logical and four arithmetic
operations Verify functionality using Test-bench Synthesize the design targeting
suitable library and by setting area and timing constraints, Tabulate the Area, Power
and Delay for the Synthesized netlist Identify Critical path.

4. Write the Verilog description for Flip-Flops (D and JK ) Verify the Functionality
using Test-bench, Synthesize the design by setting proper constraints and obtain the
gate level netlist. From the report gate level netlist identify Critical path, Maximum
delay, Total number of cells, Power requirement and Total area required. Verify the
functionality using Gate level netlist and compare the results at RTL and gate level
netlist.

5. Write Verilog Code for Four bit Synchronous MOD-N counter with Asynchronous
reset, Verify functionality using Test-bench, Synthesize the design targeting suitable
library and by setting area and timing constraints and Tabulate the Area, Power and
Delay for the Synthesized netlist.

6. Construct the schematic of Common Source Amplifier with PMOS Current Mirror
Load and find its transient response and AC response? Measure the Unit Gain
Bandwidth (UGB), amplification factor by varying transistor geometries, study the
impact of variation in width to UGB.
b) Draw Layout of common source amplifier, use optimum layout methods. Verify for
DRC & LVS, extract parasitic and perform post layout simulations, compare the
results with prelayout simulations. Record the observations.

7. Construct the schematic of two-stage operational amplifier and measure the

following: i.Unity gain Bandwidth ii. dB Bandwidth iii. Gain Margin and phase
margin with and without coupling capacitance iv. Use the op-amp in the inverting and
non-inverting configuration and verify its functionality. v. Study the UGB, 3dB
bandwidth, gain and power requirement in op-amp by varying the stage wise
transistor geometries and record the observations.
1. Write a Verilog description for a 4-Bit Adder, Verify the Functionality using Test-
bench, Synthesize the design by setting proper constraints and generate the gate level
netlist. From the report generated identify Critical path, Maximum delay, Total
number of cells, Power requirement and Total area required

2. Write Verilog code for 4-Bit Shift and add Multiplier and Verify the Functionality
using Test-bench. Synthesize the design by setting proper constraints and obtain the
gate level netlist. From the report generated identify Critical path, Maximum delay,
Total number of cells, Power requirement and Total area required.

3. Write verilog code for 32-bit ALU supporting four logical and four arithmetic
operations Verify functionality using Test-bench Synthesize the design targeting
suitable library and by setting area and timing constraints, Tabulate the Area, Power
and Delay for the Synthesized netlist Identify Critical path.

4. Write the Verilog description for Flip-Flops (SR and JK ) Verify the Functionality
using Test-bench, Synthesize the design by setting proper constraints and obtain the
gate level netlist. From the report gate level netlist identify Critical path, Maximum
delay, Total number of cells, Power requirement and Total area required. Verify the
functionality using Gate level netlist and compare the results at RTL and gate level
netlist.

5. Write Verilog Code for Four bit Synchronous MOD-N counter with Asynchronous
reset, Verify functionality using Test-bench, Synthesize the design targeting suitable
library and by setting area and timing constraints and Tabulate the Area, Power and
Delay for the Synthesized netlist.

6. Construct the schematic of Common Source Amplifier with PMOS Current Mirror
Load and find its transient response and AC response? Measure the Unit Gain
Bandwidth (UGB), amplification factor by varying transistor geometries, study the
impact of variation in width to UGB.
b) Draw Layout of common source amplifier, use optimum layout methods. Verify for
DRC & LVS, extract parasitic and perform post layout simulations, compare the
results with prelayout simulations. Record the observations.

7. Construct the schematic of two-stage operational amplifier and measure the

following: i.Unity gain Bandwidth ii. dB Bandwidth iii. Gain Margin and phase
margin with and without coupling capacitance iv. Use the op-amp in the inverting and
non-inverting configuration and verify its functionality. v. Study the UGB, 3dB
bandwidth, gain and power requirement in op-amp by varying the stage wise
transistor geometries and record the observations.