Instruction Set Architecture (ISA)
Definition: ISA is the complete specification of how to program a computer - it's the interface
between hardware and software. It defines the supported instructions, registers, memory
organization, addressing modes, data types, and how the processor interacts with I/O.
Components of ISA
1. Instruction Set
o Complete list of valid instructions
o Operation codes (opcodes)
o Instruction formats
o Instruction lengths
o Available addressing modes
2. Data Types & Formats
o Supported data sizes (byte, word, etc.)
o Integer representations
o Floating-point formats
o Character encodings
o Special data types
3. Registers
o Number of registers
o Register types
o Register sizes
o Special-purpose registers
o Register conventions
4. Memory Organization
o Address space
o Memory alignment
o Byte ordering (endianness)
o Memory segmentation
o Memory protection
ISA Classifications
1. Based on Complexity
a) CISC (Complex Instruction Set Computing)
o Many specialized instructions
o Variable instruction length
o Complex addressing modes
o Hardware handles complexity
o Example: x86 architecture
; CISC example (x86)
MOV EAX, [EBX + ECX*4 + 100] ; Complex single instruction
b) RISC (Reduced Instruction Set Computing)
o Fewer, simpler instructions
o Fixed instruction length
o Load-store architecture
o More compiler optimization
o Example: ARM architecture
; RISC example (ARM-like)
LDR R1, [R2] ; Load
ADD R3, R1, R4 ; Compute
STR R3, [R5] ; Store
Key ISA Characteristics
• Instruction Format
• Instruction Categories
• Memory Addressing (Addressing modes)
What are Registers?
• High-speed storage locations within CPU
• Direct access by processor
• Faster than memory access
• Limited in number
• Used for temporary data storage
• Critical for instruction execution
Types of Registers
1. General Purpose Registers
o Data manipulation
o Arithmetic operations
o Address calculations
o Temporary storage
2. Segment Registers
o Memory segmentation
o Code segment (CS)
o Data segment (DS)
o Stack segment (SS)
o Extra segment (ES)
3. Control Registers
o Instruction pointer (IP)
o Flags register
o Stack pointer (SP)
o Base pointer (BP)
4. Index Registers
o Source index (SI)
o Destination index (DI)
o Array operations
o String manipulation
Intel 8086 Processor Registers in Detail
1. General Purpose Registers (16-bit)
a) AX (Accumulator)
o Primary arithmetic operations
o I/O operations
o String operations
o Divided into:
§ AH (high byte)
§ AL (low byte)
b) BX (Base)
o Base address calculations
o Pointer operations
o Divided into:
§ BH (high byte)
§ BL (low byte)
c) CX (Counter)
o Loop operations
o String operations
o Shift/rotate instructions
o Divided into:
§ CH (high byte)
§ CL (low byte)
d) DX (Data)
o I/O port addressing
o Multiply/divide operations
o Divided into:
§ DH (high byte)
§ DL (low byte)
2. Segment Registers (16-bit)
CS (Code Segment) : Points to program code
DS (Data Segment) : Points to data
SS (Stack Segment) : Points to stack
ES (Extra Segment) : Additional data pointer
3. Index and Pointer Registers (16-bit)
SI (Source Index) : Source for string operations
DI (Destination Index) : Destination for string operations
BP (Base Pointer) : Stack frame reference
SP (Stack Pointer) : Top of stack pointer
IP (Instruction Pointer): Next instruction address
4. Flags Register (16-bit)
o Status flags:
§ CF (Carry Flag)
§ PF (Parity Flag)
§ AF (Auxiliary Flag)
§ ZF (Zero Flag)
§ SF (Sign Flag)
§ OF (Overflow Flag)
o Control flags:
§ TF (Trap Flag)
§ IF (Interrupt Flag)
§ DF (Direction Flag)
Instruction Set Architecture (ISA)
1. Basic Instruction Types
a) Data Movement
MOV destination, source ; Basic data transfer
PUSH source ; Push onto stack
POP destination ; Pop from stack
XCHG operand1, operand2 ; Exchange data
b) Arithmetic
ADD destination, source ; Addition
SUB destination, source ; Subtraction
MUL source ; Unsigned multiplication
DIV source ; Unsigned division
INC destination ; Increment
DEC destination ; Decrement
c) Logical
AND destination, source ; Logical AND
OR destination, source ; Logical OR
XOR destination, source ; Logical XOR
NOT destination ; Logical NOT
What are Addressing Modes?
Addressing modes are methods that specify how the processor calculates the effective memory
address or locates the data needed for instruction execution. They determine:
• Where the data is located
• How to access the data
• What manipulations are needed to get the final address
Detailed Explanation of Common Addressing Mode
1. Register Addressing Mode
o What: Data is stored in a register
o How it works: Operand is directly in CPU register
o When to use:
§ Fastest execution (no memory access)
§ Frequently used variables
§ Temporary calculations
§ Loop counters
o Example:
MOV AX, BX ; BX content is moved to AX
ADD CX, DX ; Adds content of DX to CX
2. Immediate Addressing Mode
o What: Data is part of the instruction
o How it works: Constant value embedded in instruction
o When to use:
§ Initializing variables
§ Setting constants
§ Fixed values in calculations
§ Known values at compile time
o Example:
MOV AX, 1234h ; 1234h is the immediate value
ADD BX, 25 ; 25 is the immediate value
3. Direct (Memory) Addressing Mode
o What: Memory address directly specified in instruction
o How it works: Address provided explicitly
o When to use:
Accessing global variables
§
Static memory locations
§
Fixed memory addresses
§
I/O port addressing
§
o Example:
MOV AX, [1234h] ; Load from memory address 1234h
MOV [5000h], BX ; Store to memory address 5000h
4. Register Indirect Addressing Mode
o What: Memory address contained in a register
o How it works: Register holds memory address
o When to use:
§ Pointer operations
§ Array traversal
§ Dynamic memory access
§ Parameter passing
o Example:
MOV AX, [BX] ; BX contains memory address
MOV [SI], CX ; SI points to destination
