Instruction Set
Architecture (ISA)
Computer Architecture
Prof. Nataly Medina
Instruction Set Architecture
• Defines how the CPU is controlled by the software.
• The ISA defines:
• The supported data types
• The registers
• How the hardware manages main memory (RAM)
• Which instructions a microprocessor can execute
• The input/output model
Microarchitecture
• Is the digital logic that allows an instruction
set to be executed.
• Registers, memory, arithmetic logic units,
multiplexers, etc…
• Intel´s x86 family is the architecture
• NetBurst, Nehalem, etc.. microachitecture
FETCH – DECODE – EXECUTE
CPU
2. Decode ALU
Control
Unit
Registers
1. Fetch MEMORY
CPU
Address RAM
Control Unit
ALU ALU Control
EAX
EBX 𝑊𝐸
ECX
𝑂𝐸
EDX
𝐶𝐸
Fetch – Decode – Execute Cycle
A0 A0 A5
(1) (2)
PC A4
MAR
Control 6CF5 A3
Unit
A2
IR
A1
LDA A3 A0
ALU EAX MDR
CPU RAM
Fetch – Decode – Execute Cycle
A0 A1 A0 A5
(4)
PC A4
MAR
Control 6CF5 A3
Unit
A2
IR
A1
(3)
LDA A3 LDA A3 A0
ALU EAX MDR
CPU RAM
Fetch – Decode – Execute Cycle
A0 A1 A0 A5
(4)
PC A4
MAR
Control 6CF5 A3
LDA A3 Unit
A2
IR
A1
LDA A3 LDA A3 A0
ALU EAX MDR
CPU RAM
Fetch – Decode – Execute Cycle
(7)
A0 A1 A3 A5
PC (8) A4
MAR
Control
Unit 6CF5 A3
LDA A3
A2
IR
A1
(7)
6CF5 6CF5 LDA A3 A0
ALU EAX MDR
CPU RAM
Instruction Set
Instructions
• An instruction details the CPU of "What to Execute?", "Where to
Execute?" and "How to Execute?“
• Every CPU has an Instruction Set and format for the instructions.
• An instruction consists of minimum two components:
• Instruction code (opcode)
• Operand for the instruction
CISC vs RISC
• CISC: Complex Instruction Set Computer
• CISC computers have small programs.
• It has a huge number of compound instructions.
• CISC Processors: AMD, Intel x86, VAX
• RISC: Reduced Instruction Set Computer
• Utilizes a small, highly-optimized set of
instructions
• RISC Processors: ARM, AVR, SPARC
Instruction classification
• Data movement. Read or write from/to memory (MOV, LOAD, STORE)
• Arithmetic and logical (ADD, SUB, MUL, DIV, AND, OR, NOT)
• Transfer or control Jumps (JMP, JZ)
• Input/Output (IN, OUT)
• Miscellaneous (HALT, NOP, INT)
Instruction/Data formats
2. Data-Instruction Format
An instruction is normally made up of a combination of
an operation code and operands/address.
Optional: addressing mode.
Opcode Address or operand
Types of address instructions
Zero – address instruction 2 – address instruction
CMA MOV AX, BX
NOP ADD EAX, EBX
Opcode Opcode
1 – address instruction
3 – address instruction
ADD 06H
ADD R1, R2, R3
LDA 20H
SUB R1, R2, R3
Opcode
Opcode
1 – address instruction example
𝐴−𝐵
𝑌=
𝐶+𝐷×𝐸
LDA operand LOAD TO EAX EAX Operand
STOR operand STORE VALUE FROM EAX TO ANY PLACE Operand EAX
ADD operand ADD EAX WITH OPERAND, STORE RESULT IN EAX EAX EAX + Operand
SUB operand SUB EAX WITH OPERAND, STORE RESULT IN EAX EAX EAX - Operand
MUL operand MULTIPLY EAX BY OPERAND, STORE RESULT IN EAX EAX EAX * Operand
DIV operand DIV EAX BY OPERAND, STORE RESULT IN EAX EAX EAX / Operand
2 – address instruction example
𝐴−𝐵
𝑌=
𝐶+𝐷×𝐸
MOV dest, source dest source
ADD dest, source dest dest + source
SUB dest, source dest dest - source
MUL dest, source dest dest * source
DIV dest, source dest dest / source
3 – address instruction example
𝐴−𝐵
𝑌=
𝐶+𝐷×𝐸
ADD dest, A, B dest A + B
SUB dest, A, B dest A - B
MUL dest, A, B dest A * B
DIV dest, A, B dest A / B
Byte Ordering
x86 Registers & Addressing Modes
x86 Registers
Addressing Modes
MOV AL, 35H
ADD AL,[1234H]
MOV BX,CX
Addressing Modes
MOV EAX, [ESI + 4] PUSH EAX
PUSH [var]
POP EAX
POP [EBX]
Instructions & Addressing modes
<reg32> Any 32-bit register (EAX, EBX, ECX, EDX, ESI, EDI, ESP, or EBP)
<reg16> Any 16-bit register (AX, BX, CX, or DX)
<reg8> Any 8-bit register (AH, BH, CH, DH, AL, BL, CL, or DL)
<reg> Any register
<mem> A memory address (e.g., [eax], [var + 4], or dword ptr [eax+ebx])
<con32> Any 32-bit constant
<con16> Any 16-bit constant
<con8> Any 8-bit constant
<con> Any 8-, 16-, or 32-bit constant
Instructions & Addressing modes
mov — Move (Opcodes: 88, 89, 8A, 8B, 8C, 8E, ...)
Syntax
mov <reg>,<reg>
mov <reg>,<mem>
mov <mem>,<reg>
mov <reg>,<const>
mov <mem>,<const>
FFFFF
Logical Address
Memory
Segmentation Physical Address
Segment
Offset Segment Register
INTEL x86
Segment Address
CPU
0
Memory
Example: 2915:10A2
Segment Offset Purpose
CS IP Code/Program
DS BX, DI Data
SS SP Stack
Memory ES BX General
Segmentation Memory addresses are 20 bits wide.
To generate a physical address, the 16-bit segment is effectively
INTEL x86 multiplied by 16 (shifted left by 4 bits) before adding it to the 16-bit
offset.
The resulting 20-bit address is formed by concatenating the shifted
segment value with the offset, resulting in the physical address used to
access memory
CS = 1240H DS = 3223H SS = 1123H
IP = 4523H DI = 1000H SP = 2211H
Pipelining
A pipelined processor overlaps the stages (fetch, decode, execute, memory access, write-back)
of multiple instructions, keeping different parts of the processor busy simultaneously.
Example:
Execute 4 instructions using pipelining (𝐼1 , 𝐼2 , 𝐼3 , 𝐼4 )
Stage 1 2 3 4 5 6 7 8 9 10 11 12
Instruction
Fetch
Instruction
Decode
Instruction
Execution
