CMOS-Design-Flow

CMOS Design Flow : Figure below shows the CMOS IC design flow, it consists of defining
circuit inputs and outputs also called as specifications of the circuit. Once the detailed list of
inputs and outputs is developed from this the design calculations are performed and the
circuit schematic for the intended integrated circuit is designed. This developed schematic is
then drawn in CAD (Computer Aided Design) tools e.g. Tanner. Once the schematic entry is
finished then the circuit simulations are carried out and the obtained simulation results are
checked with the intended specifications this step is called as pre-layout simulation. After
checking post layout simulation results, the next step is the fabrication of the prototype board.
Once the fabricated board comes the testing of the protype is carried out and the initial
specifications are checked, if these results are not matched with the intended specifications
then there are two possibilities of error that may be either because of fabrication or initial
specification problem. If the prototype board passed all the tests then it is given for mass
production. This flow is used for custom IC design. A custom designed IC is also called as
ASIC (Application Specific Integrated Circuit). Other noncustom methods of designing chips
includes FPGA (Field Programmable Gate Arrays) and standard cell libraries. The FPGA and
standard cell approach is used when low volume and quick design turnaround are important.
Most of the chips that are mass produced such as microprocessors and memories are
manufactured using the custom design approach shown in Figure.
CMOS lambda Design Rules
CMOS 'λ' Design Rules :
The MOSIS stands for MOS Implementation Service is the IC fabrication service available to
universities for layout, simulation, and test the completed designs. The MOSIS rules are
scalable λ rules.
The MOSIS design rules are as follows :
(1) Rules for N-well as shown in Figure below.
1. Minimum width = 10λ
2. Wells at same potential with spacing = 6λ
3. Wells at same potential = 0λ
4. Wells of different type, spacing = 8λ

(2) Rules for Active area shown in Figure below.

1. Minimum width = 3λ
2. Minimum spacing = 3λ
3. Source/Drain active to well
edge = 5λ
4. Substrate/well contact active
to well edge = 3λ

3) Rules for poly 1 as shown in Figure below.

1. Minimum width = 2λ
2. Minimum spacing = 2λ
3. Minimum gate extension of active = 2λ
4. Minimum field poly to active = 1λ

(4) Rules for contact to poly 1 as shown in Figure below.

1. Exact contact size = 2 λ  2 λ
2. Minimum poly 1 overlap = 1 λ
3. Minimum contact spacing = 2 λ

(5) Rules for contact to active as shown in Figure below. 1. Exact contact size = 2λ  2λ 2.
Minimum active overlap = 1λ 3. Minimum contact spacing = 2λ 4. Minimum spacing to gate
of transistor = 2λ

(6) Rules for metal 1 as shown in Figure below.

1. Minimum width = 3λ
2. Minimum spacing = 3λ
3. Minimum overlap of poly contact = 1λ
4. Minimum overlap of active contact = 1λ

(7) Rules for via 1 as shown in Figure below.

1. Minimum size = 2λ  λ
2. Minimum spacing = 3λ
3. Minimum overlap by metal 1 = 1λ

(8) Rules for metal 2 as shown in Figure below.

1. Minimum size = 3λ
2. Minimum spacing = 4λ
(9) Rules for metal 3 as shown in Figure below.
1. Minimum width = 6λ
2. Minimum spacing = 4λ

CMOS-Layout-Design
Design Rule Check :
In order to ensure that none of the design rules are violated CAD tools named Design Rule
Checking (DRC) is used. If DRC is not verified then it leads to the non functional design.
The layout rules are grouped in three categories that are transistor rules, contact and via rules
and well and substrate contact rules.
Transistor rules :
The transistor can be created by overlapping the the active and polysilicon layers. The
minimum length of transistor equals 0.24 m which is minimum width of polysilicon,
whereas the width of the transistor is atleast 0.3 m which is the minimum width of active
layer.
Figure below shows the layout of PMOS transistor.

Fig1-Design-Rule-Check
Contact and Via rules :
A contact forms an interconnection between metal and active or polysilicon layer whereas via
forms an interconnection between two metal lines. A contact or via is formed by overlapping
the two interconnecting layers and provides a contact hole filled with metal between the two.
Figure below shows the contacts and via used in layout.

Fig1-Design-Rule-Check
Well and substrate contact rules :
For digital circuit design it is important for the well and substrate regions to be connected to
the supply voltages. If this is not done then a resistive path is created between the substrate
contact of the transistors and the supply rails which leads to parasitic effects such as latch up.

CMOS-Layout-Design
Inverter Layout :
The schematic diagram of the inverter is as shown in Figure.

Fig1-Inverter-Layout
The stick diagram of the schematic shown in Figure.
Fig2-Inverter-Layout
Here, the most important point to note is that as we change the placing of the components in
the schematic the stick diagram and hence, the layout of the circuit will change accordingly.
For example, if we place the components vertically the stick diagram will be vertical and if
we place the components horizontally the stick diagram will be horizontal. Figure below
shows the physical layout of inverter which is drawn in tanner tool.

Fig2-Inverter-Layout
Lambda-based-design-rules
Lambda based design rules :
The Mead-conway approach is to characterize the process with a single scalable parameter
called lambda, that is process-dependent and is defined as the maximum distance by which a
geometrical feature on any one layer can stray from another feature, due to overetching,
misalignment, distortion, over or under exposure etc. with a suitable safety factor included.
The purpose of defining lambda properly is to make the design itself independent of both
process and fabrication and to allow the design to be rescaled at a future date when the
fabrication tolerances are shrunk.
Scaling Theory :
The Scaling theory deals with the shrinking transistor and directs the behaviour of a device
when its dimensions are reduced.
The most commonly used scaling models are the constant field scaling and constant voltage
scaling. And another model for scaling the combination of constant field and constant voltage
scaling. The scaling parameter s is the prefactor by which dimensions are reduced. It is s < 1.
(1) The scaling factors used are, 1/s and 1/ .
(2) 1/ is used for supply voltage VDD and gate oxide thickness .
(3) 1/s is used for linear dimensions of chip surface.
(4) For the constant field model and the constant voltage model,  = s and  = 1 are used.
Layout-Design-Rules
Layout Design Rules :
The layout design rules provide a set of guidelines for constructing the various masks needed
in the fabrication of integrated circuits. Design rules are consisting of the minimum width and
minimum spacing requirements between objects on the different layers.
The most important parameter used in design rules is the minimum line width. This
parameter indicates the mask dimensions of the semiconductor material layers. Layout design
rules are used to translate a circuit concept into an actual geometry in silicon.
The design rules is the media between circuit engineer and the IC fabrication engineer. The
Circuit designers requires smaller designs with high performance and high circuit density
whereas the IC fabrication engineer requires high yield process.
Minimum line width (MLW) is the minimum MASK dimension that can be safely transferred
to the semiconductor material. For the minimum dimension design rules differ from company
to company and from process to process.
To address this issue scalable design rule approach is used. In this approach rules are defined
as a function of single parameter called ''. For an IC process '' is set to a value and the
design dimensions are converted in the form of numbers. Typically a minimum line width of
a process is set to 2 e.g. for a 0.25 m process technology '' equals 0.125 m.
Layered Representation of Layout :
The layer representation of layout converts the masks used in CMOS into a simple layout
levels that are easier to visualise by the designers. The CMOS design layouts are based on
following components :
(1) Substrates or Wells : These wells are p type for NMOS devices and n type for PMOS
devices.
(2) Diffusion regions : At these regions the transistors are formed and also called as active
layer. These are defined by n+ for NMOS and p+ for PMOS transistors.
(3) Polysilicon layers : These are used to form the gate electrodes of the transistors.
(4) Metal interconnects layers : These are used to form the power supply and ground rails as
well as input and output rails.
(5) Contact and Via layers : These are used to form the inter layer connections.

CMOS-Layout-Design
Layout of Logic gates:
Three Input NAND Gate :
Figure below shows, the schematic, stick diagram and layout of three input NAND gate.

Two Input NAND Gate :

Figure below shows the schematic, stick diagram and layout of two input NAND gate
implemented using complementary CMOS logic.
Two Input NOR Gate :
Figure below shows the schematic, stick diagram and layout of two input NOR gate
implemented using complementary CMOS logic.
Transmission Gate :
Figure below shows the schematic, stick diagram and layout of the transmission gate.
Micron-Design-Rules
Micron () Design Rules : Industry uses the micron design rules and code designs in terms of
these micron dimensions. The micron design rules are as follows :
(1) Rules for N-well as shown in Figure below.
1. Width = 3
2. Space = 9

2) Rules for active area as shown in Figure below.

1. Minimum size = 3
2. Minimum spacing = 3
2. N+ active to N-well = 7
(3) Rules for poly 1 as shown in Figure below.
1. Width = 2
2. Spacing = 3
3. Gate overlap of active = 2
4. Field poly 1 to active = 1

(4) Rules for contact to poly 1 as shown in Figure below.

1. Exact contact size = 2  2
2. Minimum poly overlap = 1
3. Minimum contact spacing = 2

(5) Rules for contact to active as shown in Figure below.

1. Exact contact size = 2  2
2. Minimum active overlap = 1
3. Minimum contact spacing = 2
4. Minimum spacing to gate = 2

(6) Rules for metal 1 as shown in Figure below.

1. Width = 3
2. Spacing = 3
3. Overlap of contact = 1
4. Overlap of via = 2
 (7) Rules for metal 2 as shown in Figure below.
1. Width = 3
2. Space = 3
3. Metal 2 overlap of via = 2

Stick-Diagrams
Stick Diagrams :
A stick diagram is a kind of diagram which is used to plan the layout of a transistor cell. The
stick diagrams uses "sticks" or lines to represent the devices and conductors.
Figure below shows the schematic of an inverter. In order to draw the layout of this circuit it
is necessary to define the direction and metalization of the power supply, ground, input and
output. The rules for drawing stick diagrams are :

Fig_Interconnect Routing Techniques

1) Power and ground lines run horizontally in metal 1.
2) The input and output are accessible from the top or bottom of the cell and will be in Metal
2 running vertically.
3) To draw the stick diagrams the conventions used in this book are shown in
Figure. These conventions are: For Metal-1 use thick solid line, for Metal-2 use thin solid
line, for poly use thick dashed line, for active ( n+ or p+ ) use thin dashed line, for contact use
"X" and for via use "O".

Fig-Stick-Diagrams