1.
Block Diagram of 8086
Figure: Functional block diagram of the 8086 microprocessor. The 8086 is divided into two main units: the Bus
Interface Unit (BIU) and the Execution Unit (EU) 1 2 . The BIU handles memory and I/O interfacing: it
generates 20-bit physical addresses (using the segment registers and the instruction pointer), fetches
instructions into a 6‑byte prefetch queue, and manages the address/data bus 3 4 . The BIU contains the
four segment registers (CS, DS, SS, ES), the instruction pointer (IP), and the address generation circuitry. The
EU executes instructions: it fetches opcodes from the prefetch queue, decodes them, and performs
arithmetic/logic operations using the ALU and 14 internal registers (AX, BX, CX, DX, SI, DI, BP, SP, IP, flags,
and four segment registers) 5 2 . Pipelining occurs because while the EU executes one instruction, the
BIU fetches the next.
2. Addressing Modes of 8086
The 8086 supports multiple addressing modes 6 7 :
• Register: Operand in a register (e.g. MOV AX, BX ).
• Immediate: Operand is a constant (e.g. MOV AX, 1234H ).
• Direct (Displacement): 16-bit memory address given directly (e.g. MOV AX, [5000H] ) 8 .
• Register Indirect: Memory address in a register (BX, SI, DI, or BP), e.g. MOV AX, [BX] 9 .
• Based: Address = Base register (BX or BP) + displacement, e.g. MOV AL, [BP+0100H] 10 .
• Indexed: Address = Index register (SI or DI) + displacement, e.g. MOV AX, [SI+2000H] 11 .
• Based-Indexed: Address = Base + Index, with optional displacement, e.g. MOV AL,
[BX+SI+2000H] 12 .
• Relative (PC-relative): Used by jumps/calls; offset relative to IP.
• String and I/O: Special modes for string operations (MOVSB/MOVSW) and port I/O (IN/OUT) 13 14 .
These modes let the 8086 flexibly access operands in registers, immediate constants, or various memory
locations using different register combinations 6 7 .
3. 8086 Maximum Mode Interfacing Diagram
Figure: 8086 in maximum mode with supporting chips (8284 clock, 8288 bus controller, 8282 latches, 8286
transceivers). In maximum mode (MN/MX’=0), the 8086 can interface with coprocessors or bus controllers
15 . An external 8284 generates the clock and provides ALE, reset, and READY sync, while an 8288 bus
controller decodes the 8086’s status signals into control lines (MEMR, MEMW, IOR, IOW, etc.) 16 . Three 8-
bit latches (8282) capture the 20-bit address bus (using ALE) and 2 bytes of opcode, and 8286 transceivers
drive the 16-bit data bus. The diagram shows 8282 latches (AD bus demultiplex), 8288 controller (taking S2–
S7 and producing control signals), and 8286 buffers. In this mode the 8086 outputs the signals BD̅#, DT/R̅,
DEN̅, ALE, and status (S3–S6) to support external bus control 17 .
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4. Memory Organization of 8086
The 8086 has a 20-bit address bus, so it can address 1 MB of physical memory (0–FFFFFH) 18 . It uses
segmented memory: memory is divided into segments up to 64 KB each, and four segment registers (CS,
DS, SS, ES) select the active segments 18 19 . Physical memory is also organized in two 512 KB banks (even
and odd), controlled by BHE’ and A0 for interfacing 8-bit chips 20 . A 20-bit physical address is calculated by
taking a 16-bit segment base (from a segment register) shifted left 4 bits plus a 16-bit offset:
PhysicalAddress = (Segment * 16) + Offset
For example, if CS=3000H and IP=0200H, the address = 30000H + 0200H = 30200H 21 22 . This
segmentation allows overlapping segments and flexible data/code layout, but effectively the total
addressable memory remains 1 MB.
5. Multiplexing in 8086
To reduce pin count, the 8086 multiplexes address and data lines: pins AD0–AD15 serve as the lower 16
address lines in T1, then become the 16-bit data bus in T2/T3 of a cycle 23 . Likewise, A16–A19 are
multiplexed with status signals S3–S6, and BHE’ with S7 24 25 . For instance, A16/S3 means that bit 16 of
the address is output during T1 and the status line S3 is output during T2–T3. An ALE (Address Latch Enable)
signal from the 8284 latch (edges strobe) the address from AD0–AD15 into external latches so the bus can
be used for data. This multiplexing means that in T1 the full 20-bit address is presented (via AD0–15 and
A16–19), and in later states the same pins carry data or status. The BHE’ (Bus High Enable) line is low when a
transfer uses the high byte (D15–D8) 25 . Overall, multiplexing lets 8086 use fewer pins by time-sharing the
address and data signals 23 24 .
6. Procedures in Assembly Language
A procedure (subroutine) is a named block of code that can be called from multiple places. In 8086
assembly, a procedure is identified by a label and typically begins with a declaration (like MyProc PROC in
MASM) and ends with RET . Using the CALL instruction pushes the return address (IP,CS) onto the stack
and jumps to the procedure’s code 26 . When the procedure executes RET , it pops the return address
from the stack back into IP, returning control to the caller 26 . Parameters are often passed on the stack
before the CALL, and the procedure uses PUSH / POP or other registers to save/restore registers. This
modular design allows code reuse. For example:
MyProc PROC
; procedure code here
RET
MyProc ENDP
MOV AX, … ; caller code
2
CALL MyProc
; return here
This CALL/RET mechanism enables structured programs. Modern 8086 assemblers (MASM/TASM) support
PROC/ENDP directives, but fundamentally CALL pushes IP/CS and RET restores them 26 .
7. Intel 8284 Clock Generator Features
The Intel 8284A is used with the 8086/8088 to provide clock and reset signals. Its key features are 27 16 : -
Clock generation: It can use a crystal or external oscillator to generate the CPU clock (CLK) and a peripheral
clock (PCLK). The 8284 divides the input clock by 2 for the CPU 27 .
- Address Latch Enable (ALE): It provides a buffered ALE signal to demultiplex the 8086’s AD bus lines.
- READY synchronization: It has inputs (RDY1, RDY2) to sample slow memory or I/O devices; READY output
then gates the 8086’s bus cycle (inserting wait states if needed) 16 .
- Reset generator: It includes a power-on reset circuit (with RC network) and an external RES input,
generating a proper RESET pulse for the 8086 16 .
Outputs are TTL-compatible. In summary, the 8284 provides the clock, ALE strobe, synchronized READY, and
reset control needed for stable 8086 operation 27 16 .
8. Differences: 8086 vs 8088
The 8086 and 8088 are architecturally the same (same 16-bit registers, instructions, and 20-bit addressing)
28 . The main difference is the data bus width: 8086 has a 16-bit external data bus, while 8088 has only an
8-bit bus 28 . This makes the 8088 cheaper (it can use 8-bit support chips) but slower: the 8088 needs two
bus cycles to fetch a 16-bit word whereas the 8086 does it in one 28 . Aside from the bus, pinouts differ
(8088 uses two phases for data on AD0–AD7 only). Performance-wise, an 8086 runs nearly twice as fast on
the same clock, because its 16-bit bus and pipeline fetch deliver data more quickly. Functionally, their
instruction sets and modes are identical 28 .
9. Wait States in 8086
Wait states are inserted when memory or I/O is slower than the CPU’s bus cycle. The 8086 samples the
READY input in T2 of a bus cycle: if READY=0, the CPU inserts extra idle cycles (Tw) after T2 (i.e. extends T3)
and repeats until READY=1 29 . This lengthens the memory or I/O cycle to accommodate slower devices. For
example, a slow RAM might hold READY low so the 8086 waits an extra clock. The 8086 also has a dedicated
WAIT instruction that causes the CPU to loop on its TEST (WAIT) pin until the external device raises it. In
practice, to insert wait states you ensure the memory’s READY line is asserted appropriately (or use the
8284’s RDY sync inputs). Using an instruction WAIT or holding READY low achieves the same effect: the
8086 delays the bus cycle as needed 29 .
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10. Configuring Minimum vs Maximum Mode
The mode of the 8086 is selected by the MN/MX’ pin (sometimes called Mode Select). Setting MN/MX’ = 1
puts the processor in minimum mode; MN/MX’ = 0 selects maximum mode 30 . In minimum mode (pin
high), the 8086 assumes it is the only bus master and generates all control signals internally. In maximum
mode (pin low), external bus controllers are used (e.g. the 8288) and the 8086 provides only status lines and
local bus signals 30 . Thus, to configure: tie MN/MX’ to Vcc for minimum mode, or to ground for maximum
mode 30 . Other bus pins (like BD’) will then reflect the chosen mode (BD’=1 for min mode).
11. Software Interrupts (8086) and Execution
Sequence
A software interrupt is invoked by the INT n instruction (where n = 00H–FFH). When executed, the 8086
does the following 31 32 : it pushes the FLAGS register onto the stack, then pushes the current CS and IP. It
then clears the Trap and Interrupt-Enable flags, and loads new IP and CS from the interrupt vector table at
address 4×n (IP from memory[4n], CS from memory[4n+2]) 32 . Control transfers to this interrupt service
routine (ISR). For example, INT 21H pushes FLAGS, CS, IP, then jumps to the routine whose address is
stored at 21H×4. The ISR executes, and eventually an IRET will pop IP, CS, and FLAGS off the stack to
resume the original program. In summary: push FLAGS, push CS, push IP, load CS:IP from vector 31 32 .
12. Type 0 Interrupt (Divide-by-Zero)
A type 0 interrupt is the “divide error” exception. It is triggered when a DIV or IDIV instruction is executed
with a divisor of zero, or when the signed quotient does not fit in the destination register. In other words,
DIV or IDIV causes a type 0 fault if the divisor=0 or the result overflows. No other instructions cause
INT 0. For example, DIV CX when CX=0 will generate a divide-by-zero interrupt. The 8086 automatically
handles this by invoking interrupt vector 0 (like a software INT 0 ), so the CPU pushes flags/CS/IP and
jumps to the handler address at 0×4 33 .
13. Memory Segmentation and Physical Address
Calculation
Segmentation: The 8086 organizes memory into segments of 64 KB each. Four segment registers (CS, DS,
SS, ES) hold the segment bases for code, data, stack, and extra. These segment registers contain the high 16
bits of the base (shifted left 4 bits) of a segment in memory 18 19 . The CPU uses these to form linear
addresses.
Physical Organization: Physically, memory is 1 MB total, arranged as two interleaved 512 KB banks (even/
odd) with A20 (address line 20) selecting above 1 MB if any 20 .
Address Calculation: To compute a 20-bit physical address from a logical address (segment:offset), use:
4
PhysicalAddress = (SegmentRegister << 4) + Offset
Here, the 16-bit segment register is effectively multiplied by 16 (shifted left by 4) and then added to the 16-
bit offset 21 22 . For example, CS:IP = 1234H:0020H yields physical address 12340H+0020H = 12360H. This
formula means segments can overlap and be positioned anywhere in memory, but the maximum address
remains 20 bits.
14. Example: Multiply Two 16-bit Numbers
Use the MUL instruction (unsigned multiply). For instance, if the first number is at [3000H] and the second
at [3002H], one program is 34 :
MOV AX, [3000H] ; load first 16-bit number into AX
MOV BX, [3002H] ; load second number into BX
MUL BX ; unsigned multiply: AX*BX → 32-bit result in DX:AX
MOV [3004H], AX ; store low word of result
MOV AX, DX
MOV [3006H], AX ; store high word of result
HLT
This sequence loads the operands into AX and BX, executes MUL BX (which multiplies AX by BX giving a 32-
bit product in DX:AX), and then writes the low word (AX) and high word (DX) to memory 34 .
15. Example: Count Negative Numbers in 5-Byte
Array
A simple loop can examine each byte’s sign bit. For example (assuming data starts at label arr and count
at cnt ):
MOV CX, 5 ; number of elements
MOV SI, OFFSET arr ; index pointer
XOR DL, DL ; clear count in DL
CheckLoop:
MOV AL, [SI] ; load byte
TEST AL, 80h ; check sign bit (80h = bit7)
JZ Skip ; if sign=0 (non-negative), skip
INC DL ; else increment negative count
Skip:
INC SI
5
LOOP CheckLoop
MOV [cnt], DL ; store result
This code iterates 5 times, uses TEST AL,80h to test the sign (negative numbers have bit7=1), and
increments DL when negative. The final count is stored in memory. (The exact syntax may vary by
assembler.)
16. Example: Transfer a String of Data Bytes
We can use string instructions. For example, assume a null-terminated source at src and a destination at
dst :
MOV SI, OFFSET src
MOV DI, OFFSET dst
CLD ; ensure forward direction
NextByte:
LODSB ; load byte at DS:SI into AL (SI++)
STOSB ; store AL at ES:DI (DI++)
CMP AL, 0
JNZ NextByte ; loop until zero byte
This loop copies each byte from src to dst until a 0 terminator is reached (copying the terminator as
well). On the 8086, by default DS:SI and ES:DI should point to the source and destination segments
respectively (often DS=ES). (Alternatively, one can use REP MOVSB with CX set to length.)
17. Intel 80186 Architecture
Figure: 80186 block diagram (typical high-integration microcontroller architecture). The 80186 is a 16-bit
microprocessor with built-in peripherals for embedded systems 35 36 . Architecturally it has the same BIU/
EU core as the 8086, but integrates many common support functions on-chip: an 8284-style clock
generator, a programmable interrupt controller, DMA channels, three 16-bit timers, bus address
decoding (chip-select), and wait-state generator 36 . These on-chip units (shown in the block diagram
above) reduce external components. The 80186 also adds some new instructions (relative to the 8086) for
string handling and loop control. In the block diagram, the lower-left is the BIU (address bus, 6-byte queue),
the upper-middle is the EU (ALU, registers), and the right side shows the internal peripherals (timers, DMA,
interrupt controller, bus logic)【82†】. Overall, the 80186 offers twice the performance of an 8086 at the
same clock and full 8086 compatibility plus extra I/O hardware on chip 36 .
18. Multitasking vs. Multiprogramming
Multiprogramming and multitasking are OS-level scheduling concepts. Multiprogramming means
keeping multiple jobs in memory so the CPU always has a process to execute: when one job waits (e.g. for I/
6
O), another runs. This maximizes CPU utilization 37 . For instance, if Program A is waiting for disk, the OS
runs Program B, minimizing idle time.
Multitasking (time-sharing) is an extension where the CPU rapidly switches between jobs so that each
appears to run “simultaneously.” It uses time slices: the OS gives each task a small time quantum, then
preempts and switches to the next, typically with round-robin scheduling 38 . This provides interactive
responsiveness. GeeksforGeeks notes that multitasking is a logical extension of multiprogramming: it
“executes more than one task simultaneously” by sharing CPU time 38 . In summary, multiprogramming
simply loads multiple jobs and switches on I/O, whereas multitasking actively timeshares the CPU among
tasks (often with interrupts and context switches) 37 38 . Both aim to reduce idle CPU time, but
multitasking allocates defined time slots (time-sharing).
19. 80286 Protected (Virtual) Address Mode
In 80286 protected mode, each segment register (CS, DS, etc.) contains a selector that indexes into a
descriptor table (GDT/LDT) rather than supplying the base directly. Each segment descriptor holds a 24-bit
base address and 16-bit limit 39 . When a logical address (selector:offset) is used, the CPU reads the
descriptor base and adds the 16-bit offset to compute the 24-bit physical address 39 40 . In other words:
PhysicalAddress = (Descriptor_Base) + Offset
This allows addressing up to 2^24 bytes (16 MB) of physical memory 39 . For example, if a code segment’s
descriptor base is 50000H and IP=1234H, the CPU jumps to physical address 51234H. Protected mode adds
bounds and privilege checks when combining base+offset. This protected (or “virtual”) mode contrasts with
real mode’s simple segment<<4 scheme.
20. GDT/LDT Descriptor Counts and Access
On the 80286, each descriptor table (global or local) is addressed by a 13-bit index in a segment selector
(plus a Table Indicator bit). This allows up to 2^13 = 8192 entries per table 41 . The Global Descriptor Table
(GDT) holds global descriptors; the Local Descriptor Table (LDT) holds local descriptors. A segment
selector’s TI (Table Indicator) bit selects which table: TI=0 means GDT, TI=1 means LDT 41 . Thus, you can
define up to 8192 global descriptors and 8192 in each LDT. To access them, you load a selector into a
segment register (using MOV or a CALL far), and the CPU fetches the appropriate descriptor from the GDT
or LDT indexed by the selector 41 . In summary, selectors (with index+TI bit) point to GDT or LDT entries,
allowing up to 8192 entries in each table 41 .
21. Virtual-8086 Mode on 80286
The 80286 does not support true Virtual-8086 mode; this was introduced in the 80386. The 286 can run in
real mode (8086-compatible segmentation, 1 MB) or in protected mode (16 MB via descriptors). Real mode
on the 80286 is similar to the 8086’s, except it can access a slight “High Memory Area” above 1 MB (up to
~1.06 MB) due to not truncating addresses 42 . However, it has no virtualization layer. Therefore, on an
7
80286 memory is managed either in real mode (with one segment×16 + offset) or in protected mode (using
GDT/LDT descriptors). There is no hardware “virtual 8086” sub-mode in the 286; multiple real-mode
programs cannot run concurrently under protected mode until the 386 introduced v86 mode. In protected
mode, memory management uses descriptors as above.
22. 8086 Read/Write Cycle (Min Mode)
Figure: 8086 minimum-mode memory read cycle (T1–T4). ALE=Address Latch Enable, M/IO’=0 for memory,
RD’=active, DEN=Data Enable. In a memory-read cycle (min mode):
- T1: The 8086 places the 20-bit address on AD0–AD19 (ALE=1), and M/IO’=0 indicates a memory cycle 43 .
- T2: ALE goes low, the address is latched externally. The CPU asserts RD’ low (with DEN active) to read. The
addressed memory drives the data bus.
- T3: If the memory is ready, the CPU samples the data on AD0–AD15. If not, wait states are inserted (READY
held low) 29 .
- T4: RD’ is deasserted, and the cycle ends.
In a memory-write cycle, the pattern is similar but with WR’ asserted:
- T1: Address on bus (ALE=1), M/IO’=0.
- T2: Data to write is placed on AD0–AD15, and WR’ is asserted. Memory latches the data.
- T3/T4: Complete the write (memory takes any extra time).
Thus each bus cycle has at least T1–T4; the 8086 uses the control signals (RD’, WR’, DEN, etc.) to coordinate
the transfer 43 .
23. 80286 Pin Functions
Key 80286 pins include:
• Clock (CLK): Input clock; internally divided by 2 to drive the CPU 44 .
• Data bus D15–D0: 16-bit bidirectional data lines for memory/I-O. During bus cycles these lines carry
data (high=active); they float (tri-state) when the bus is released 45 .
• Address bus A23–A0: 24-bit address outputs. The upper 8 bits (A16–A23) are only valid during
memory cycles. The lines float during bus hold 46 .
• BHE# (Bus High Enable): Active-low output indicating the transfer uses the high byte (D15–D8). Low
means D8–D15 contain valid data 47 .
• Status signals S1–S0: Active-low outputs indicating the current bus cycle status (in conjunction with
M/IO# and CODE/INTA#) 48 .
• M/IO#: Output: High for memory cycle, Low for I/O cycle (or HALT) 49 .
• CODE/INTA#: Output: distinguishes code fetch (instruction) vs data read, and low during interrupt
acknowledge cycles 50 .
• LOCK#: Active-low output, asserted to lock the bus during atomic instructions (XCHG, INTA, etc.) 51 .
• READY#: Active-low input. When low, it indicates the addressed device is not ready, causing wait
states (extends T3) 52 .
• HOLD/HLDA: HOLD (input) requests bus control (for DMA); when HOLD=1 the CPU tri-states the bus
and raises HLDA (output) to acknowledge 53 .
8
• INTR (Interrupt Request): Maskable interrupt input (active high). If IF=1, a low-to-high on INTR
causes the CPU to perform two INT acknowledge cycles 54 .
• NMI (Non-Maskable Interrupt): Edge-triggered, non-maskable interrupt (active high). Triggers
vector 02H (no INTA cycle needed) 55 .
• Processor Extension (80287) interface: PEREQ# (input) and PEACK# (output) signal co-processor
requests, and BUSY# / ERROR# inputs indicate 80287 busy or error 56 57 .
• RESET: Active-high input; a rising edge resets the CPU (must be high for ≥16 CLK cycles) 58 .
• VCC, VSS: +5 V supply and ground.
• CAP: Connects a 0.047 µF capacitor for the internal bias generator (must be present).
Each of these pins is described in the Intel 80286 documentation 59 60 .
24. Descriptor Table Register Instructions
The special registers for descriptor tables are loaded by specific instructions:
- LGDT – Load Global Descriptor Table Register (GDTR) with a memory operand (the GDT’s base and limit).
- LLDT – Load Local Descriptor Table Register (LDTR) with a selector in the argument.
- LIDT – Load Interrupt Descriptor Table Register (IDTR) from memory (IDT base and limit).
Their complementary instructions SGDT, SLDT, SIDT store the contents of GDTR, LDTR, IDTR to memory.
These instructions were introduced with the 80286/386 for protected-mode memory management.
25. Main Features of 80186 and 80286
• 80186: A 16-bit “embedded” microprocessor that packs many support functions on-chip. It has the
same instruction set as the 8086 (plus the 80188’s extra instructions) and adds about 10 new
instructions. Unlike the 8086, the 80186 integrates an on-chip clock generator, interrupt
controller, DMA controller, three 16-bit timers, wait-state generator, and chip-select logic for
memory/IO decoding 35 36 . This high integration (15–20 components on one chip) reduces the
external hardware needed, making it suitable for embedded controllers. It typically offers about
twice the performance of an 8086 at the same clock due to faster bus interface and built-in
peripherals 36 .
• 80286: A 16-bit CPU introduced in 1982 with a 24-bit address bus (capable of 16 MB physical
memory) 61 . It features a pipelined ALU/EU architecture (non-multiplexed bus) that nearly doubles
8086 performance per clock 62 . The 80286 can operate in real mode (like an 8086) or protected
mode. Protected mode was the first on-chip MMU in x86: it provides hardware memory protection
and supports privilege levels and segmentation for multitasking OSes 63 . It retains all 8086/80186
instructions and adds many new ones (e.g. for protected mode setup: ARPL, LAR, LGDT, LIDT, LLDT,
LTR, etc.) 64 . Unlike the 8086, the 80286 can address extended memory (beyond 1 MB) and supports
multitasking OSes. However, once in protected mode it cannot return to real mode without a reset.
In summary, the 80286’s main features are a larger address space (24-bit bus), on-chip memory
management (protected mode), higher performance, and compatibility with the 8086 instruction set
61 63 .
9
26. Real Mode vs. Virtual-8086 Mode
Real mode is the original 8086-compatible mode present on all x86 CPUs. In real mode, segmentation
works as on the 8086: segment registers are shifted 4 bits to form 20-bit addresses, giving a 1 MB linear
address space. No privilege levels or protection exist; any instruction can access all memory. Real mode is
how the CPU starts up (BIOS boot).
Virtual-8086 mode (v8086 mode) is a feature of the 80386 and later, not the 80286. It is a sub-mode of
protected mode where the CPU can run a “virtual” 8086 environment. Each v8086 task runs in a protected-
mode segment, but the hardware provides a view of real-mode memory (1 MB space) for that task. This lets
an OS run multiple real-mode programs concurrently under protected mode. In v86 mode, segments are
managed by descriptors (like protected mode), but interrupts and memory access behave as if in real mode.
In short, real mode is the legacy 20-bit mode of the 8086, while virtual-8086 mode (only on 386+) simulates
real mode under the control of the protected-mode operating system. (The 80286 does not support v86
mode; it only has real or protected modes.)
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39 41 65 60 61 .
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34 8086 program to multiply two 16-bit numbers - GeeksforGeeks
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35 36 80186 Microprocessor Architecture - EEEGUIDE.COM
https://www.eeeguide.com/80186-microprocessor-architecture/
37 38 Difference between Multiprogramming and Multitasking - GeeksforGeeks
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39 40 41 42 x86 memory segmentation - Wikipedia
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