UNIT - I

Introduction to 80386

Reference book: Intel 80386 Programmer's Reference Manual 1986,Intel Corporation,

Order no.: 231630-011, December 1995
 Intel
 1971 - 4004
– First microprocessor
– All CPU components on a single chip
– 4 bit, Single Core

 Followed in 1972 by 8008

– 8 bit, Single Core
– Both designed for specific applications

 1974 - 8080
– Intel’s first general purpose microprocessor (8 bit)
 x86 Evolution
• 80286
– 16 bit
• 8086
– much more powerful
• 80386
– 16 bit
– 32 bit
– instruction cache, prefetch few
– Support for multitasking
instructions
– 8088 (8 bit external bus) used in first
IBM PC • 80486
– sophisticated powerful cache and
instruction pipelining
– built in maths co-processor
 x86 Evolution
• • Pentium III
Pentium
• Additional floating point instructions for 3D
– Superscalar graphics
– Multiple instructions executed in parallel
• Pentium 4
• Pentium Pro • Note Arabic rather than Roman numerals
– Increased superscalar organization • Further floating point and multimedia
– Aggressive register renaming enhancements
– branch prediction • Core
– data flow analysis • First x86 with dual core
– speculative execution
• Core 2
• Pentium II • 64 bit architecture
– MMX technology
• Core 2 Quad – 3GHz – 820 million transistors
– graphics, video & audio processing
• Four processors on chip
Refer Intel web pages for detailed information on processors
 Features of 80386DX
• Flexible 32-bit Microprocessor • Hardware Debugging Support
– 8, 16, 32-Bit Data Types
– 8 General Purpose 32-Bit Registers
– 32 bit ALU • 3 stage Pipeline
– 32 bit Data Bus(4 memory Bank)
– 32 bit Address Bus( 4 GB Memory) • Multitasking

• Very Large Address Space • Operating Speed-16,20,25,33 MHz

– 4 Gigabyte Physical
– 64 Terabyte Virtual • SX (16 bit Data Bus)
– 4 Gigabyte Maximum Segment Size DX(32 bit Data Bus)

• Integrated Memory Management Unit

– Segmentation and Paging
– 4 Levels of Protection
– Fully Compatible with 80286
 80386DX Architecture

Memory Management Unit

Bus Control Unit

Central Processing Unit

 80386DX Architecture
The Intel386DX consists of
– A central processing unit,
• Execution unit
• Instruction unit

– A memory management unit and

• Segmentation unit
• Paging unit

– A bus interface.
• offers address pipelining, dynamic data bus sizing, and direct Byte Enable signals for each
byte of the data bus
 Execution Unit
• The execution unit contains the
 Eight 32-bit general purpose registers which are used for both address calculation, data
operations and

 A 64-bit barrel shifter used to speed shift, rotate, multiply, and divide operations.

• The multiply and divide logic uses a 1-bit per cycle algorithm.

• The multiply algorithm stops the iteration when the most significant bits of the multiplier are all
zero.

• This allows typical 32-bit multiplies to be executed in under one microsecond.

 Execution Unit (Cont…)
 The linear address consists of two components:
• The segment base address and
• An effective address.

 The effective address is calculated by using four address elements:

• DISPLACEMENT: An 8-, 16- or 32-bit immediate value
• BASE: The contents of any general purpose register. It is generally used by compilers to point
to the start of the local variable area.
• INDEX: The contents of any general purpose register except for ESP. The index registers are
used to access the elements of an array, or a string of characters.
• SCALE: The index register's value can be multiplied by a scale factor, either 1, 2, 4 or 8. Scaled
index mode is especially useful for accessing arrays or structures.
EA = Base Register + (Index Register * Scaling) + Displacement.
 Instruction and Segmentation Unit
Instruction Unit:

The instruction unit decodes the instruction opcodes and stores them in the
decoded instruction queue for immediate use by the execution unit.

Segmentation Unit:

Segmentation allows the managing of the logical address space by

providing an extra addressing component, one that allows
 easy code
 data relocatability, and
 efficient sharing
 Paging Unit
– The paging mechanism operates beneath and is transparent to the segmentation
process, to allow management of the physical address space.

– Each segment is divided into one or more 4K byte pages.

 Programmers Model
• Intel386 DX base architecture registers:

 General data and address registers

 Segment selector registers

 Instruction pointer

 Flags register
Register Organization of 80386
Flags Register
 Processing Modes
• The Intel386 DX modes of operation: • Protected mode:
– Real Address Mode (Real Mode), and – Natural 32-bit environment, in which all
instructions and features are available.
– Protected Virtual Address Mode
– It provides access to the sophisticated
(Protected Mode).
memory management, paging and privilege
– Virtual 8086 mode (V86 Mode). capabilities of the processor

• Real-address mode (Real mode): • Virtual 8086 mode (V86 Mode):

– Power on default mode :mode of the – It is a dynamic mode within protected
processor immediately after RESET. mode.
– Upward Compatibility. – processor can repeatedly and rapidly
– Faster 8086: In this mode the Intel386 switch between V86 mode and protected
DX operates as a very fast 8086, mode.
– but with 32-bit extensions if desired. – CPU enters V86 mode from protected mode
to execute an 8086 program, then leaves
V86 mode and enters protected mode to
continue executing a native 80386 program
 80386 Addressing Modes
 Addressing modes indicate a way of locating data or operands.
 Describes the type of operands and the way they are accessed for executing an instruction.
 The method by which address of source data and destination address of result is given in the
instruction is called as “ Addressing Modes”.
 The 80386 Microprocessor Provide 11 addressing modes

• Register addressing Mode

• Scaled Index addressing Mode
• Immediate addressing Mode
• Based Index addressing Mode
• Direct addressing Mode
• Based Scaled Index addressing Mode
• Register Indirect addressing Mode
• Based Index addressing Mode with Displacement
• Based addressing Mode
• Based Scaled Index addressing Mode with
Displacement
• Index addressing Mode
 Register Addressing Modes
• The data is stored in a register and it is referred using a particular register.

• All register accept IP used in this addressing mode.

• The 8/16/32 bit data required to execute an instruction is present in 8/16/32 bit register is
given along with the instruction is called “Register addressing mode.”

 Example : ADD EAX,EBX

 Immediate addressing mode
• In this addressing mode, immediate data is part of instruction.

• The 8/16/32 bit data required to execute an instruction is given directly along with the
instruction is called “Immediate addressing mode”.

 Example: Mov AX,0020H

 Direct and Register Indirect addressing mode

• Direct addressing mode

The operand's offset is contained as part of the instruction as an 8-, 16- or 32-bit
displacement.
In Direct addressing mode the effective address of memory location where the operand
is present is written directly in the instruction.
 Example: MOV AX, [5000H]

• Register Indirect Mode:

A BASE register contains the address of the operand.

 Example: MOV EAX, [EBX]

 Based and Index addressing mode
• Based addressing mode
Based Mode: In this addressing mode, the offset address of the operand is given by the sum
of the contents of Base Register and Displacement.
 Example: MOV ECX, [EAX+24]

• Index addressing Mode:

An INDEX register's contents is added to a DISPLACEMENT to form the operands offset.

 Example: ADD EAX, TABLE[ESI]

 Scaled Index & Based Index addressing mode

• Scaled Index addressing mode

An INDEX register's contents is multiplied by a scaling factor which is added to a
DISPLACEMENT to form the operands offset.

 Example: IMUL EBX, TABLE[ESI*4],7

• Based Index addressing Mode:

The contents of a BASE register is added to the contents of an INDEX register to form the
effective address of an operand.

 Example: MOV EAX, [ESI] [EBX]

 Other addressing mode
• Based Scaled Index addressing mode: The contents of an INDEX register is multiplied by a
SCALING factor and the result is added to the contents of a BASE register to obtain the
operands offset.

 Example: MOV ECX, [EDX*8] [EAX]

• Based Index addressing Mode with Displacement: The contents of a BASE register is
added to the contents of an INDEX register to form the effective address of an operand.

 Example: ADD EDX, [ESI] [EBP+00FFFFF0H]

• Based Scaled Index addressing Mode with Displacement: The contents of an INDEX
register are multiplied by a SCALING factor, the result is added to the contents of a BASE
register and a DISPLACEMENT to form the operand's offset.
 Data Types
Fundamental Data Types:
– Byte
– Word
– Doubleword
Byte, word and doubleword in memory
80386 Data Types
 Instruction Sets
• Data Movement Instructions
• Binary Arithmetic Instructions
• Decimal Arithmetic Instructions
• Logical Instructions
• Control Transfer Instructions
• String and Character translation Instructions
• Instructions for Block-Structured Languages
• Flag Control Instructions
• Coprocessor Interface Instructions
• Segment Register Instructions
• Miscellaneous Instructions
 Data Movement Instructions
• Provides convenient methods for moving bytes, words or
doublewords of data between memory and the register.

• Various Classes
o General purpose data movement instructions
o Stack manipulation instructions
o Type-conversion instructions
 General Purpose data movement instructions

• MOV (Move): Transfers a byte, word or doubleword from the source operand
to the destination operand

• Operand options
– To a register from memory
– To memory from a register
– Between general registers
– Immediate data to a register
– Immediate data to a memory

• Memory to Memory and Segment register to segment register, not allowed

• MOVS: string manipulation instruction for memory to memory moves
 Example: MOV EAX, EBX ; Moves contents of EBX to EAX
• XCHG (Exchange): Swaps the contents of two operands.

• Operands may be two registers or a register with memory

 Example: XCHG EAX, EBX
(it exchanges the contents of register with an another register or the content of
register with content on memory location and vice-versa.)

• Does not require temporary location to save the contents of one

operand while the other is being loaded
 Stack manipulation Instructions
• PUSH

• PUSHA

• POP

• POPA
 Type Conversion Instructions

• Converts bytes to words, words to •CBW: (Convert byte to word)

doublewords and doublewords to 64- AL  AX
bit items •CWD: (Convert word to doubleword)
AX  DX:AX
• Specially useful for converting signed •CDQ: (Convert doubleword to quadword)
integers
• Two classes: EAX  EDX:EAX
 The forms CBW, CWD, CDQ and CWDE •CWDE: (Convert word to doubleword extended)
(Operates on EAX)
 MOVSX and MOVZX (One register AX  EAX
•MOVSX: (Move with sign extension) sign-extends
operand and other may be register or
memory) an 8-bit to 16-bits and 8- or 16- bit value to 32- bit
value
•MOVZX: (Move with zero extension) zero-
extended
 Binary Arithmetic Instructions
• Addition and subtraction
instructions
– ADD (Add integers)
– ADC (Add integers with carry)
– INC (Increment)
– SUB (Subtract integers)
– SBB (Subtract integers with borrow)
– DEC (Decrement)

• Comparison and Sign change

– CMP (Compare)
– NEG (Negate) subtract from zero
 Binary Arithmetic Instructions
• Multiplication Instructions: • Division Instructions:
– MUL (Unsigned Integer multiply) • DIV (Unsigned Integer division)

Source Accumulator Result Size of Source Dividen Result Result

(Multiplier (Multiplicand (Product) operand d (Quotien (Remainder)
) ) [Double-length] (Divisor) t)
8-bit AL AX 8-bit AX AL AH
16-bit AX DX:AX 16-bit DX:AX AX DX
32-bit EAX EDX:EAX 32-bit EDX:EAX EAX EDX

• IDIV (Signed Integer division)

Same register combinations
– IMUL (Signed Integer multiply)
Three variations: One-, two- and three- operand form
 Decimal Arithmetic Instructions
 Decimal arithmetic is performed in
combination with binary arithmetic  Packed BCD Adjustment instructions
instructions. • DAA (Decimal adjust after addition)
• DAS (Decimal adjust after subtraction)
– To adjust the results of a previous binary
arithmetic operation to produce a valid
packed or unpacked decimal result
 Unpacked BCD Adjustment instructions
• AAA (ASCII Adjust after Addition)
– To adjust the input to a subsequent binary
arithmetic operation so that the operation • AAS (ASCII Adjust after Subtraction)
will produce a valid packed or unpacked • AAM (ASCII Adjust after Multiplication)
decimal result • AAD (ASCII Adjust before division)
 Logical Instructions
 The Boolean operation instructions

 Bit test and modify instructions

 Bit scan instructions

 Rotate and shift instructions

 Byte set on condition

 Logical Instructions (Cont…)
 The Boolean operation instructions
Boolean operation instructions:
 Bit test and modify instructions • NOT:

 Bit scan instructions • AND:

• OR:
 Rotate and shift instructions
• XOR:
 Byte set on condition
 Logical Instructions (Cont…)
 The Boolean operation instructions

 Bit test and modify instructions

 Bit scan instructions

 Rotate and shift instructions

 Byte set on condition

 Logical Instructions (Cont…)
Bit test and modify instructions: Bit Scan Instructions:
– Operates on single bit within the
• Scan a word or doubleword for a one-bit
operand (Register or Memory)
and store the index of the first set bit into a
register
– Bit location is specified as an offset
from low-order end of the operand
Instruction Effect on Effect on Selected • ZF is set if entire operand is zero
CF Bit  BSF (Bit Scan Forward)
BT (Bit test) CF  BIT (none)  BSR (Bit Scan Reverse)
BTS (Bit test and Set) CF  BIT BIT  1
BTR (Bit test and Reset) CF  BIT BIT  0
BTC (Bit test and CF  BIT BIT  NOT (BIT)
Complement)
 Logical Instructions (Cont…)
 The Boolean operation instructions

 Bit test and modify instructions

 Bit scan instructions

 Rotate and shift instructions

 Byte set on condition

 Logical Instructions (Cont…)
• Shift and Rotate Instructions:
– Shift instructions
SAL (Shift Arithmetic Left) Byte set on Condition instructions:
•
• SHL (Shift Logical Left)
• Sets a byte to Zero or One depending on any
• SHR (Shift Logical Right)
of the 16 conditions defined by the status
• SAR (Shift Arithmetic Right) flags

– Double shift instructions SETcc (Set byte on condition cc)

• SHLD (Shift Left Double)
• SHRD (Shift Right Double) • Test Instructions:

– Rotate instructions TEST (Test) performs the logical “and”

• ROL, ROR, RCL, RCR
 Control Transfer Instructions

Control Transfer Instructions  Unconditional transfer

Instructions (Near and Far)
Unconditional Transfer
Instructions – JMP (Jump)- one way transfer of
execution
Conditional Transfer
Instructions – CALL (Call procedure)

– RET (Return from procedure)

– IRET (Return from interrupt)

 Control Transfer Instructions

 Conditional transfer
instructions
– Conditional jump instructions
 Control Transfer Instructions

 Loop Instructions: (before testing the  Software generated interrupts

condition/s it decrements ECX) – INT n (Software interrupt)
• LOOP (Loop while ECX not zero)
• LOOPE (Loop while equal) and
LOOPZ (Loop while zero) – INTO (Interrupt on Overflow)
• LOOPNE (Loop while not equal)
and LOOPNZ (Loop while not
zero) – BOUND (Detect value out of range.
BOUND ensures that a signed array index
 Executing a Loop or Repeat zero is within the limits specified by a block of
times memory consisting of an upper and a
• JCXZ (Jump if ECX zero) lower bound.)
 String and Character translation instructions

• Set of primitive string instructions  Repeat prefixes

(Operand B/W/D) – REP: repeat while ECX not zero
– MOVS: Move string
– REPE / REPX: repeat while equal or zero
– CMPS: Compare string
– SCAS: Scan string – REPNE / REPNZ: repeat while not equal
– LODS: Load string or not zero
– STOS: Store string

• Indirect, indexed addressing with auto-

incrementing/decrementing index
– Indexes: ESI & EDI
– Control flag: DF
– Control flag instruction: CLD and STD
Instructions for Block-Structured Languages

To provide machine-language support for functions normally

found in high-level languages

– ENTER (Enter Procedure): ENTER creates the stack frame

required by most block-structured high-level languages.

– Leave (Leave procedure): LEAVE reverses the actions of the

ENTER instruction. By copying the frame pointer to the stack
pointer, LEAVE releases the stack space used by a procedure
for its local variables.
 Flag Control Instructions
Carry and Direction Flag control instructions
 Flag transfer instructions

• LAHF (Load AH from Flags)

• SAHF (Store AH into Flags)

• PUSHF (Push flags)

• POPF (Pop flags)

• Segment-register transfer instructions • Data pointer instructions
– MOV – LDS (Load pointer using DS)
– POP – LES (Load pointer using ES)
– PUSH – LFS (Load pointer using FS)
– LGS (Load pointer using GS)
– LSS (Load pointer using SS)
•Far control transfer instructions
– Direct far JMP
– Indirect far JMP
– Far CALL
– Far RET
 Miscellaneous Instructions
 Address calculation instruction
• LEA (Load effective address)

 No-operation instruction
• NOP (No operation)

 Translate instruction
• XLAT