UNIT 1
INTRODUCTION TO
80386
Microprocessor
Micro80386processor is a 32-bit processor that holds the ability to carry
out 32-bit operations in one cycle. It has a data and address bus of 32-bit
each. Thus has the ability to address 4 GB (or 232) of physical memory.
Multitasking and protection capability are the two key characteristics of
the 80386 microprocessor. 80386 has internal dedicated hardware that
permits multitasking.
Features of 80386
➢ As it is a 32-bit microprocessor. Thus has a 32-bit ALU.
➢ 80386 has a data bus of 32-bit.
➢ It holds an address bus of 32 bit.
➢ It supports physical memory addressability of 4 GB and virtual memory
addressability of 64 TB.
➢ 80386 supports a variety of operating clock frequencies, which are 16
MHz, 20 MHz, 25 MHz, and 33 MHz.
➢ It offers 3 stage pipeline: fetch, decode and execute. As it supports
simultaneous fetching, decoding, and execution inside the system.
The Internal Architecture of 80386 is divided into 3 sections.
1. Central Processing Unit
Code prefetch Unit
Decoder Unit
Execution Unit
2. Memory management unit
Segmentation
Paging Unit
3. Bus interface unit
Register of 80386
• The 80386 has 32 registers in the following categories:
General Purpose Register
1. Segment Registers
2. Instruction Pointer and Flags
3. Status and Control Registers
4. System Address Registers
5. Debug Registers
6. Test Register
The general registers of the 80386
are the 32-bit registers
EAX Accumulator
EBX Base Register
ECX Count Register
EDX Data Register
EBP Base Pointer
ESP Stack Pointer
ESI Source Index and
EDI Destination Index
Addressing Modes of 80386 Microprocessor
Register addressing Immediate addressing Memory addressing mode
Direct Register based Index Scaled Based Based Based Based
Addressing indirect Addressing Addressing index index scaled Index mode scaled
addressing addressing index with displacement index
mode
with displacement
1. Register Addressing modes
In this mode data is in the registers and the instruction specifies the particular register.
All the register in this mode are on chip so the execution is very fast. External bus is not
required.
Format :
OPCODE DESTINATION REGISTER SOURCE REGISTER
Ex :
MOV EAX , EDX
Copy the content of EDX register to the EAX register
2. Immediate Addressing modes
In this mode constant data has been kept in instruction itself. Immediate data may be 8
bits, 16 bits or 32 bits in length.
Format :
OPCODE REGISTER Address Immediate Operant
Ex :
MOV ECX, 20305060H
This instruction copies 20305060H in the ECX register
3. Memory Addressing modes
In this addressing, memory operands must be transferred to CPU over the
bus.
Direct Register based Index Scaled Based Based Based Based
Addressing indirect Addressing Addressing index index scaled Index mode scaled
addressing addressing index with displacement index
mode
with displacement
Sr. No. Addressing modes Mechanism Example
1 Register Resister Data MOV EAX , EBX
2 Immediate Instruction Data MOV EAX, 12345678H
3 Direct Instruction address Memory data MOV EAX, [12345678H]
4 Register Indirect Register address Memory data MOV EAX, [EBX]
5 Indexed Index Register + displacement address MOV EAX, [ESI +
Memory data 2345678H]
6 Base addressing Base Register + displacement address MOV EAX,
Memory data [EBX+2345678H]
7 Base indexed Base Register + Index Register address MOV EAX, [EBX+ESI]
Memory data
8 Base indexed with Base Register + Index Register +displacement MOV EAX,
displacement address Memory data [EBX+ESI+12345678H]
9 Scaled indexed (Index Register + Scaling) + displacement MOV
address memory data EAX,[4*ESI+12345678H]
10 Base scaled indexed Base Register +( Index register * scaling ) MOV EAX, [EBX+8*ESI]
address memory data
11 Base scaled indexed Base Register +( Index register * scaling ) + MOV EAX.
with displacement Displacement address memory data [EBX+2*ESI+12345678H]
Instruction Set
Mnemonic:
MOV destination source
MOV operand 1 operand 2
FLAG Control
Instructions
Instruction Description Effect
STC Set carry flag CF = 1
CLC Clear carry flag CF = 0
CMC Complement carry flag CF = NOT (CF)
CLD Clear direction flag DF=0
STD Set direction flag DF=1
