This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2019.2942540, IEEE
Transactions on Industrial Electronics
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A PWM ZVS High-Frequency-Link Three-Phase

Inverter with T-type NPC Unfolder
Anirban Pal, Student Member, IEEE, Kaushik Basu, Senior Member, IEEE

Abstract—In this paper a pulse width modulated (PWM) (MCT) technique. Small DC link filter capacitors are used to
single-stage high frequency link (HFL) three-phase DC-AC filter out the switching frequency components.
converter is proposed for grid integration of solar and fuel The PWM single-stage HFL converters are of two types-
cell based energy sources. On the DC side, the converter
has three half-bridge legs which are zero-voltage switched cyclo-converter type HFL (CHFL) [9]–[11] and rectifier type
(ZVS) over the entire line cycle without using any additional HFL (RHFL) [12], [13]. In a CHFL topology, high frequency
snubber circuit. On the AC side, two diode bridge rectifiers (HF) AC is generated from DC input using H-bridge and
and one neutral point clamped (NPC) T-type three-level is fed to HFT. In the secondary, cyclo-converter is used to
inverter are employed. The active switches in NPC inverter get line frequency AC from HF AC. The operation of the
are switched either at line frequency or twice of it, incurring
negligible switching loss. Modulation ensures soft commu- cyclo-converter can be divided in two parts- first rectification
tation in the diode bridges. The intermediate three level of HF AC and then line frequency inversion [14]. In a
DC bus is pulsating and does not require any DC filter RHFL topology, instead of using a cyclo-converter, a rectifier
capacitor and thus reduces overall filtering requirements. followed by a voltage source inverter (VSI) is used in the
The high frequency galvanic isolation provides high power secondary. Here intermediate DC link is pulsating.
density, low cost converter solution. The converter opera-
tion is analysed in detail and verified on a 2 kW hardware Unidirectional PWM RHFL DC-3φ AC converter topologies
prototype. [15]–[20] are becoming popular in applications like grid
Index Terms—Phase shift modulation, DC-AC power con- integration of PV, fuel cell where the power flow is unidi-
version, high frequency link, zero voltage switching, three- rectional (from source to grid). But in case of large scale PV
phase unfolder, NPC T-type three-level inverter, single- plant, reactive power support with power factor ± 0.9/0.95
stage power conversion is essential at the grid end [21]. The unidirectional topologies
can be broadly classified in two categories based on the ability
I. I NTRODUCTION to support limited amount (±0.866 PF) of reactive power at
INGLE-stage high frequency link (HFL) DC-AC convert- the AC port.
S ers are becoming attractive solution for applications like
grid integration of renewable energy sources [1]–[3], power
In [15]–[18], the presented topologies can support upto
±0.866 power factor load. These converters employ a hybrid
train in electric and hybrid vehicle [4], battery based storage modulation strategy. In [15]–[17], the AC side 3φ VSI is
system [5], UPS [6] etc. These compact, high power density high frequency switched only for one third of the line cycle
and low cost converters employ high frequency galvanic isola- thus reducing the switching loss of the converter. In [15],
tion instead of conventional line frequency transformers which the DC side high frequency inverter is also soft switched. In
are bulky and costly. These converters also avoid use of bulky [18], the secondary has a three level NPC inverter where the
interstage DC link filter capacitor and thus reduce overall active switches are high frequency switched for one sixth of
filtering requirements and increase the system reliability. the line cycle. The DC side converter is hard-switched and
additional snubber circuits are used for transformer leakage
The single-stage three-phase HFL inverter topologies dis-
energy commutation.
cussed in literature can be broadly classified into two
The topologies in [19], [20] can support only UPF load and
categories- resonant and PWM type. In [7], a three-phase
require additional shunt compensator to support any reactive
bidirectional DC-AC converter is presented. It has two isolated
power demand by the load. Here all the active switches in the
dual-bridge series resonant converters (DBSRC) followed by a
AC side are line frequency switched. But the high frequency
three-level unfolder. The dual bridge series resonant converter
switched DC side converters are partially soft-switched.
has following problems- high circulating current, load depen-
This paper introduces a unidirectional PWM high frequency
dency of voltage gain and constant frequency duty modulation
link DC- 3φ AC converter (in Fig. 1) which can support
resulting in limited range of soft-switching [8]. To reduce
upto ± 0.866 power factor operation. All active switches
tank current, [7] employs complex minimum current trajectory
in the AC side NPC T-type three-level unfolder are low
frequency (LF) switched, incurring negligible switching loss.
Manuscript received March 12, 2019; revised June 15, 2019 and Modulation strategy ensures zero voltage switching (ZVS) of
August 22, 2019; accepted September 1, 2019. This work was sup- all six active switches in the DC side bridge over complete
ported by Department of Science and Technology, Government of India
under the project titled “Development of an advanced System-On-Chip line cycle without additional snubber. The proposed converter
(SoC) based embedded controller for power electronic converters”. with suggested modulation scheme has following additional
(Corresponding author : Anirban Pal). features. (i) PWM is implemented in the DC side bridge.
The authors are with the Department of Electrical Engineering, In-
dian Institute of Science, Bangalore 560012, India. (e-mail: anir- (ii) The secondary diode bridges are soft commutated. (iii)
banp@iisc.ac.in; kbasu@iisc.ac.in). Intermediate three level DC link is pulsating and does not

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Fig. 1: Configuration of the proposed inverter

require any DC filter capacitor. (iv) High frequency galvanic
isolation results in compact, low cost converter solution.
The organisation of this paper is as follows. The converter
structure is described in section II. In section III modulation
strategy is discussed. The steady state operation of the con-
verter over a switching cycle along with soft-switching condi-
tions are presented in section IV. Key experimental results are
presented in section V. Converter power loss and measured
efficiency are shown in section VI. Topology comparison is
presented in section VII.
II. P ROPOSED I NVERTER
The proposed inverter is shown in Fig. 1. In the DC side
converter (DSC), a full bridge, SA1 − SB2 along with a half
bridge leg, S1 −S2 are employed. The output of the full-bridge
(SA1 − SB2 ) is fed to two high frequency transformers (HFT),
T r1 and T r2 with turns ratio n : 1. The primary windings
of T r1 and T r2 are connected in series and the common
point is shorted with the pole (N ) of S1 − S2 . The secondary Fig. 3: Modulation of DC side bridge
windings of T r1 and T r2 are connected to two diode-bridge
rectifiers D1 −D4 , D5 −D8 respectively. The output terminals leg a is connected to p, leg b to q and leg c to o, i.e.
of the diode-bridges are connected in series. A three-level T- Qap , Qbq , Qco are ON. To generate √ balanced three-phase
type neutral point clamp (NPC) 3φ inverter is used to generate average line to line voltages, v ab = 3Vpk sin(ω
 o t=θ),v bc =
√ √

2π 2π
the line frequency AC voltages from the rectifier output. The 3Vpk sin θ − and v ca = 3Vpk sin θ + with
converter is connected to a balanced 3φ voltage source through 3 3
2π
filter inductors Lf as shown in Fig. 1. angular frequency ωo = , the operation of the converter is
To
III. M ODULATION STRATEGY divided into six equal sectors over a line cycle, (θ ∈ [0, 2π]),
as shown in Fig. 2. In each sector, the two line-line voltages
with non-maximum magnitudes are plotted with respect to
(w.r.t) a common phase (see Fig. 2) e.g. v ac and v bc in sector
2. Here c is the common phase and w.r.t c, v ac > 0 and
v bc < 0. In sector 2, the average rectifier output voltages
are v po = v ac and v oq = −v bc as shown in Fig. 2. Hence,
in this sector, the common phase c should be connected to
node o and phase a and b should be connected to nodes
p and q respectively through the NPC inverter legs. Thus
the switching state of the NPC inverter in sector 2 is (pqo).
Similarly, the switching states in other sectors can be obtained
and are shown in Fig. 2. As the switching states are changed
at the beginning of each sector and remain same throughout a
sector, the NPC inverter is low frequency switched incurring
negligible switching loss. Following the switching states, two
quadrant switches (Qap − Qcq ) are line frequency switched
and the four quadrant switches (Qao − Qco ) are switched at
twice of the line frequency.
Fig. 2: Switching states of NPC inverter The DSC is phase shift modulated (PSM) to generate
The pole a can be connected to the nodes p, o and q mpo Vdc
average rectifier output voltages v po = and v oq =
through the NPC inverter leg a (Qap , Qao , Qaq ) (see Fig. n
moq Vdc
1). The switching state of the NPC inverter, (pqo), implies . mpo and moq are the modulation signals as shown in
n

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2019.2942540, IEEE
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Fig. 4: Control circuit of the converter

1.5nVpk
Fig. 2 with peak M = . The modulation strategy over
Vdc
a switching cycle Ts is shown in Fig. 3. F is a high frequency
(HF) square wave signal with period Ts and 50% duty ratio.
Ts is considered to be flux balance cycle of the HFTs. A Fig. 5: Converter current waveforms at UPF operation
unity magnitude, unipolar saw-tooth carrier (C) with period
Ts
, aligned with F is considered. Two switches in each half-
2
bridge leg of the DSC are complementary switched with a dead
time to avoid short circuit of the DC source, Vdc . F is assigned
to be the gating signal of S1 , GS1 . The modulation signals mpo
and moq are compared with the saw-tooth carrier to generate
the gating signals of SA1 − SA2 and SB1 − SB2 respectively.
Slowly varying modulation signals are approximated as con- Fig. 6: Phasor diagram at UPF operation
stant over a switching cycle Ts . The gating signal of SA1 ,
GSA1 is (a square wave with period Ts and 0.5 duty ratio)  π  π
mpo Ts ip = ia = Ipk sin θ − and iq = −ib = Ipk sin θ + .
phase shifted by w.r.t F . Similarly, the gating signal of 6 6
2 Similarly, in other sectors ip and iq can be defined. As seen
moq Ts in Fig. 5, ip and iq have maximum values of Ipqmax = Ipk
SB1 , GSB1 is phase shifted by w.r.t F as shown in Fig.
2 and minimum values of Ipqmin = 0.5Ipk . Fig. 5 also shows
3. The suggested modulation strategy generates pulse width
modulated (PWM) high frequency AC voltages vN A and vN B √ waveform of (ip + iq ) with maximum value I(p+q)max =
the
with voltage levels ±Vdc and 0 which are fed to T r1 and T r2 3Ipk and minimum value I(p+q)min = 1.5Ipk respectively.
respectively. In the secondary, the diode bridges D1 − D4 and Due to diode bridges, ip and iq have to be positive in-
D5 −D8 rectify the high frequency AC and generate pulsating stantaneously, in each sector. Let us consider sector 2, where
DC voltages vpo and voq with required average v po , v oq ip = ia and iq = −ib . V ab , V ang , V bng , I a and I b are the
respectively. The control circuit of the proposed converter is phasor quantities of v ab , v ang , v bng , ia and ib respectively. As
shown in Fig. 4. The controller gives the three phase reference seen in Fig. 6, in sector 2 (S-2), ip becomes negative, if ia lags
voltage signals vab,ref = vVdc ab
, vbc,ref and vca,ref . Using the more than 30◦ and iq < 0, if ib leads more than 30◦ . Which
n cannot be supported by the diode bridges. Due to waveform
reference voltages, the sector signals can be generated. Using
symmetry, similar observations can be made in other sectors
sector informations and voltage references, gating pulses of
also. Thus the converter can support upto ±30◦ leading and
NPC inverter and the modulations signals mpo and moq are
lagging power factor operation.
obtained. The gating signals of the DSC are generated by
employing comparators and logic gates as shown in Fig. 4. IV. S TEADY STATE OPERATION AND SOFT- SWITCHING
The converter operation at UPF, over one switching cycle
Fig. 5 shows the properly filtered, ripple
 free line currents Ts , is described in detail when the converter is in sector 1.
 π 5π In other sectors, similar switching strategy is followed. In
ia = Ipk sin θ − , ib = Ipk sin θ − and ic =
6 6 the analysis, DSC device capacitances (Cs ) and the leakage
 π 
inductances (seen from primary) Llk1 , Llk2 of T r1 and T r2 re-
Ipk sin θ + for unity power factor (UPF) operation of
2 spectively are considered. Considering the leakage inductances
the converter. ip and iq are the output currents of the rectifiers
D1 −D4 and D5 −D8 respectively at UPF operation. Following of the transformers are of same order, Llk1 ' Llk2 = Llk .
The DSC active switches are zero voltage switched (ZVS)
 
π 2π
the NPC inverter switching state in sector 2 ≤θ≤ , over complete line cycle (To ). ZVS is achieved using Cs
3 3

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and Llk . Following the switching state in sector 1, the NPC

inverter switches Qao , Qbq and Qcp are kept ON (see  Fig.π2).

Hence, ip = ic = Ipk cos θ and iq = −ib = Ipk sin θ + .
6
As the switching state of the NPC inverter remains same
over the sector, it can be replaced by two current sinks Ip
and Iq at the rectifier output stage (see Fig. 8a). Ip and
Iq are the rectifier output currents, ip , iq , respectively, over
Ts and can be considered as constant current sinks, if ia,b,c (a)
are properly filtered with negligible ripple. In the following
analysis Ip > Iq is considered (θ ∈ [0, π6 ]). Thus mpo > moq
as seen in Fig. 2. The analysis will be similar in the other
half of the sector 1, when Ip < Iq . What follows is a detailed
description of the switching process of the DC side bridge
and current commutation of AC side diode bridges in one (b)
half of the switching cycle. In the other half cycle, circuit Fig. 8: Mode I-(a) circuit diagram, (b) equivalent circuit
evolves in similar fashion. Fig. 7 presents key waveforms
during switching transitions.

(a)

(b)
Fig. 9: Mode II-(a) circuit diagram, (b) equivalent circuit

across SB1 . The equivalent circuit is shown in Fig. 9b. The

voltage dynamics across SB1 − SB2 can be described by (1).
Iq
vSB1 = Vdc − (t − t1 )
2nCs
(1)
Iq
vSB2 = (t − t1 )
2nCs
At t2 , vSB1 = 0. The anti-parallel diode across SB1 is forward
biased.
C. Mode III (t2 < t < t3 Fig. 10)
Fig. 7: Important switching waveforms over Ts
A. Mode I (t0 < t < t1 Fig. 8)
S1 , SA2 and SB2 are conducting in the DSC. Vdc is applied
across HFT primary terminals N A and N B. In the secondary,
D2 , D3 and D5 , D8 are conducting Ip and Iq respectively.
Reflected transformer primary currents iA,B are shown in Fig.
Ip Iq Ip + Iq
7. iA = − , iB = − and iN = . Equivalent
n n n
circuit is shown in Fig. 8b. The voltage polarity and current (a)
directions indicate the active power transfer from DC source
to load through both the transformers and diode bridges.
B. Mode II (t1 < t < t2 Fig. 9)
At t1 , SB2 is turned OFF. Due to Cs voltage across SB2
changes slowly which reduces turn OFF loss. iB starts charg- (b)
ing the capacitance across SB2 and discharging the capacitance Fig. 10: Mode III-(a) circuit diagram, (b) equivalent circuit

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The anti-parallel diode of SB1 is conducting. The primary

terminals N , B of T r2 is shorted. In this mode, no active
power is transferred from source to load through T r2 and the
diode bridge D5 − D8 . The voltage across N A is Vdc . Active
power is transferred from source to load trough T r1 and diode
bridge D1 −D4 . Equivalent circuit is shown in Fig. 10b. Gating
pulse of SB1 is applied in this mode to achieve ZVS turn ON
of SB1 when the anti-parallel diode is conducting. To achieve (a)
ZVS turn ON of SB1 the dead time (DTB ) between the gating
signals of SB1 − SB2 is given in (2).
2nCs Vdc
DTB ≥ (2)
Iq
2nCs Vdc (b)
is maximum when Iq is minimum i.e. Iq =
Iq Fig. 12: Mode VI-(a) circuit diagram, (b) equivalent circuit
Ipq,min = 0.5Ipk at θ = 0. So, to achieve ZVS turn ON
2nCs Vdc 4nCs Vdc
through out the line cycle DTB ≥ = .
Ipq,min Ipk through diode bridges. The equivalent circuit is shown in Fig.
D. Mode IV (t3 < t < t4 ) 12b. The transition can be described by (3).
At t3 , SA2 is turned OFF. Due to device capacitance the
voltage across SA2 changes slowly thus reduces turn OFF loss. iA + iB + iN = 0
In this mode the circuit dynamics is similar as discussed in vS1 + vS2 = Vdc
Mode II. At the end of this mode the anti-parallel diode of Cs (dvS1 /dt − dvS2 /dt) = iN (3)
SA1 is forward biased.
diA diB
vS1 = Llk = Llk
E. Mode V (t4 < t < t5 Fig. 11) dt dt
Equation (3) is solved with initial conditions vS1 (t5 ) = 0,
(Ip + Iq ) (Ip ) (Iq )
iN (t5 ) = , iA (t5 ) = − and iB (t5 ) = − .
n n n
The voltage across S1 , vS1 and currents are given in (4).
ωr Llk
vS1 (t) = (Ip + Iq ) sin ωr (t − t5 )
2n
(Ip + Iq )
iN (t) = cos ωr (t − t5 )
n (4)
(a)
Ip Ip + Iq
iA (t) = − + (1 − cos ωr (t − t5 ))
n 2n
Iq Ip + Iq
iB (t) = − + (1 − cos ωr (t − t5 ))
n 2n
1
Where ωr = √ . This mode ends at t6 when vS1 =
(b) Llk Cs
Fig. 11: Mode V-(a) circuit diagram, (b) equivalent circuit Vdc and vS2 = 0. From (4), to completely charge Cs across
S1 to Vdc , following condition needs to be satisfied- (Ip +
After t4 , the anti-parallel diode of SA1 is conducting. Now 2nVdc
Iq ) ≥ . Otherwise, the circuit enters into a resonating
both transformer primaries are shorted by S1 and anti-parallel ωr Llk
diodes of SA1,B1 . The converter is in zero state and no active oscillation mode and results in hard turn ON of S2 . As seen
power is transferred from DC source to load. The equivalent in Fig. 5, the minimum value of (Ip + Iq ) over a line cycle is
circuit is shown in Fig. 11b. Gating signal of SA1 is applied in I(p+q),min = 1.5Ipk . So, the condition on Ipk is given in (5).
this state to ensure ZVS turn ON. Like SB1 − SB2 , dead time 4nVdc
between the gating signals of SA1 − SA2 should be DTA ≥ Ipk ≥ (5)
4nCs Vdc 3ωr Llk
.
Ipk
G. Mode VII (t6 < t < t7 Fig. 13)
F. Mode VI (t5 < t < t6 Fig. 12)
After t6 , the anti-parallel diode across S2 starts conducting
At t5 , S1 is turned OFF. The device capacitance helps to
iN . To achieve ZVS ON, gating pulse of S2 is applied when
reduce turn OFF loss by slowing down the rise of voltage
the anti-parallel diode is conducting. The dead time DTN
across S1 . The pole current iN starts charging the capacitance
between the gating pulses of S1 − S2 should satisfy (6).
across S1 and discharging the capacitance across S2 . Appeared
voltage polarity across N A and N B forward bias D1 , D4
 
1 4nVdc
and D6 , D7 . Secondary windings of T r1 and T r2 are shorted DTN ≥ (t6 − t5 )max = sin−1 (6)
ωr 3ωr Llk Ipk

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(a) (a)

(b) (b)
Fig. 13: Mode VII-(a) circuit diagram, (b) equivalent circuit Fig. 15: Mode IX-(a) circuit diagram, (b) equivalent circuit

The equivalent circuit in this mode is shown in Fig. 13b. The

primary currents, iA and iB are changed linearly. iA,B,N are
given in (7).
Vdc
iA = iA (t6 ) −
(t − t6 )
Llk
Vdc
iB = iB (t6 ) − (t − t6 ) (7)
Llk (a) (b)
2Vdc
iN = iN (t6 ) − (t − t6 ) Fig. 16: (a) ZVS bound of leg N (b) ZVS bound of leg A, B
Llk
In the secondary, current changes linearly between diode pairs is in next active state. Active power is transferred from DC
(D1,4 ), (D2,3 ) and (D5,8 ), (D6,7 ). Current through D5 and D6 source to load through both the transformers and the diode
are shown in Fig. 7. As S2 , SA1,B1 are ON, iA , iB and iN can bridges. The equivalent circuit is shown in Fig. 15b. The circuit
change their direction and build up in the opposite directions. condition is similar as in M ode I.
Iq
At t7 , when iB = , this mode ends.
n J. Estimation of ZVS bounds of the DSC
H. Mode VIII (t7 < t < t8 Fig. 14) During the switching transitions of leg A and B, the pole
currents iA,B do not change direction. Whereas the pole
current iN changes its direction during the switching transition
of S1,2 . Which puts a strict upper limit on dead time (DTN ) to
achieve ZVS turn ON of S1,2 . What follows is a procedure q to
find out the upper limit of DTN . Let, R = Ipk , Ro = LClks
nVdc

I +I
and x0 = 3R 4R
o
. As in Fig.7, at t5 , iN (t5 ) = p n q . The
minimum value of Ip + Iq is 1.5Ipk (at θ = 0 and π3 in
1.5Ipk
(a)
sector 1, Fig. 5). p Hence iN (t5 )min = n . Using (4),
1.5Ipk 02
iN (t6 )min = n (1 − x ). It can be shown that, iN falls
to zero at tZ with a slope 2V Llk . Hence, (tZ − t6 )min =
dc
√
Llk 1 1−x 02
2Vdc iN (t6 )min = ωr x0 . From (6), at θ = 0 and π3
in sector 1, (t6 − t5 ) = ω1r sin−1 x0 , which is also the
π
lower limit of DTN . Hence, at θ = 0 and √ 3
, (tZ − t5 ) =
(b)
1 −1 0 1 1−x02
(t6 −t5 )+(tZ −t6 )min = ωr sin x + ωr x0 . Combining
Fig. 14: Mode VIII-(a) circuit diagram, (b) equivalent circuit
(6), the limits on DTN is expressed as (8) and is shown in Fig.
D5 and D8 are reverse biased and stop conducting whereas
D6 and D7 are conducting Iq . The equivalent circuit is shown
Vdc
in Fig. 14b. iA and iN changes linearly with slope L lk
. At t8 ,
Ip Ip + Iq
iA = , iN = − and this mode ends.
n n
I. Mode IX (t8 < t < t9 Fig. 15)
After t8 , D2 , D3 are reverse biased. D1 and D4 conduct Ip .
In the primary, S2 , SA1 and SB1 are conducting. The converter
Fig. 17: Hardware prototype

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(a) (b)
(a)

(c) (d)
Fig. 19: (a) [CH1] HFT primary voltage- vN A , rectifier output voltages-
[CH2] vpo , [CH3] voq (500V/div), [CH4] NPC inverter pole voltage- vab
(1kV/div.). (b) Waveforms over switching cycle- [CH1]-[CH2]: vN B , vN A
(250V/div.) and [CH3]-[CH4]: iB , iA (20A/div.). (c) [CH1] vAB , [CH2]-
[CH4]: vpq , vpo , voq (500V/div). (d) [CH1] vab (1kV/div)., [CH2]-[CH4]:
vpq , vpo , voq (500V/div).
(b)

(a) (b)
Fig. 20: (a) Non UPF operation (PF-0.89 lagging)- [CH1]: va0 ng
(c) (250V/div.), [CH2]-[CH4]: ia , ip and iq (10A/div.), (b) Non UPF operation
(PF-0.896 leading)- [CH1]: va0 ng (250V/div.), [CH2]-[CH4]: ia , ip and iq
(10A/div.)
complete line cycle whereas SA1 − SB2 are hard-switched in
some small durations of the line cycle.
The above discussion shows the switching process of the
converter in one half of the switching cycle Ts in sector 1. In
next half of the switching cycle, similar switching sequences
are followed with other symmetrical switches. In other sectors,
though the switching states of the NPC inverter will change,
(d) still the NPC inverter can be modelled as two current sources
Fig. 18: (a) UPF operation- [CH1] va0 ng (100V/div.), [CH2]-[CH4]: line Ip and Iq connected across the rectifier outputs. So, similar
currents (20A/div.). (b) [CH1]-[CH4]: ia , ip , iq (20A/div.), DSC pole currents circuit dynamics as discussed above, will be observed through
iA,N (50A/div.) . (c) Line switching of NPC leg- [CH1] ia (20A/div.), [CH2]-
[CH4]: Gate-emitter voltages of Qap , Qao , Qaq (25V/div.). (d) Unbalance
out the line cycle.
operation- [CH1]-[CH3]: ia , ib and ic (5A/div.). V. E XPERIMENTAL RESULTS
16a. DTN0 is device technology imposed minimum required A. Setup and operating condition
0.75Ipk Llk
dead time. When x0 << 1, DTN ≤ ωr1x0 = nVdc .
Similarly, the lower limit of the dead times of leg A − B, TABLE I: Operating condition
(DTA,B ≥ 4nC s Vdc
Ipk ) is given in (8) and is shown in Fig. 16b.
0
Output power (P ) 2.15kW
DTA,B is the minimum dead time requirement imposed by DC input (Vdc ) 230V
the device technology. √ HFT turns ratio√(n) 3/4
1 − x02 L-L peak voltage ( 3Vpk ) 270V
sin−1 x0 ≤ωr DTN ≤ sin−1 x0 + Switching frequency (fs = T1 ) 20kHz
x0 (8) s
ωr (DTA,B ) ≥ 3x0 Line frequency (fo = ω o
2π
) 50Hz

In this section, the soft-switching conditions of the DSC The operation of the converter discussed so far is exper-
are derived for UPF operation of the converter. At UPF, soft- imentally verified in a 2kW hardware prototype. The ex-
switching can be achieved for all the switches of the DSC over perimental hardware is shown in Fig. 17. Table I presents
the complete line cycle. Similar conditions can be derived for the operating condition. The active switches in DSC are
other power factor operation. It can be shown that at ±30◦ PF implemented with 1200V, 75 A SEMIKRON IGBT modules
operation, soft turn ON of S1 − S2 can be achieved over the and are switched at 20kHz. IXYS 1200V, 75A diode modules

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(a) (b) (c)

Fig. 21: Switching transition waveforms- (a) Turn OFF of S2 and turn ON of S1 . (b) Turn OFF of SA1 and turn ON of SA2 . (c) Turn OFF of SB1 and
turn ON of SB2 .
MEE 75-12 DA are used in the secondary rectifiers. The NPC and voq are shown in [CH2] and [CH3] respectively. The
inverter is implemented with INFINEON IKW40N120H3 dis- Vdc
pulsating vpo and voq have voltage levels = 307 V and 0.
crete IGBTs (1200V, 40A). Optically isolated gate drivers n
Thus Fig. 19a verifies pulsating intermediate DC link without
ACPL-339J are used to drive all the IGBTs with gate-emitter
any capacitor. In [CH4], the NPC inverter pole voltage vab is
voltage levels ±15V . The dead-time provided between two
shown. vab has steady state voltage levels- ±307 V (Vdc /n),
active switches in a leg of DSC is 600 ns which satisfies all
±614 V (2Vdc /n) and 0.
the dead-time limits derived in last section. An overlap time of
The primary voltages (vN A,N B ) and currents (iA,B ) of
800ns is provided between two consecutive gating signals of
T r1 and T r2 are shown in Fig. 19b. This result verifies the
the NPC inverter. The turns ratio of T r1 and T r2 are selected
transformer voltage and current waveforms presented in Fig.
as 51 : 68. EPCOS ferrite E cores (E80/38/20) are used. The
7. Transformer flux balance is achieved over one switching
leakage inductances seen from primary of T r1 and T r2 are
cycle. From the figure, across the primary windings, 0 to ±Vdc
6.5 µH and 5.3 µH respectively. Additional series inductance
transitions happen simultaneously in both the transformers.
of 36 µH is connected in series with each primary winding
At these instants, S1 − S2 are switched and iA,B change
to achieve soft-switching of the DSC and hence Llk ' 42µH.
directions. But ±Vdc to 0 transitions are not synchronised.
2.5 mH inductance is used as line filter (Lf ) at the converter
Fig. 19c shows the pulse width modulated high frequency
output. Xilinx Zynq-7010 based control platform is used to
AC voltage, vAB . The voltage levels of vAB are ±230 V and
implement the modulation strategy.
0. The secondary DC link voltage vpq is shown in [CH2]. The
B. Verification of modulation strategy 2Vdc Vdc
pulsating vpq has voltage levels = 614 V, = 307 V
The converter is connected to√ a balanced 3φ voltage source n n
and 0 V. The rectifier output voltages vpo and voq are shown
v(a0 b0 c0 )ng with line-line peak ( 3Vpk ) 270V. The input DC in [CH3] and [CH4] respectively.
supply is 230 V. Fig. 18a presents the UPF operation of the Fig. 19d shows the pulse width modulated pole voltage, vab .
converter with an output power (P ) of 2.15 kW. The phase vab has steady state voltage levels- ±307 V (Vdc /n), ±614 V
voltage va0 ng and line current ia are in same phase as seen in (2Vdc /n) and 0. vpq , vpo and voq are shown in [CH2]-[CH4]
2P
Fig. 18a. The peak of the line current Ipk = = 9.1 A. respectively.
3Vpk Fig. 20a shows the lagging power factor operation of the
3φ balanced line currents ia,b,c are shown in Fig. 18a.
proposed converter. From the figure, ia lags va0 ng by 26.7◦ .
The rectifier output currents ip , iq and DSC pole currents iA
The converter is supplying cos 26.7◦ = 0.89 lagging power
and iN are shown in Fig. 18b over a line cycle. ip and iq have
factor load. This figure also shows rectifier output currents ip
the peak of 9.1 A (Ipk ) and the experimental waveforms are
and iq and they are positive over the line cycle. The converter
matched as shown √ in Fig. 5. The envelope of iA and iN have operation supplying 0.896 power factor leading load is shown
3Ipk 3Ipk
peak values of = 21A and = 18.2A respectively. Fig. 20b. The line current ia leads the output voltage by 26.4◦ .
n 2n
Experimentally obtained envelops of iA and iN are similar to The rectifier output currents ip and iq are shown in Fig. 20b.
what is analytically predicted in Fig. 5.
C. Verification of soft-switching of the DSC legs
Fig. 18c presents the line current ia and gate emitter
voltages of Qap , Qao and Qaq of the NPC inverter. Qap and In the following discussion turn ON transitions of S1 , SA2
Qaq are switched at line frequency (50 Hz) whereas Qao are and SB2 and turn OFF of S2 , SA1 and SB1 are described.
switched at twice of the line frequency. This result verifies the Fig. 21a shows the switching transition of leg S1 − S2 . S2
low frequency switching strategy of NPC inverter. was ON and conducting pole current iN . S1 was blocking
Experimental result of the converter supporting unbalanced vCE,S1 = Vdc . At t− 5 , the gating pulse of S2 is withdrawn.
load is shown in Fig. 18d. The three phase unbalanced line After sometime at t5 , voltages across S1 − S2 start changing.
currents (ia −ic ) have peak values of 6.36A, 3.68A and 6.12A Slow change in voltage across S2 due to device capacitance
respectively. The Phase angles between ia,b , ib,c and ic,a are helps to reduce turn OFF loss of S2 . During this time iN
116◦ , 102◦ and 142◦ respectively. changes as per (4) in Mode VI of section IV. At t6 , vCE,S1 = 0
Fig. 19a shows the pulse width modulated high frequency and after that iN changes linearly as per (7) in Mode VIII of
AC (vN A ) applied across T r1 primary. The voltage levels of section IV. At t+
6 , gating pulse of S1 , vGE,S1 is applied (before
vN A are ±230 V and 0. The rectifier output voltages vpo iN changes its direction). As vCE,S1 = 0, zero voltage turn

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2019.2942540, IEEE
Transactions on Industrial Electronics
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87 8
ON (ZVS) of S1 is ensured. At tZ , iN becomes zero and
86

Power loss (%)

changes its direction. 6

Efficiency (%)
85
Switching transition of SA1 − SA2 is shown in Fig. 21b. 84
4
DSC
Before t− 3 , SA1 was conducting iA and SA2 was blocking 83 2 HFT
DBR
Vdc . At t−3 , gating pulse of SA1 is removed. After sometime 82 0
NPC
0 1 2 3 0 1 2 3
at t3 , voltages across SA1 − SA2 begin to change. Voltage Output Power (kW) Output Power (kW)

across SA1 , vCE,SA1 , slowly builds upto Vdc and the voltage (a) (b)
across SA2 becomes zero at t4 . Slow change in voltage across
DSC
SA1 due to device capacitance helps to reduce turn OFF loss
120
of SA1 . As iA does not change its direction, the anti-parallel Experimental
HF ind.
100 Analytical
diode of SA2 is in conduction after t4 . At t+

Power loss (W)

4 , gating pulse 2.9% 41.45%
80 HFT
of SA2 , vGE,SA2 is applied when vCE,SA2 = 0 and thus ZVS 9.1%
2.54%
60 LF
turn ON is achieved. This transition verifies the operation in
40 18.9%
Mode IV of section IV. 25.1%
20
Switching transition of SB1 − SB2 is presented in Fig. 21c. DSC HFT DBR NPC DBR
NPC

The switching process is similar to the transition of SA1 −SA2 . (c) (d)
The switching process verifies the converter operation in Mode
II and III of section IV. Due to device capacitance, slow rise Fig. 22: (a) Efficiency of the proposed 3φ HFL inverter, (b) Power
in voltage across SB1 helps to reduce turn OFF loss of SB1 . loss at different stages of 3φ HFL inverter. (c) Power loss break down
From Fig. 21c, it is clearly seen that the gating signal of SB2 and (d) Percentage loss distribution at 1.76kW output power.
is applied when the voltage across SB2 , vCE,SB2 is zero and
thus ensuring ZVS turn ON of SB2 . B. Experimentally measured power loss
The converter is operated with input 230V DC for a
VI. P OWER L OSS AND E FFICIENCY variation of output load 0.57kW to 2.42kW. The power loss is
The converter power loss is analytically estimated assuming measured at different stages of the converter. Fig. 22a shows
ripple free line currents. In the analysis only conduction loss is the measured efficiency of the converter. The prototype has
considered as the proposed topology is soft-switched. Power maximum efficiency 86.52 % at 1.76kW output power. The
loss is also obtained experimentally. experimentally obtained power losses in different stages of
the converter are shown in Fig. 22b. The experimental and
A. Analytical loss estimation analytical loss distribution of the converter at 1.76kW output
The conduction loss in switch S1 and SA1 are given in power is shown in Fig. 22c. As seen from the figure, the
(9). Due to operation symmetry, leg A and B switches have analytically estimated power losses at the different stages of
same loss. The conduction loss in anti-parallel diode of SA1 is the converter are closely matched with the experimentally
given in (9). VCE , VD and RCE , RD are the constant voltage obtained losses. A pie chart showing the share of loss in
drop and on state resistance of the IGBT switches and diodes different stages at 1.76kW output power is shown in Fig. 22d.
respectively.
TABLE II: Topology Comparison
2
0.83VCE,S1 Ipk RCE,S1 Ipk Proposed [17] [20] PSFB+
PCS1 = + 1.37 2 topology 3φ VSI
n √ n
Active switch count 18 12 14 10
M VCE,SA1 Ipk 5 3M 2 No. of diodes 8 6 12 4
PCSA1 = + RCE,SA1 Ipk Load support (PF) ±0.866 ±0.866 UPF Any
4n 12πn2 (9) DSC ZVS Hard- Partially ZVS
VD,SA1 Ipk switched ZVS
PCD,SA1 = (0.41 − 0.254M )
n ASC LF switched Partially HF LF HF
2 Switched switched Switched
RD,SA1 Ipk Intermediate No No No Yes
+ (0.353 − 0.23M ) DC link Filter
n2
The conduction loss in ASC diode D1 , NPC inverter switch TABLE III: Devices used in experiment and optimal design
Qap and Qao are given in (10). Part No. VCE /VD RCE /RD
SKM75GB123D
2 Used 1.8V 38 mΩ
PCD1 = 0.41VD1 Ipk + 0.36RD1 Ipk DSC (1200V, 75A)
Optimal IRFP4137PbF
2 - 56mΩ
PCQap = 0.276VCEap Ipk + 0.235RCEa1 Ipk (10) Design (300V, 38A)
2 MEE 75-12 DA
PCQao = 0.04VCEao Ipk + 0.014RCEao Ipk Used 1.5V 3.65mΩ
DBR (1200V, 75A)
Optimal DPG20C400PC
0.77V 19.8mΩ
2 2 Design (400V, 20A)
The conduction loss of HFT is given as Ip,HF T (Rp + n Rs ).
0.84Ipk IKW40N120H3
Used 2.05V -
Where Ip,HF T = n is the RMS current of the primary NPC (1200V, 40A)
Optimal IKP28N65ES5
winding. Rp and Rs are primary and secondary winding Design (650V, 28A)
1.06V 14mΩ
resistance. At the switching frequency the HFT core loss is
negligible. The experimental prototype is not optimally designed for

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2-3kW power level and hence has the relatively low peak effi- over 0 < θ < π3 . In a switching cycle (Ts ), S1 conducts half
ciency of 86.52%. We have optimally designed the converter of Ts . The RMS current, average current and the conduction
at 2.15kW with the devices listed in Table III. The design loss PCS1 of S1 are given in (11).
has an analytically estimated efficiency of 94.7%. The method Z π3 2 2
of analytical estimation is already verified with the existing 3 3Ipk 2 π
  Ipk
IS21 ,rms = cos − θ dθ = 1.37
hardware. As the chosen devices in the optimal design has 2π 0 n2 6 n2
better conduction loss parameters as shown in Table III and Z π3 √
3 3Ipk  π  Ipk (11)
as the loss is primarily due to conduction, the optimal design IS1 ,avg = cos − θ dθ = 0.83
2π 0 n 6 n
has better efficiency. 2
0.83VCE,S1 Ipk R I
CE,S1 pk
VII. TOPOLOGY COMPARISON PCS1 = + 1.37
n n2
The proposed topology is compared with the single stage
topologies presented in [17], [20] and a conventional multi- Following similar process, the losses in other switches and
stage topology (PSFB followed by a 3φ VSI). Key features diodes are obtained.
are summarised in Table II. The multi-stage topology uses
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2019.2942540, IEEE
Transactions on Industrial Electronics
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Anirban Pal (S’17) received the B.E. and M.E.

degrees from the Indian Institute of Engineering
Science and Technology, Shibpore, India in 2010
and the Indian Institute of Science, Bangalore,
India in 2015, both in electrical engineering. He
is currently pursuing the Ph.D. degree at the
Electrical Engineering Department, Indian Insti-
tute of Science, Bangalore, India. From 2010
to 2013, he worked as an Assistant Manager
in National Thermal Power Corporation Limited.
His research interests include high-frequency-
link inverters, dual active bridge converters, resonant converters, soft-
switching techniques, design of high-frequency magnetics.

Kaushik Basu (S’07, M’13, SM’17) received

the BE. degree from the Bengal Engineering
and Science University, Shibpore, India, in 2003,
the M.S. degree in electrical engineering from
the Indian Institute of Science, Bangalore, In-
dia, in 2005, and the Ph.D. degree in elec-
trical engineering from the University of Min-
nesota, Minneapolis, in 2012, respectively. He
was a Design Engineer with Cold Watt India in
2006 and an Electronics and Control Engineer
with Dynapower Corporation USA from 2013-15.
Currently he is an Assistant Professor, in the Department of Electrical
Engineering in Indian Institute of Science. He has been an author and
coauthor of several technical papers published in peer reviewed journals
and conferences. His research interests include various aspects of the
general area of Power Electronics. He is the founding chair of both IEEE
PELS and IES Bangalore Chapter.

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