Solution of Assignment 3

CMOS Analog IC Design

Prepared by Sachin Kumar(S23100)
Instructor : Prof. Hitesh Shrimali
School: SCEE (IIT MANDI)
September 20, 2025

Figure 1:

1
 W
iD = K ′ (VGS−VT )2 (1)
L
µCox
K′ = (2)
s2
2iD
VGS = + VT (3)
k′ W
L
  2
′ W
io = K2 VGS − VT (4)
L 2
  s 2
′ W 2iD
io = K2 + VT 1 − VT 2 (5)
L 2 K1′ ( W )
L 1

K1′ K2′ (W/L)1 (W/L)2 VT 1 VT 2

IO (min) Max Min Max Min Min Max
IO (max) Min Max Min Max Max Min

IO (min)
115.5µ 104.5µ 3.316 2.714 0.695 0.705
27.82µ
IO (max)
104.5µ 115.5µ 2.714 3.316 0.705 0.695
56.93µ

2
Q2. Fig. 2 illustrates a reference circuit that provides an
interesting reference voltage output. Derive a symbolic
expression for VREF.
1 Solution

Figure 2:

VGS1 + VGS3 − VGS4 = VREF (6)

VREF = VON 1 + VT 1 + VON 3 + VT 3 − VON 4 − VT 4 (7)
VT 4 = VT 3 (8)
VON 1 = VON 3 (9)
VON 4 = 2VON 3 (10)
VREF = 2VON 1 + VT 1 + VT 3 − 2VON 1 − VT 3 (11)
VREF = VT 1 (12)

3
Q3. Fig. 3 illustrates a current reference. The W/L
of M1 and M2 is 100/1. The resistor is made from
n-well and its nominal value is 400k at 25 °C. Using
Table 1 and an n-well resistor with a sheet resistivity
of 1k/sq. +/- 40calculate the total variation of output
current seen over process, temperature of 0 to 70 °C,
and supply voltage variation of +/- 10threshold voltage
is –2.3 mV/°C.
2 Solution

Figure 3:

4
 q
2IREF
VDD − β
+ VT
IREF = (13)
R
1 q 2IREF VDD − VT
β
= − IREF (14)
R R
Define V = VDD − VT (15)
2IREF
= (V − IREF R)2 (16)
β
 
2 2
IREF R − 2IREF V R + β + V 2 = 0
1
(17)
 
2 V 1 V2
IREF − 2IREF R
+ βR2
+ R2
=0 (18)

V 1 1 q 2V 1
IREF = + ± + β 2 R2
(19)
R βR2 R βR
VDD − VT 1 1
q
2(VDD −VT ) 1
IREF = + 2
± βR
+ β 2 R2
(20)
R βR R

Rmin (25◦ C) = 500kΩ × (1 − 0.4) = 300kΩ (21)

Rmax (25◦ C) = 500kΩ × (1 + 0.4) = 700kΩ (22)

Rmin (0◦ C) = Rmin (25◦ C) × (1 + 8000 × 10−6 × −25)

= 300 × 0.8 = 240kΩ
Rmax (70◦ C) = Rmax (25◦ C) × (1 + 8000 × 10−6 × 45)
= 700 × 1.36 = 952kΩ (23)
VT (min) (25◦ C) = 0.7 − 0.15 = 0.55 (24)
VT (max) (25◦ C) = 0.7 + 0.15 = 0.85 (25)
VT (min) (70◦ C) = 0.55 − 45 × 0.0023 = 0.4465 (26)
VT (max) (0◦ C) = 0.85 + 25 × 0.0023 = 0.9075 (27)
′
K(max) (25◦ C) = 110 × 10−6 × 1.1 = 121 × 10−6 (28)
′
K(min) (25◦ C) = 110 × 10−6 × 0.9 = 99 × 10−6 (29)
 −1.5
′ ′ T
K (T ) = K (T0 ) × (30)
T0
 −1.5
′ ◦ −6 343
K(min) (70 C) = 99 × 10 × = 80.17 × 10−6 (31)
298
 −1.5
′ ◦ −6 273
K(max) (0 C) = 121 × 10 × = 138 × 10−6 (32)
298

5
 K′ VT VDD R
IREF (min) max max min max
IREF (max) min min max min

IREF (min) 80.17 ×10−6 0.9075 4.5 952kΩ

IREF (max) 138 ×10−6 0.4465 5.5 240kΩ

Q4. Fig. 4 illustrates a current reference circuit. As-

sume that M3 and M4 are identical in size. The sizes of
M1 and M2 are different. Derive a symbolic expression
for the output current Iout.
3 Solution

Figure 4:

6
Assume that M3 and M4 make a perfect current mirror,as does M2 and M5 .

VGS2 − VGS1 + IR = 0 (33)

VT 1 + VON 1 − VT 2 − VON 2 = IR (34)
IR = VON 1 − VON 2
s s
2iD 2iD
= ′
− ′
(35)
K (W/L)1 K (W/L)2
r s s !
2iD 1 1
IR = − (36)
K′ (W/L)1 (W/L)2
r s s !
1 2iD 1 1
Iout = − (37)
R K′ (W/L)1 (W/L)2

Q5. Calculate the output resistance and the minimum

output voltage while maintaining all devices in satura-
tion for the circuit shown in Fig. P4.3-6. Assume that
IOUT is actually 10A. Determine the actual output cur-
rent, IOUT. Use Table 1 for device model information.
4 Solution

Figure 5:

7
Assume a near perfect current mirror so that the current in all device is 10µA
s r
2iD 2 × 10 × 10−6
VGS4 = VG4 = + VT = + 0.7
β 1 × 110 × 10−6
q
20
= 110 + 0.7 = 1.126 (38)
s r
2iD 2 × 10 × 10−6
VGS3 = VG3 = + VT = + 0.7
β 4 × 110 × 10−6
q
20
= 440
+ 0.7 = 0.913 (39)
s
2iD p p 
VGS = VG − VS = + VT 0 + γ 2ϕf + VSB − 2ϕf (40)
β
s
2iD p p 
VG − VS = + VT 0 + γ 2ϕf + VS − 2ϕf (41)
β

s
2iD p p p 
VG − VS − − VT 0 + γ 2ϕf = γ 2ϕf + VS − 2ϕf (42)
β
s
2iD p p p 
VG − − VT 0 + γ 2ϕf − VS = γ 2ϕf + VS − 2ϕf (43)
β
p 
A − VS = γ 2ϕf + VS (44)

where
s
2iD p
A = VG − − VT 0 + γ 2ϕf (45)
β

(A − VS )2 = γ 2 (2ϕf + VS ) (46)

A2 − 2AVS + VS2 = γ 2 (2ϕf + VS ) (47)

VS2 − VS (2A + γ 2 ) + A2 − γ 2 (2ϕf ) = 0 (48)

Now solving numerically:

s
2iD p
A = VG − − VT 0 + γ 2ϕf (49)
β
q
20
√
= 1.126 − 440 − 0.7 + 0.4 0.7 = 0.5475 (50)

8
 Definitions:
β = µn Cox WL
(MOSFET process transconductance parameter)
 
ϕf = kT
q
ln NnAi (Fermi potential of the substrate)
√
2qεs NA
γ= (Body-effect coefficient)
Cox

VS2 − VS 2(0.5475) + 0.42 + 0.54752 − 0.42 (0.7) = 0

 
(51)
VS2 − VS (1.255) + 0.1877 = 0 (52)
VS = 0.1736 (53)

s r
2iD 20
VON = = = 0.2132
β 440

VOU T (min) = VON + VS = 0.2132 + 0.1736 = 0.3868

Small signal calculation of output resistance:

r
p 4
gm1 = gm2 ≡ (2K ′ W/L)|I D| = 2 × 110 × 10−6 × × 10 × 10−6 = 93.81 × 10−6
1

γ −6 0.4 −6
gmbs2 = gm2
1/2 = 93.81 × 10 ·  1/2 = 20.07 × 10 (54)
2 2|ϕF | + VSB 2(0.7 + 0.1736)
vout  
rout = = rds1 + rds2 + (gm2 + gmbs2 )rds2 rds1
iout

gds1 = gds2 ≡ ID λ = 10 × 10−6 × 0.04 = 400 × 10−9

1
rds1 = rds2 = = 2.5 × 106
gds

 
rout = rds1 + rds2 + (gm2 + gmbs2 )rds2 rds1 (55)

= 2.5 × 106 + 2.5 × 106 + (93.81 × 10−6 + 20.07 × 10−6 ) · 2.5 × 106 2.5 × 106
 
(56)
rout = 717 × 106 (57)

9
Q6. Design M3 and M4 of Fig. 5 so that the IOUT is
ideally 20A.
5 Solution
s
2iD
VGS = ′
+ VT
K (W/L)

s s
2(5µA) 2(10µA)
VGS (5 µA) = + VT = VGS (10 µA) = + VT (58)
K ′ (W/L)5µA K ′ (W/L)10µA
s s
2(5µA) 2(10µA)
=
K ′ (W/L) 5µA K ′ (W/L) 10µA

5µA 10µA
=
(W/L)5µA (W/L)10µA
(W/L)10µA 10µA
= =2
(W/L)5µA 5µA

(W/L)10µA = 2(W/L)5µA
Thus for Fig. 5:
1 2
(W/L)4 = , (W/L)3 =
2 1

Q7. For the circuit shown in Fig. 6, determine IOUT

using Table 1 for device model information if required.
6 Solution

Figure 6:

So as the property of current mirror if the aspect ratio of trasistor same then
the same current is pass though the transistor Iout = 10µA.

10
Q8. The common-gate stage of Fig. 7 employs the cur-
rent source M3 as the load to achieve a high voltage
gain. For simplicity, neglect channel-length modulation
and body effect in M1. Assuming (W/L)3 = 40/0.18, n
= 0.1V1, and p = 0.2V1, design the circuit for a volt-
age gain of 20, an input impedance of 50, and a power
budget of 13 mW. (You may not need all of the power
budget.)
7 Solution

Figure 7:

Assumptions
1. VDD = 1.8 V (given).
2. Neglect channel-length modulation in M1 , i.e. ro1 → ∞. Hence gain

Av ≈ gm1 ro3 .

3. Input impedance of a common-gate: Zin ≃ 1/gm1 .

Specified Zin = 50 Ω ⇒ gm1 = 1/50 = 0.02 S.
20
4. Desired gain |Av | = 20 ⇒ ro3 = = 1000 Ω.
0.02
5. Given λp = 0.2 V−1 . For PMOS current source:
1 1 1
ro3 = ⇒ ID = = = 5 mA.
λp ID λp ro3 0.2 · 1000
Hence stage power P = VDD ID = 1.8 · 5 mA = 9 mW < 13 mW.
6. Technology parameters (typical 65 nm values):

k ′ n ≡ µn Cox ≈ 300 × 10−6 A/V2 , kp′ ≈ 100 × 10−6 A/V2 .

11
Sizing Calculations
1) M1 (common-gate NMOS). We require gm1 = 0.02 S at ID = 5 mA. Using the
square-law:
2
gm
q
gm = 2kn′ W W



L
ID ⇒ L 1
= .
2kn′ ID
Plugging values:

W

(0.02)2 4 × 10−4
L 1
= = ≈ 133.3.
2 · (300 × 10−6 ) · (5 × 10−3 ) 3 × 10−6

With Lmin = 0.18 µm:

W1 ≈ 24.0 µm, (W/L)1 ≈ 24/0.18

2) M3 (PMOS load). Given (W/L)3 = 40/0.18. Check overdrive:

s s
2I 2 · 5 × 10−3
Vov,3 = = ≈ 0.671 V.
kp′ (W/L)3 100 × 10−6 · (40/0.18)

3) M4 (cascode PMOS). To match bias and current handling:

(W/L)4 ≈ 40/0.18

4) Current mirror NMOSes (MREF , M5 ). To mirror 5 mA reliably, choose same aspect

ratio as M1 :
(W/L)M REF ≈ (W/L)M5 ≈ 24/0.18

5) M2 (bias NMOS). Sized comparably to M1 :

(W/L)2 ≈ 24/0.18

Final Aspect Ratio Summary

Device Aspect Ratio (W/L)
M1 24/0.18
M2 24/0.18
M3 40/0.18 (given)
M4 40/0.18
MREF , M5 24/0.18
Stage current ID ≈ 5 mA, stage power P ≈ 9 mW.

12
Q9. Figure 8 depicts a cascode current source whose
value is defined by the mirror arrangement, M1-M2.
Assume W/L = 5 m/0.18 m for M1-M3. (a) Select the
value of Vb so that Iout is precisely equal to 0.5 mA.
(b) Determine the change in Iout if Vb varies by +/-100
mV. Explain the cause of this change. (c) Determine the
output impedance of the cascode.
8 Solution

Figure 8:

Assumptions:

• Devices M1 –M3 : (W/L) = 5/0.18.

• Process parameter K ′ = 110 × 10−6 A/V2 .

• Threshold VT = 0.40 V.

• Channel-length modulation parameter (NMOS) λn = 0.10 V−1 .

• Reference branch current = 0.5 mA.

• Square-law saturation model: ID = 12 K ′ (W/L)(VGS − VT )2 .

(a) Value of Vb for Iout = 0.5 mA

Overdrive voltage: s
2ID
Vov = ′
K (W/L)
r
5 2(0.5 × 10−3 )
(W/L) = = 27.78, Vov = ≈ 0.572 V.
0.18 110 × 10−6 · 27.78

13
 For cascode bias:

Vb ≈ VT + 2Vov = 0.40 + 2(0.572) ≈ 1.54 V.

Vb ≈ 1.54 V
—

(b) Change in Iout for ∆Vb = ±0.1 V

Small-signal parameters at I = 0.5 mA:
p 1 1
gm = 2K ′ (W/L)I ≈ 1.748 mS, ro = = = 20 kΩ.
λI 0.10 × 0.5 × 10−3
Fraction of ∆Vb appearing at M3 VGS :
   
1 1
∆VGS3 ≈ ∆Vb 1 − = ∆Vb 1 − ≈ 0.97 ∆Vb .
1 + gm ro 36

Current change:

∆I ≈ gm ∆VGS3 = 1.748 mS · (0.97 · 0.1) ≈ 0.17 mA.

∆I ≈ ±0.17 mA
So Iout varies between ≈ 0.33 mA and 0.67 mA.
—

(c) Output resistance of the cascode

rout ≈ gm3 ro3 ro2 + ro3 + ro2 .
With gm3 ≈ 1.748 mS, ro2 = ro3 = 20 kΩ:

gm3 ro3 ro2 ≈ 1.748 × 10−3 · (2 × 104 )2 = 6.99 × 105 Ω.

rout ≈ 7.0 × 105 Ω (≈ 700 kΩ)

This large output resistance demonstrates the benefit of cascode biasing.

14
Q10. For Fig. 9: Assume (W/L)1,2 = 10m/0.18m, Vb
= 0.9 V, and I1 = 1 mA is an ideal current source.
(a) Plot the input/output characteristic and determine
the value of Vin at which the slope (small-signal gain)
reaches a maximum. (b) Now, suppose the biasing cir-
cuitry that must produce the above DC value for Vin
incurs an error of +/- 20mV. From (a), explain what
happens to the small-signal gain.
9 Solution

Figure 9:

Av = −gm1 gm2 ro1 ro2 (59)

gm1 = 3.5m℧
gm2 = 3.5m℧
ro1 = ro2 : 1KΩ(Assume)
Av = 12.25K

Given / assumptions:
10
(W/L)1 = (W/L)2 = , Vb = 0.9 V, I1 = 1 mA,
0.18
K ′ = 110 × 10−6 A/V2 , VT = 0.40 V.

15
 Compute overdrive for the 1 mA branch:
s s
2I 2(1 × 10−3 )
Vov = = ≈ 0.573 V.
K ′ (W/L) 110 × 10−6 · (10/0.18)

The transistor knee (bottom device entering saturation) is at

Vin ≈ VT + Vov ≈ 0.40 + 0.573 ≈ 0.973 V.

Vin,peak ≈ 0.974 V
and the approximate small-signal slope evaluated there:

dVout
≈ −15.8.
dVin peak

Effect of a ±20 mV DC error in Vin :

Evaluating the computed slope at Vin = Vin,peak ± 20 mV yields

dVout dVout
V in = Vin,peak − 20mV ≈ +1.0, V in = Vin,peak + 20mV ≈ +0.17.
dVin dVin

Conclusion: the large magnitude negative peak is very sharp — a DC bias error of only
±20 mV reduces the slope magnitude by more than an order of magnitude. Therefore the
small-signal gain is highly sensitive to DC bias around the knee.

16
Q11. Repeat Problem 10 for the cascode shown in Fig.
10, assuming W/L=10 m/0.18 m for all of the transis-
tors.
10 Solution

Figure 10:

Av = −gm1 (gm3 ro3 ro4 ||gm2 ro2 ro4) (60)

= −gm1 (gm3 ro3 ro4 ) (61)
V out V
VDD = = 18K (62)
V in V
1.8
V in = = 0.1mV (63)
18K

17