1
Constant- Techniques for Rail-to-Rail CMOS
Amplifier Input Stages: A Comparative Study
Shouli Yan, Jingyu Hu, Tongyu Song, and Edgar Sanchez-Sinencio*
Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX 78712, USA
* Department of Electrical Engineering, Texas A&M University, College Station, TX 77843, USA
email: slyan, hu, tsong@ece.utexas.edu, sanchez@ee.tamu.edu
Abstract This paper presents a comparative study of a
number of constant-transconductance ( ) techniques for CMOS
amplifier input stages. The pros and cons of each technique are
discussed. Theoretical analysis along with simulation results are
discussed to demonstrate the performance of each constanttechnique. Finally, we propose a novel technique which achieves
within
variation over the full input common-mode
voltage range. The new technique exhibits improvement over
other existing techniques.
I. I NTRODUCTION
During the past decade, there have been considerable
interests in the design of low-voltage CMOS operational
amplifiers (opamps). Rail-to-rail common-mode (CM) input
voltage range is demanding for a high signal swing and thus a
high signal-to-noise ratio in certain amplifier (such as unity
gain buffer) configurations. The total effective input stage
transconductance ( ) of rail-to-rail input CMOS amplifiers
should be maintained as constant as possible over the entire
input CM voltage range [1] [20]. Hence, necessary constanttechniques need to be developed for rail-to-rail CMOS
opamps. A number of rail-to-rail schemes were proposed in the
past years, and necessitate a detailed review and comparison.
This paper is organized as follows. In section II, several difinput stages are discussed and
ferent schemes of constantcompared. Section III introduces a new constant- technique.
In section IV concludes this paper with with a comparison
table of different input stage schemes.
Throughout this paper we use the following notations.
Total transconductance of the amplifier input stage is denoted
by
. The and are the transconductance
and tail current of the n(p)-channel input differential pairs,
respectively. = and = are the transconductance parameter of the N and P input transistors. The input
CM voltage and slew rate are denoted by
and ,
respectively. The current summation circuits [2] to add the
currents from the constant- N- and P- input differential pairs
together and converts to a single-ended output, are omitted in
the figures for simplicity.
II. R EVIEW AND D ESIGN G UIDELINES OF C ONSTANTT ECHNIQUES
Techniques to maintain a nearly constant
over the
entire
range in rail-to-rail amplifiers have been reported
in [2] [20]. Most of them used N-P complementary input
0-7803-8834-8/05/$20.00 2005 IEEE.
differential pairs (except the ones in [13], [15], [21]). A
simple N-P complementary input stage is shown in Fig. 1(a).
This circuit has a limitation that, at the middle of the input
CM range (i.e., Region II), the total transconductance has
nearly twice the value of a single pair in Region I or III,
as illustrated in Fig. 1(b), due to the fact that there is a large
overlap between the CM swings of the N differential pair M1nM2n and the P differential pair M1p-M2p, as illustrated in
Fig. 1(c). This drawback results in variable DC gain, unitygain bandwidth, nonconstant SR, and non-optimal frequency
compensation [1] [22].
Several guidelines could be followed for constantcircuits. First, the large-signal and small-signal performances of
the rail-to-rail stage should be maintained constant regardless
of the varying
level. Second, the accuracy of the
technique does not rely on any particular characteristic (such
as the MOS drain current square law) and any strict
and matching of the input devices. In other words,
the technique should be universal and robust. Thirdly, the
circuit should allow high-frequency/high-speed operation and
consume low power. Finally, the complexity of the technique
should be moderate. Please note that different applications
may demand different design requirements. For example, high
bandwidth is needed for video applications, while compactness
is demanded for VLSI cell libraries. In this section, we will
give a brief overview of several reported techniques. Due to
the space limitations, not all published constant- techniques
are included.
Technique I Varying Tail Current
A. Constantcan be tackled by altering the
Stabilization of the total
effective tail currents of the input differential pairs. A typical
example is to use square-root circuit [2], [3]. The work in [3]
used new bias circuits not requiring and matching
of input pair transistors for proper operation. Another scheme
is to employ current switches to increase the tail current when
is near power supply rails or to 4 times of the
tail current when
is in the mid-range [2], [4], [5]. The
conceptual circuit is shown in Fig. 2(a) and the real circuit in
Fig. 2(b). When
is close to either (or ), only
SW1 (or SW2) is on. SW1 (or SW2) diverts tail current
from P (or N) pair to the N (or P) pair through a 1:3 current
mirror and thus increase the effective tail current of the active
N (or P) pair by four times. For mid-range
levels, both
stays as the nominal value.
switches are off thus the total
2571
The above square-root circuit and 1:3 current mirror circuit
have two limitations. First, both depend heavily on drain
current quadratic characteristic (i.e., the square-law model)
of the input MOS transistors, thus they can not be applied
universally to strong and weak inversion operation regions, and
are not compatible with deep submicrometer CMOS devices
that do not follow quadratic characteristic accurately. Second,
the SR is a function of
and has a variation of 2 times
from rail to rail. The input stage in Fig. 3(a) overcome these
problems by employing two backup pairs to replace two primary pairs [6]. Transistors M1A-M4A are biased normally and
form two primary pairs, and transistors M1B-M4B are backup
pairs biased with current steered (through either current switch
SWN or SWP) from the primary pairs. Another scheme [9]
has similar underlying idea to that of [6]. Fig. 3(b) depicts
the circuit with a hex-pair structure. Three differential pairs
of each polarity are used. At supply rails when one of input
pairs (M1A-M2A or M3A-M4A) loses sufficient gate drive
to operate, another pair similar to the active pair is activated.
As a result, two similar pairs of same polarity generate signal
doubles to have the
current in parallel, hence the input
same
as that when both pairs are active.
The tail-current-varying constant- techniques exhibit substantial improvements over the simple circuit in Fig. 1, but still
variation
possess a serious drawback, 15 -20 systematic
(see Appendix for the proof) over the entire input common
variations of some circuits based on
mode range. The
constanttechnique I are shown in Fig. 4.
B. ConstantSelection
Technique II Maximum/Minimum Current
variation, maxiTo further reduce the input stage
techniques are
mum/minimum current selection constantused in [7], [8], [10]. The working principle of this technique
is illustrated in Fig. 5(a). When
drives the tail current
transistor out of saturation region, the tail current will decrease
significantly. The differential pair with the larger tail current
should be working properly. Fig. 5(b) describes one circuit
implementation of a maximum current selection technique [8].
In this technique, the input pair with the larger working current
is always chosen while the output of another pair is discarded.
There is another configuration of this technique which utilizes
folded-cascode circuit and minimum selection circuit to get
in a similar way [8]. The advantage of the
the maximum
latter scheme is that a wider CM range can be achieved.
The maximum/minimum current selection technique probehavior (5 in [8] and 6 in [7])
vides better constantthan technique I. As only the largest signal current is chosen,
the SR is kept constant. In addition, this technique can work
for all operation regions of input MOS transistors. However,
the transient settling behavior of this technique is imperfect
because the current selection circuit may present open loop
high impedance nodes, preventing high-speed operation.
C. Constant-
Technique III Level Shifting
A few years ago, the idea of level shifting to achieve
was reported [11]. As shown in Fig. 6(a), the
constant
transition region (i.e. the
range where its tail current
source operates in the triode) of the p-channel input differential
pair is shifted up by DC level shifters to overlap with that
of the N pair. Two P source followers are used as DC level
shifters in [11], as shown in Fig. 6(b). It has very good
behavior (
deviation) but also a major
constantlimitation: there is a need to manually tune the bias currents
of the input DC level shifters (
in Fig. 6(b)). The work
in [12] employs two automatic tuning sections to obtain the
optimum current value for the level shifter thus variations
over
range is minimized, as shown in Fig. 7(a).
In a recent work [13], unlike traditional approaches based on
complementary input pairs, the authors uses two N differential
pairs which avoids the matching requirement between N and
P pairs (Fig. 7(b)). Two identical source followers are used
in front of the input pair M1-M2. In addition, a feedforward
(FF) canceling section is designed to ensure that only one
for any
levels.
differential pair contributes to the total
This technique accomplishes all of the necessary features of
an ideal rail-to-rail input stage except that the measured
deviation exceeds .
Very small
and SR variations (within ) can be
achieved using technique III if the DC shift level is tuned
carefully. It is worth noting that circuits designed using level
shifting techniques are sensitive to and power supply
voltage variations and mismatch between N and P input pairs.
Other constant- techniques include, i) sensing and regulation of the amplifier
[14], ii) single input differential pair
with boosted for the input stage using a charge pump
[21], or tunable DC level shifters via multiple input floating
gate transistors [15], and iii) electronic zener diode regulation
[16].
D. Constantages
Techniques for Extremely Low Supply Volt-
Most previous published techniques are only valid for power
higher than
supply voltage
(see Fig. 1). For very low voltage supply (less than
2V), there is a forbidden input voltage region where neither of
the input pair is turned on, which makes it extremely difficult
input stage. Dynamic-level
to obtain a rail-to-rail constantshifting techniques was first proposed in [17] and later studied
techniques for very low supply
in [18]. Similar constantvoltages has been studied in [19], [20]. Boosting has
the potential to work with a low supply voltage, but a high
breakdown voltage is required for critical transistors in the
charge pump.
I NPUT-S TAGE A RCHITECTURE
III. N EW C ONSTANTFOR 3-V P OWER S UPPLY
In this section, we introduce a novel constant- technique.
The basic structure of the new rail-to-rail constantinput
stage is shown in Fig. 8(a). It is designed using a dynamic
current scaling technique. The output signal currents of the
input N and P channel differential pairs are scaled dynamically
, respectively. Thus
by a factor of
and
can be obtained while the tail currents of the
a constant
2572
TABLE I
S UMMARY AND COMPARISON OF CONSTANTtechnique
variation
SR variation
universality
I
15
20
2 times or constant
some (e.g. [2])
relies on
the square law
simple
fast
complexity
speed
R EFERENCES
TECHNIQUES .
II
5
7
constant
universal
III
8
9
constant
universal
new
3
constant
universal
moderate
moderate
moderate
fast
simple
fast
input transistors are unchanged. The new constantscheme
achieves
and
variation, respectively, for
input devices in strong and weak inversion operation regions.
Simulation results with transistors in strong inversion region is
given are Fig. 8(b). The advantage of the new scheme is that,
it can be applied to both short and long channel transistors,
and is compatible with deep sub-micrometer CMOS devices.
Interested readers can refer to [22] for details.
IV. C ONCLUSION
We have investigated several published constanttechniques for low-voltage rail-to-rail CMOS amplifier input
stages. The tail-current varying technique is relatively simple
variations. The maximum/minimum selection
but has large
technique has smaller
variation but lacks good transient
performance. Level shifting technique only needs additional
variation is sensitive to mismatch
source followers but its
and power supply voltage change. In Section III, we briefly
present an innovative constant- technique based on dynamic
current scaling technique. Table I provides a brief comparison
techniques discussed
of the characteristics of the constantin the previous sections. The authors cordially acknowledge
the critical comments and suggestions from the anonymous
reviewers.
V. A PPENDIX
In this appendix, we will prove that the total
of the
input stage in Fig. 2(b) has around 15 deviation over the
full input common-mode range. Refer to Fig. 2(b), if
is
between and , transistor M116 is partly
conducting, and the rest of tail current flows through M3 and
M4, which is assumed to be here. The tail current of the
. Therefore,
P input pair M1-M2 is thus
the total
of the input stage is given by
=
= . Calculate
where
maximum value of (1), we can obtain that when
reaches its maximum value, which yields
(1)
the
,
(2)
is
about
15
above
its
nominal
value
.
hence
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VDD
VDD
MBp
IP
M2p
Vi
M1n M2n
gmT, the sum of
pair active
gmN and gmP
region
Region I
Region III
M17
M16
Io+
active
VCMP
VDD
Input Common-Mode Voltage Vi,cm
M2
Vi+ M1
region
gmP
gmN
Vi
M3 M4
Io
IP (gmP)
IN (gmN)
pair active
region
Vss
VSS
VSS
(a)
Input Common-Mode Voltage Vi,cm
IN
VDD
VSS
M11
(c)
(b)
M12
M13 M14 M15
VDD
M121
M122
1.4V
(b)
Fig. 5. Rail-to-rail constantinput stage using constant[8], (a) working principle, (b) circuit example.
Vi
M1
M3
M2
M4
IN
Vi+
M2
M1
M116
M4
Vi
gmT ( after level shift )
gmN
gmP( before level shift )
gmP( after level shift )
Iref
1.4V
SW1
M113
Iref
Mb1
Mb2
M7
M9
M8
IP
Iref
M1
VSS
M10
M2
M6
M5
M114
M3 M4
Vi+
VSS
1:3
Mb3
gm
SW2
SW2
In
M124
M3
VDD
Current Summation
and Subsequent
Stages
Current Summation
and Subsequent
Stages
Vi+
technique II
Iref
SW1
IP
M23 M24 M25
VDD
1:3
Iref
M22
Maximum Selection II
(a)
M21
Maximum Selection I
Fig. 1. Conventional N-P complementary rail-to-rail input stage, (a) basic
circuit, (b)
vs input CM voltage, and (c) CM swings of N and P input
and
).
pairs (
In
M17
M16
Both pairs
VSS
IN
IP
Itail (gm)
P-channel
MBn
VDD
gmT of rail-to-rail input stage with
maximum current selection
VCMN
To the next stage
Current Summation
and Subsequent Stages
Region II
M1p
Vi+
N-channel
gm
Vi
To the
next
stage
VSS
IN
(b)
VSS
Fig. 2. Rail-to-rail constantinput stage using constant[4], (a) conceptual circuit, (b) real circuit.
Fig. 6. Rail-to-rail constantinput stage using constant[11], (a) working principle, (b) circuit example.
Iref
M10
M1B M1A
SWP
M2A
Vi+
M3B M3A
M7
Vb2
M4A
M2B
Vi
M4B
SWN
M5
Iref
M6
VSS
(a)
VDD
M2A
M1A M1B
M1C
M2C
Vi+
Vi
M3A M3B
M4B
M4A
Vi
Vi+
M1
M2
M6
M3 M4
Vi
To the
next
stage
VSS
Vis
Vis+
M1
Vis
M2
M6
M5
M3 M4
Vi+
Iref
Vi
Iref
VSS
Vis+
(b)
(a)
Fig. 7. Rail-to-rail input stages using constantexample [12], (b) circuit example [13].
M4C
M3C
Iref
Iref
M10
M5
Vi+
To the
next
stage
M9
M8
IP
IN
M2B
VDD
Mb3
Mb2
M7
Iref
Iref
Current Summation
Iref
technique III
VDD
Mb3
Mb2
Tuning for transition region
overlapping
M9
(b)
(a)
To the summation and subsequent stages
M8
DC
level
shifters
Overlapped transition regions
technique I
VDD
Vb1
VDD
Input Common-Mode Voltage Vi,cm
FF Canceling Stage
(a)
technique III, (a) circuit
Iref
VSS
(b)
Fig. 3. Rail-to-rail input stages using constantpair circuit in [6], (b) backup-pair circuit in [9].
technique I, (a) backupVDD
IP
gm
p(Vi,cm)
gmT of rail-to-rail input stage
without gm control
gm
2.4
MPA
MPB
Vi+
Vi
MNA
2.4
1-p(Vi,cm)
MNB
1-p(Vi,cm)
Vi,cm
VDD
(a)
VDD
(b)
VSS
Vi,cm
Vi,cm
VSS
IN
1.0
1.0
1.0
VSS
2.0
2.0
2.0
Current Summation
p(Vi,cm)
gmT of rail-to-rail input stage
with gm control
gm
VSS
Dynamic Current Scaling Circuit
(a)
(b)
VDD
(c)
Fig. 4. Transconductance vs. input CM voltage of rail-to-rail input stages in
(a) [4], (b) [6], and (c) [9].
Fig. 8. The new input-stage, (a) basic architecture, (b) simulation result of
vs.
characteristics of the proposed input stage .
2574
