data sheet

TPS2375
TPS2376
D8 PW8 TPS2377
www.ti.com............................................................................................................................................................ SLVS525B APRIL 2004 REVISED APRIL 2008

IEEE 802.3af PoE POWERED DEVICE CONTROLLERS

1FEATURES APPLICATIONS
Fully Supports IEEE 802.3af Specification VoIP Phones
Integrated 0.58-, 100-V, Low-Side Switch WLAN Access Points
15-kV System Level ESD Capable Security Cameras
Supports Use of Low-Cost Silicon Rectifiers Internet Appliances
POS Terminals
Programmable Inrush Current Control
Fixed 450-mA Current Limit TPS2375/77 TPS2376
(TOP VIEW) (TOP VIEW)
Fixed and Adjustable UVLO Options 1 8 1 8
ILIM VDD ILIM VDD
Open-Drain, Power-Good Reporting 2 7 2
CLASS UVLO
7
CLASS N/C
Overtemperature Protection 3
DET PG
6 3
DET PG
6
4 4
RTN 5 RTN 5
Industrial Temperature Range: -40C to 85C VSS VSS

8-Pin SOIC and TSSOP Packages

DESCRIPTION
These easy-to-use 8-pin integrated circuits contain all of the features needed to develop an IEEE 802.3af
compliant powered device (PD). The TPS2375 family is a second generation PDC (PD Controller) featuring
100-V ratings and a true open-drain, power-good function.
In addition to the basic functions of detection, classification and undervoltage lockout (UVLO), these controllers
include an adjustable inrush limiting feature. The TPS2375 has 802.3af compliant UVLO limits, the TPS2377 has
legacy UVLO limits, and the TPS2376 has a programmable UVLO with a dedicated input pin.
The TPS2375 family specifications incorporate a voltage offset of 1.5 V between its limits and the IEEE 802.3af
specifications to accommodate the required input diode bridges used to make the PD polarity insensitive.
Additional resources can be found on the TI Web site www.ti.com.
RJ45

1
TX
Data to
Detect Classify Power Up & Inrush
Pair
Ethernet
PHY
2
Class 3
Input Current
DF01S Current
2 Places
VDD

R(DET) 100
24.9 kW, kW V (PG-RTN)
SMAJ58A

1%
DET PG
CONVERTER
TO DC/DC

ILIM
TPS2375

R(ILIM)
4 0.1mF,
5
178 kW, 100 mF, VDD
100 V 1%
Spare 10 % 100 V
Pair CLASS
7 RTN VRTN
VSS

R(ICLASS)
8 357 W,
Spare
Pair 1%

3
RX
Note: Class 3 PD Depicted. Note: All Voltages With Respect to VSS.
Data to PG Pullup Resistor Is Optional.
Pair
Ethernet PHY

Figure 1. Typical Application Circuit and Startup Waveforms

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright 20042008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
 data sheet
TPS2375
TPS2376
TPS2377
SLVS525B APRIL 2004 REVISED APRIL 2008............................................................................................................................................................ www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

AVAILABLE OPTIONS
UVLO THRESHOLDS (NOMINAL) PACKAGE (1)
TA MARKING
TYPE LOW HIGH SO-8 TSSOP-8
802.3af 30.5 V 39.3 V TPS2375D TPS2375PW 2375
-40C to 85C Adjustable 1.93 V 2.49 V TPS2376D TPS2376PW 2376
Legacy 30.5 V 35.1 V TPS2377D TPS2377PW 2377

(1) Add an R suffix to the device type for tape and reel.

ABSOLUTE MAXIMUM RATINGS

(1)
over operating free-air temperature range (unless otherwise noted) , voltages are referenced to V(VSS)
TPS237x
(2)
VDD, RTN, DET, PG -0.3 V to 100 V
Voltage ILIM, UVLO -0.3 V to 10 V
CLASS -0.3 V to 12 V
(3)
RTN 0 to 515 mA
Current, sinking PG 0 to 5 mA
DET 0 to 1 mA
CLASS 0 to 50 mA
Current, sourcing
ILIM 0 to 1 mA
Human body model 2 kV
ESD Charged device model 500 V
System level (contact/air) at RJ-45 (4) 8/15 kV
TJ Maximum junction temperature range Internally limited
Tstg Storage temperature range -65C to 150C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds - Green Packages 260C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds - Nongreen Packages 235C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolutemaximumrated conditions for extended periods may affect device reliability.
(2) I(RTN) = 0
(3) SOA limited to V(RTN) = 80 V and I(RTN) = 515 mA.
(4) Surges applied to RJ-45 of Figure 1 between pins of RJ-45, and between pins and output voltage rails per EN61000-4-2, 1999.

DISSIPATION RATING TABLE (1)

POWER RATING
JA (LOW-K) JA (HIGH-K) (HIGH-K)
PACKAGE
C/W C/W TA = 85C
mW
D (SO-8) 238 150 266
PW (TSSOP-8) 258.5 159 251

(1) Tested per JEDEC JESD51. High-K is a (2 signal 2 plane) test board and low-K is a double sided
board with minimum pad area and natural convection.

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TPS2377
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RECOMMENDED OPERATING CONDITIONS

MIN MAX UNIT
VDD, PG, RTN 0 57 V
Input voltage range
UVLO 0 5 V
Operating current range (sinking) RTN 0 350 mA
Classification resistor (1) CLASS 255 4420
(1)
R(ILIM) Inrush limit program resistor 62.5 500 k
Sinking current PG 0 2 mA
TJ Operating junction temperature -40 125 C
TA Operating freeair temperature -40 85 C

(1) Voltage should not be eternally applied to CLASS and ILIM.

ELECTRICAL CHARACTERISTICS
V(VDD) = 48 V, R(DET) = 24.9 k, R(CLASS) = 255 , R(ILIM) = 178 k, and 40C TJ 125C, unless otherwise noted. Positive
currents are into pins. V(UVLO) = 0 V for classification and V(UVLO) = 5 V otherwise for the TPS2376. Typical values are at 25C.
All voltages are with respect to VSS unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DETECTION
DET open, V(VDD) = V(RTN) = 1.9 V, measure
Offset current 0.3 3 A
I(VDD) + I(RTN)
DET open, V(VDD) = V(RTN) = 10.1 V, measure
Sleep current 4 12 A
I(VDD) + I(RTN)
DET leakage current V(DET) = V(VDD) = 57 V, measure I(DET) 0.1 5 A
V(RTN) = V(VDD), V(VDD) = 1.4 V 53.7 56 58.3 A
R(DET) = 24.9 k,
Detection current
measure I(VDD) + I(RTN) + V(VDD) = 10.1 V 395 410 417 A
I(DET)
CLASSIFICATION
R(CLASS) = 4420 , 13 V(VDD) 21 V 2.2 2.4 2.8
R(CLASS) = 953 , 13 V(VDD) 21 V 10.3 10.6 11.3
I(CLASS) Classification current (1) R(CLASS) = 549 , 13 V(VDD) 21 V 17.7 18.3 19.5 mA
R(CLASS) = 357 , 13 V(VDD) 21 V 27.1 28.0 29.5
R(CLASS) = 255 , 13 V(VDD) 21 V 38.0 39.4 41.2
V(CL_ON) Classification lower threshold Regulator turns on, V(VDD) rising 10.2 11.3 13.0 V
V(CU_OFF) Regulator turns off, V(VDD) rising 21 21.9 23 V
Classification upper threshold
V(CU_H) Hysteresis 0.5 0.78 1 V
Leakage current V(CLASS) = 0 V, V(VDD) = 57 V 1 A
PASS DEVICE
rDS(on) On resistance I(RTN) = 300 mA 0.58 1.0
V(VDD) = V(RTN) = 30 V, 15
Leakage current A
V(UVLO) = 0 V (TPS2376)
Current limit V(RTN) = 1 V 405 461 515 mA
I(LIM) Inrush limit V(RTN) = 2 V, R(ILIM) = 178 k 100 130 180 mA
(2) V(RTN) falling, R(ILIM) = 178 k, inrush 85% 91% 100%
Inrush current termination
statenormal operation
R(ILIM) = 69.8 k, V(RTN-VSS) = 5 V, 15 25
Current rise time into inrush I(RTN) = 30 mA300 mA, V(VDD) increasing s
past upper UVLO
Apply load 20 , time measured to 2 2.5
Current limit response time s
I(RTN) = 45 mA
Leakage current, ILIM V(VDD) = 15 V, V(UVLO) = 0 V 1 A

(1) Classification is tested with exact resistor values. A 1% tolerance classification resistor assures compliance with IEEE 802.3af limits.
(2) This parameter specifies the RTN current value, as a percentage of the steady state inrush current, below which it must fall to make PG
assert (open-drain).

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ELECTRICAL CHARACTERISTICS (continued)

V(VDD) = 48 V, R(DET) = 24.9 k, R(CLASS) = 255 , R(ILIM) = 178 k, and 40C TJ 125C, unless otherwise noted. Positive
currents are into pins. V(UVLO) = 0 V for classification and V(UVLO) = 5 V otherwise for the TPS2376. Typical values are at 25C.
All voltages are with respect to VSS unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PG
Latchoff voltage threshold rising V(RTN) rising 9.5 10.0 10.5 V
PG deglitch Delay rising and falling PG 75 150 225 s
I(PG) = 2 mA, V(RTN) = 34 V, 0.12 0.4
V
V(VDD) = 38 V, V(RTN) falling
Output low voltage
I(PG) = 2 mA, V(RTN) = 0 V, V(VDD) = 25 V, for 0.12 0.4
V
TPS2376 V(UVLO) = 0 V
Leakage current V(PG) = 57 V, V(RTN) = 0 V 0.1 1 A
UVLO
V(UVLO_R) V(VDD) rising 38.4 39.3 40.4
V(UVLO_F) TPS2375 Voltage at VDD V(VDD) falling 29.6 30.5 31.5 V
Hysteresis 8.3 8.8 9.1
V(VDD) rising 2.43 2.49 2.57
TPS2376 Voltage at UVLO V(VDD) falling 1.87 1.93 1.98 V
Hysteresis 0.53 0.56 0.58
V(VDD) rising 34.1 35.1 36.0
TPS2377 Voltage at VDD V(VDD) falling 29.7 30.5 31.4 V
Hysteresis 4.3 4.5 4.8
TPS2376 Input leakage, UVLO V(UVLO) = 0 V to 5 V -1 1 A
THERMAL SHUTDOWN
Shutdown temperature Temperature rising 135 C
Hysteresis 20 C
BIAS CURRENT
Operating current I(VDD) 240 450 A

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TPS2377
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DEVICE INFORMATION
FUNCTIONAL BLOCK DIAGRAM
DET
3
Detection
Comparator
12 V
+
VDD
8
CLASS
Classification 10 V
Comparator 2
Regulator
22 V PG
+
PG Comparator 6
Delay
1.5 V 150 mS
& 10 V
+

R
S Q 0 = Fault
0 = Inrush
S Q
R

UVLO RTN
Comp. 5
2.5 V Thermal Shutdown,
Counter, and Latch
UVLO +
76 Only 1 = Limiting
See Current
7 Note 45 mV 1 +
Mirror EN
2.5 V 1:1
+ Current
ILIM 0 Limit Amp.
1 800 W
VSS 0.08 W
4

Note: For the TPS2376, the UVLO comparator connects to the UVLO pin and not to the UVLO divider.

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TPS2375
TPS2376
TPS2377
SLVS525B APRIL 2004 REVISED APRIL 2008............................................................................................................................................................ www.ti.com

TERMINAL FUNCTIONS
PIN NUMBER
PIN NAME I/O DESCRIPTION
TPS2375/77 TPS2376
Connect a resistor from ILIM to VSS to set the start-up inrush current limit.
ILIM 1 1 O The equation for calculating the resistor is shown in the detailed pin
description section for ILIM.
Connect a resistor from CLASS to VSS to set the classification of the
CLASS 2 2 O powered device (PD). The IEEE classification levels and corresponding
resistor values are shown in Table 1.
Connect a 24.9-k detection resistor from DET to VDD for a valid PD
DET 3 3 O
detection.
VSS 4 4 I Return line on the source side of the TPS2375 from the PSE.
Switched output side return line used as the low-side reference for the
RTN 5 5 O
TPS2375 load.
PG 6 6 O Open-drain, power-good output; active high.
Used only on the TPS2376. Connect a resistor divider from VDD to VSS to
UVLO - 7 I
implement the adjustable UVLO feature of the TPS2376.
NC 7 - No connection
VDD 8 8 I Positive line from the rectified PSE provided input.

Detailed Pin Description

The following descriptions refer to the schematic of Figure 1 and the functional block diagram.
ILIM: A resistor from this pin to VSS sets the inrush current limit per Equation 1:
I + 25000
(LIM) R
(ILIM) (1)
where ILIM is the desired inrush current value, in amperes, and R(ILIM) is the value of the programming resistor
from ILIM to VSS, in ohms. The practical limits on R(ILIM) are 62.5 k to 500 k. A value of 178 k is
recommended for compatibility with legacy PSEs.
Inrush current limiting prevents current drawn by the bulk capacitor from causing the line voltage to sag below
the lower UVLO threshold. Adjustable inrush current limiting allows the use of arbitrarily large capacitors and also
accommodates legacy systems that require low inrush currents.
The ILIM pin must not be left open or shorted to VSS.
CLASS: Classification is implemented by means of an external resistor, R(CLASS), connected between CLASS
and VSS. The controller draws current from the input line through R(CLASS) when the input voltage lies between
13 V and 21 V. The classification currents specified in the electrical characteristics table include the bias current
flowing into VDD and any RTN leakage current.

Table 1. CLASSIFICATION
CLASS PD POWER (W) R(CLASS) () 802.3af LIMITS (mA) NOTE
0 0.44 12.95 4420 1% 0-4 Default class
1 0.44 3.84 953 1% 9 - 12
2 3.84 6.49 549 1% 17 - 20
3 6.49 12.95 357 1% 26 - 30
4 - 255 1% 36 - 44 Reserved for future use

The CLASS pin must not be shorted to ground.

DET: Connect a resistor, R(DET), between DET and VDD. This resistor should equal 24.9 k, 1% for most
applications. R(DET) is connected across the input line when V(VDD) lies between 1.4 V and 11.3 V, and is
disconnected when the line voltage exceeds this range to conserve power. This voltage range has been chosen
to allow detection with two silicon rectifiers between the controller and the RJ-45 connector.
VSS: This is the input supply negative rail that serves as a local ground to the TPS2375.

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RTN: This pin provides the switched negative power rail used by the downstream circuits. The operational and
inrush current limit control current into the pin. The PG circuit monitors the RTN voltage and also uses it as the
return for the PG pin pulldown transistor. The internal MOSFET body diode clamps VSS to RTN when voltage is
present between VDD and RTN and the PoE input is not present.
PG: This pin goes to a high resistance state when the internal MOSFET that feeds the RTN pin is enabled, and
the device is not in inrush current limiting. In all other states except detection, the PG output is pulled to RTN by
the internal open-drain transistor. Performance is assured with at least 4 V between VDD and RTN.
PG is an open-drain output; therefore, it may require a pullup resistor or other interface.
UVLO: This pin is specific to the TPS2376; it is not internally connected on the TPS2375 and TPS2377. The
UVLO pin is used with an external resistor divider between VDD and VSS to set the upper and lower UVLO
thresholds. The hysteresis, as measured as a percentage of the upper UVLO, is the same as the TPS2375.
The TPS2376 enables the output when V(UVLO) exceeds the upper UVLO threshold. When current begins to flow,
VDD sags due to cable resistance and the dynamic resistance of the input diodes. The lower UVLO threshold
must be below the lowest voltage that the input reaches.
The TPS2376 implements adjustable UVLO thresholds, but is otherwise functionally equivalent to the TPS2375.
The TPS2375 offers fixed UVLO thresholds designed to maximize hysteresis while maintaining compatibility with
the IEEE 802.3af standard. The TPS2377 offers fixed UVLO thresholds optimized for use with legacy PoE
systems.
VDD: This is the positive input supply to the TPS2375, which is also common to downstream load circuits. This
pin provides operating power and allows the controller to monitor the line voltage to determine the mode of
operation.

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TYPICAL CHARACTERISTICS
Graphs over temperature are interpolations between the marked data points.

CLASSIFICATION TURNON
PD DETECTION RESISTANCE VOLTAGE
vs vs
I(VDD) + I(RTN) IN DETECTION V(PI) TEMPERATURE
6 35 11.3

Classification Turnon Voltage V

5
30
TA = 125C

Resistance k
4 11.2
Current A

25
3 TA = 25C

20
2 Specification Limits 11.1

15
1
TA = 40C
0 10 11.0
0 1 2 3 4 5 6 7 8 9 10 11 1 3 5 7 9 11 40 20 0 20 40 60 80 100 120
V(VDD) V V(PI) V TA Free-Air Temperature C

Figure 2. Figure 3. Figure 4.

CLASSIFICATION TURNOFF PASS DEVICE

VOLTAGE I(VDD) CURRENT RESISTANCE
vs vs vs
TEMPERATURE VDD TEMPERATURE
21.94 0.350 0.9
TA = 125C
Classification Turnoff Voltage V

Pass Device Resistance

0.300 0.8
21.93 TA = 25C
I (VDD) mA

0.250 TA = 40C 0.7

21.92

0.200 0.6

21.91
0.150 0.5

21.90 0.100 0.4

40 20 0 20 40 60 80 100 120 22 27 32 37 42 47 52 57 40 20 0 20 40 60 80 100 120
TA Free-Air Temperature C VDD V TA Free-Air Temperature C
Figure 5. Figure 6. Figure 7.

TPS2375 TPS2375 TPS2376

UVLO RISING UVLO FALLING UVLO RISING
vs vs vs
TEMPERATURE TEMPERATURE TEMPERATURE
39.5 30.60 2.489

30.56 2.488

39.4
V (UVLO) V
VDD V

30.52 2.487
VDD V

30.48 2.486
39.3

30.44 2.485

39.2 30.40 2.484

40 20 0 20 40 60 80 100 120 40 20 0 20 40 60 80 100 120 40 20 0 20 40 60 80 100 120
TA Free-Air Temperature C TA Free-Air Temperature C TA Free-Air Temperature C

Figure 8. Figure 9. Figure 10.

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TYPICAL CHARACTERISTICS (continued)

Graphs over temperature are interpolations between the marked data points.

TPS2376 TPS2377 TPS2377

UVLO FALLING UVLO RISING UVLO FALLING
vs vs vs
TEMPERATURE TEMPERATURE TEMPERATURE
1.929 35.20 30.65

1.928 35.15
30.60
1.927
V (UVLO) V

35.10

VDD V
VDD V
1.926 30.55

35.05
1.925
30.50
35.00
1.924

1.923 34.95 30.45

40 20 0 20 40 60 80 100 120 40 20 0 20 40 60 80 100 120 40 20 0 20 40 60 80 100 120
TA Free-Air Temperature C TA Free-Air Temperature C TA Free-Air Temperature C

Figure 11. Figure 12. Figure 13.

INRUSH STATE TERMINATION

THRESHOLD INRUSH CURRENT CURRENT LIMIT
vs vs vs
TEMPERATURE TEMPERATURE TEMPERATURE
94.0 350 440

325 75 k
93.5
Percent of Inrush Limit Current

300
93.0 275
435
I (ILIM) mA

I (RTN) mA
250
92.5
225
92.0 125 k
200
430
91.5 175

150 178 k
91.0
125
90.5 100 425
40 20 0 20 40 60 80 100 120 40 20 0 20 40 60 80 100 120 40 20 0 20 40 60 80 100 120
TA Free-Air Temperature C TA Free-Air Temperature C TA Free-Air Temperature C

Figure 14. Figure 15. Figure 16.

PG DEGLITCH PERIOD
vs
TEMPERATURE
180
PG Deglitch Period s

160

140

120
40 20 0 20 40 60 80 100 120
TA Free-Air Temperature C

Figure 17.

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TPS2376
TPS2377
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APPLICATION INFORMATION

OVERVIEW
The IEEE 802.3af specification defines a process for safely powering a PD over a cable, and then removing
power if a PD is disconnected. The process proceeds through three operational states: detection, classification,
and operation. The intent behind the process is to leave an unterminated cable unpowered while the PSE
periodically checks for a plugged-in device; this is referred to as detection. The low power levels used during
detection are unlikely to cause damage to devices not designed for PoE. If a valid PD signature is present, then
the PSE may optionally inquire how much power the PD requires; this is referred to as classification. The PD
may return a default full-power signature, or one of four other choices. Knowing the power demand of each PD
allows the PSE to intelligently allocate power between PDs, and also to protect itself against overload. The PSE
powers up a valid PD, and then monitors its output for overloads. The maintain power signature (MPS) is
presented by the powered PD to assure the PSE that it is there. The PSE monitors its output for the MPS to see
if the PD is removed, and turns the port off, if it loses the MPS. Loss of MPS returns the PSE to the initial state of
detection. Figure 18 shows the operational states as a function of PD input voltage range.
The PD input is typically an RJ-45 (8-pin) connector, referred to as the power interface (PI). PD input
requirements differ from PSE output requirements to account for voltage drops in the cable and margin. The
specification uses a cable resistance of 20 to derive the voltage limits at the PD from the PSE output
requirements. Although the standard specifies an output power of 15.4 W at the PSE output, there is only
12.95 W available at the input of the PD due to the worst case power loss in the cable.
The PSE can apply voltage either between the RX and TX pairs, or between the two spare pairs as shown in
Figure 1. The applied voltage can be of either polarity. The PSE cannot apply voltage to both paths at the same
time. The PD uses input diode bridges to accept power from any of the possible PSE configurations. The voltage
drops associated with the input bridges cause a difference between the IEEE 802.3af limits at the PI and the
TPS2375 specifications.
The PSE is required to current limit between 350 mA and 400 mA during normal operation, and it must
disconnect the PD if it draws this current for more than 75 ms. The PSE may set lower output current limits
based on the PD advertised power requirements, as discussed below.
The following discussion is intended as an aid in understanding the operation of the TPS2375, but not as a
substitute for the actual IEEE 802.3af standard. Standards change and should always be referenced when
making design decisions.
Must Turn Off by

Must Turn On by
Proper Operation

Maximum Input
Voltage Falling

Voltage Rising
Classification

Classification

Lower Limit
Lower Limit

Upper Limit
Lower Limit

Upper Limit
Detection

Detection

Voltage

Shut -
Detect Classify Normal Operation
down

0 2.7 10.1 14.5 20.5 30 36 42 57

PI Voltage (V)

Figure 18. IEEE 802.3 PD Limits

INTERNAL THRESHOLDS
In order to implement the PoE functionality as shown in Figure 18, the TPS2375 has a number of internal
comparators with hysteresis for stable switching between the various states. Figure 19 relates the parameters in
the Electrical Characteristics section to the PoE states. The mode labeled idle between classification and
detection implies that the DET, CLASS, PG, and RTN pins are all high impedance.

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Operational Mode
PD Powered
Idle

Classification

Detection
V(VDD)
V(CU_H)
V(UVLO_F) V(UVLO_R)
1.4V V(CL_ON) V(CU_OFF)

Figure 19. Threshold Voltages

DETECTION
This feature of IEEE 802.3af eliminates powering and potentially damaging Ethernet devices not intended for
application of 48 V. When a voltage in the range of 2.7 V to 10.1 V is applied to the PI, an incremental resistance
of 25 k signals the PSE that the PD is capable of accepting power. A PD that is capable of accepting power,
but is not ready, may present an incorrect signature intentionally. The incremental resistance is measured by
applying two different voltages to the PI and measuring the current it draws. These two test voltages must be
within the specified range and be at least 1 V apart. The incremental resistance equals the difference between
the voltages divided by the difference between the currents. The allowed range of resistance is 23.75 k to
26.25 k.
The TPS2375 is in detection mode whenever the supply voltage is below the lower classification threshold. The
TPS2375 draws a minimum of bias power in this condition, while PG and RTN are high impedance and the
circuits associated with ILIM and CLASS are disabled. The DET pin is pulled to ground during detection. Current
flowing through R(DET) to VSS (Figure 1) produces the detection signature. For most applications, a 24.9-k, 1%,
resistor is recommended. R(DET) can be a small, low-power resistor because it only sees a stress of about 5 mW.
When the input voltage rises above the 11.3 V lower classification comparator threshold, the DET pin goes to an
open-drain condition to conserve power.
The input diode bridge incremental resistance can be hundreds of ohms at the low currents seen at 2.7 V on the
PI. The bridge resistance is in series with R(DET) and increases the total resistance seen by the PSE. This varys
with the type of diode selected by the designer, and it is not usually specified on the diode data sheet. The value
of R(DET) may be adjusted downwards to accommodate a particular diode type.

CLASSIFICATION
Once the PSE has detected a PD, it may optionally classify the PD. This process allows a PSE to determine the
PD power requirements in order to allot only as much power as necessary from its fixed input power source. This
allows the PSE to power the maximum number of PDs from a particular power budget. This step is optional
because some PSEs can afford to allot the full power to every powered port.
The classification process applies a voltage between 14.5 V and 20.5 V to the input of the PD, which in turn
draws a fixed current set by R(CLASS). The PSE measures the PD current to determine which of the five available
classes (Table 1) that the PD is signalling. The total current drawn from the PSE during classification is the sum
of bias currents and current through R(CLASS). The TPS2375 disconnects R(CLASS) at voltages above the
classification range to avoid excessive power dissipation (Figure 18 and Figure 19).
The value of R(CLASS) should be chosen from the values listed in Table 1 based on the average power
requirements of the PD. The power rating of this resistor should be chosen so that it is not overstressed for the
required 75-ms classification period, during which 10 V is applied. The PD could be in classification for extended
periods during bench test conditions, or if an auxiliary power source with voltage within the classification range is
connected to the PD front end. Thermal protection may activate and turn classification off if it continues for more
than 75 ms, but the design must not rely on this function to protect the resistor.

Copyright 20042008, Texas Instruments Incorporated Submit Documentation Feedback 11

Product Folder Link(s): TPS2375 TPS2376 TPS2377
 data sheet
TPS2375
TPS2376
TPS2377
SLVS525B APRIL 2004 REVISED APRIL 2008............................................................................................................................................................ www.ti.com

UNDERVOLTAGE LOCKOUT (UVLO)

The TPS2375 incorporates an undervoltage lockout (UVLO) circuit that monitors line voltage to determine when
to apply power to the downstream load and allow the PD to power up. The IEEE 802.3af specification dictates a
maximum PD turnon voltage of 42 V and a minimum turnoff voltage of 30 V (Figure 19). The IEEE 802.3af
standard assumes an 8-V drop in the cabling based on a 20- feed resistance and a 400-mA maximum inrush
limit. Because the minimum PSE output voltage is 44 V, the PD must continue to operate properly with input
voltages as low as 36 V. The TPS2375 UVLO limits are designed to meet the turnon, turnoff, and hysteresis
requirements.
Various legacy PSE systems in the field do not meet the minimum output voltage of 44 V. The TPS2377 UVLO
limits are designed to support these systems with a lower turnon voltage and smaller hysteresis. Although the
TPS2377 works with compliant PSEs, it could potentially exhibit startup instabilities if the PSE output voltage
rises slowly. The TPS2375 is recommended for applications with compliant PSEs.
In order to provide flexibility for noncompliant designs, the TPS2376 allows the designer to program the turnon
thresholds with a resistor divider. The hysteresis of the TPS2376, measured as a percentage of the turnon
voltage, is similar to that of the TPS2375. To use the TPS2376, connect a resistor divider between VDD and
VSS with the tap connected to the UVLO pin. The total divider resistance appears in parallel with the R(DET), and
the combination of the two should equal 24.9 k. The divider ratio should be chosen to obtain 2.5 V at the UVLO
pin when V(VDD) is at the desired turnon voltage.
The TPS2375 uses the UVLO function to control the load through an onboard MOSFET switch. Figure 19
graphically shows the relationships of the UVLO thresholds defined in the Electrical Characteristics section to the
TPS2375 operational states.

PROGRAMMABLE INRUSH CURRENT LIMIT AND FIXED OPERATIONAL CURRENT LIMIT

Inrush limiting is beneficial for a number of reasons. First, it provides a mechanism to keep the inrush current
below the 400 mA, 50 ms, maximum inrush allowed by the standard. Second, by reducing the level of the current
limit below the PSE operational limit, which can be as low as the classification power divided by the PSE voltage,
it allows an arbitrarily large bulk capacitor to be charged. Third, some legacy PSEs may not tolerate large inrush
currents while powering their outputs up.
The TPS2375 operational current limit protects the internal power switch from instantaneous output faults and
current surges. The minimum operational current limit level of 405 mA is above the maximum PSE output current
limit of 400 mA. This current limit allows the PD to draw the maximum available power and also allows the PSE
to detect fault conditions.
The TPS2375 incorporates a state machine that controls the inrush and operational current limit states. When
V(VDD) is below the lower UVLO threshold, the current limit state machine is reset. In this condition, the RTN pin
is high impedance, and at V(VDD) once the output capacitor is discharged by the downstream circuits. When
V(VDD) rises above the UVLO turnon threshold, the TPS2375 enables the internal power MOSFET with the
current limit set to the programmed inrush value. The load capacitor charges and the RTN pin voltage falls from
V(VDD) to nearly V(VSS). Once the inrush current falls about 10% below the programmed limit, the current limit
switches to the internal 450-mA operational level after a 150-s delay. This switchover can be seen in the
operation of PG, which goes active (open drain) after inrush terminates as seen in Figure 1. The internal power
MOSFET is disabled if the input voltage drops below the lower UVLO threshold.
When in the operating current-limit state, a fault on the output or a large input transient can cause the internal
MOSFET to limit current. The RTN voltage rises above its normal operating level of less than 0.5 V while in
current-limit state. If V(RTN) rises above 10 V for more than 150 s, the MOSFET is latched off. The PD input
voltage must drop below the lower UVLO threshold to clear this latch. If the RTN voltage does not exceed 10 V
while in current-limit state, but the condition persists long enough to overheat the TPS2375, the thermal limit
circuit activates, as described in the thermal protection section.
Practical values of R(ILIM) lie between 62.5 k and 500 k. The pin must not be left open. An inrush level of
140 mA, set by an R(ILIM) of 178 k, should be used with TPS2377 applications for compatibility with legacy
systems. This same inrush current level suffices for many TPS2375 applications.
The inrush limit, the bulk capacitor size, and the downstream dc/dc converter startup method must be chosen so
that the converter input current does not exceed the inrush current limit while it is active. This can be achieved by
using the PG output to enable the downstream converter after inrush finishes, by delaying the converter startup
until inrush finishes, or by increasing the value of the inrush current limit.
12 Submit Documentation Feedback Copyright 20042008, Texas Instruments Incorporated

Product Folder Link(s): TPS2375 TPS2376 TPS2377

 data sheet
TPS2375
TPS2376
TPS2377
www.ti.com............................................................................................................................................................ SLVS525B APRIL 2004 REVISED APRIL 2008

MAINTAIN POWER SIGNATURE

Once a valid PD has been detected and powered, the PSE uses the maintain power signature (MPS) to
determine when to remove power from the PI. The PSE removes power from that output port if it detects loss of
MPS for 300 ms or more. A valid MPS requires the PD to draw at least 10 mA and also have an ac impedance
less than 26.25 k in parallel with 0.05 F. TI's reference designs meet the requirements necessary to maintain
power.

POWER GOOD
The TPS2375 includes a power-good circuit that can be used to signal the PD circuitry that the load capacitor is
fully charged. This pin is intended for use as an enable signal for downstream circuitry. If the converter tries to
start up while inrush is active, and draws a current equal to the inrush limit, a latchup condition occurs in which
the PD never successfully starts. Using the PG pin is the safest way to assure that there are no undesired
interactions between the inrush limit, the converter startup characteristic, and the size of the bulk capacitor.
The PG pin goes to an open-drain state approximately 150 s after the inrush current falls 10% below the
regulated value. PG pulldown current is only assured when the voltage difference between VDD and RTN
exceeds 4 V. This is not a limiting factor because the dc/dc converter should not be able to run from 4 V. The PG
output is pulled to RTN whenever the MOSFET is disabled or is in inrush current limiting.
Referencing PG to RTN simplifies the interface to the downstream dc/dc converter or other circuit because it is
referenced to RTN, not VSS. Care must be used in interfacing the PG pin to the downstream circuits. The pullup
to VDD shown in Figure 1 may not be appropriate for a particular dc/dc converter interface. The PG pin connects
to an internal open-drain, 100-V transistor capable of sinking 2 mA to a voltage below 0.4 V. The PG pin can be
left open if it is not used.

THERMAL PROTECTION
The controller may overheat after operation in current-limit state or classification for an extended period of time,
or if the ambient temperature becomes excessive. The TPS2375 protects itself by disabling the RTN and CLASS
pins when the internal die temperature reaches about 140C. It automatically restarts when the die temperature
has fallen approximately 20C. If this cycle occurs eight times, then the device latches off until the supply voltage
drops below the lower classification threshold. This feature prevents the part from operating indefinitely in fault,
and ensures that the PSE recognizes the fault condition when using dc MPS. Thermal protection is active
whenever the TPS2375 is not in detection.
Figure 20 shows how the TPS2375 responds when it is enabled into a short. The TPS2375 starts in the inrush
current-limit state when the input voltage exceeds the upper UVLO limit. A power dissipation of over 5 W heats
the die from 25C to 140C in approximately 400 ms. The TPS2375 then shuts down until the die temperature
drops to about 120C, which occurs in about 20 ms. This process repeats eight times before the TPS2375
latches off. The PG pin is high because RTN is tied to VDD.
V(PI) = 44 V, R(ILIM) = 178 kW

Ch1: VDD @ 50 V/div

CH2: RTN @ 50 V/div

CH3: V(PG) @ 50 V/div

Iin @ 100 mA/div

Figure 20. TPS2375 Started Into Short

Copyright 20042008, Texas Instruments Incorporated Submit Documentation Feedback 13

Product Folder Link(s): TPS2375 TPS2376 TPS2377
 data sheet
TPS2375
TPS2376
TPS2377
SLVS525B APRIL 2004 REVISED APRIL 2008............................................................................................................................................................ www.ti.com

POWER SYSTEM DESIGN

The PSE is a power and current limited source, which imposes certain constraints on the PD power supply
design. DC/DC converters have both a constant input power characteristic that causes them to draw high
currents at low voltage, and they tend to go to a full input power mode during start-up that is often 25% or more
above their rated power. Improper design of the power system can cause the PD to not start up with all
combinations of Ethernet lines and PSE sources.
The following guidelines should be used:
1. Set the TPS2375 inrush to a moderate value as previously discussed.
2. Hold the dc/dc converter off during inrush as previously discussed.
3. The converter should have a softstart that keeps the peak input start-up current below 400 mA, and
preferably only a modest amount over the operating current, with a 44-V PSE source and a 20- loop.
4. If step 3 cannot be met, the bulk input capacitor should not discharge more than 8 V during converter start
up from a 400-mA limited, 44-V source with a 20- line. Start-up must be completed in less than 50 mS
Step 4 requires a balance between the converter output capacitance, load, and input bulk capacitance. While
there are some cases which may not require all these measures, such as a 1-W PD with minimal converter
output capacitance, it is always a good practice to follow them.

AUXILIARY POWER SOURCE ORING

Many PoE capable devices are designed to operate from either a wall adapter or PoE power. A local power
solution adds cost and complexity, but allows a product to be used regardless of PoE availability. Attempting to
create solutions where the two power sources coexist in a specific controlled manner results in additional
complexity, and is not generally recommended. Figure 21 demonstrates three methods of diode ORing external
power into a PD. Option 1 inserts power on the output side of the PoE power conversion. Option 2 inserts power
on the TPS2375 output. Option 3 applies power to the TPS2375 input. Each of these options has advantages
and disadvantages. The wall adapter must meet a minimum 1500-Vac dielectric withstand test voltage to the ac
input power and to ground for options 2 and 3.

Inserting a Diode in This Location

With Option 2, Allows PoE To Start
With Aux Power Present.

~ +

~
VDD

Main
RJ45

R (DET) DC/DC
22 F DC/DC
Converter
DET Converter
Output
0.1 F

TPS237X

UCC3809
ILIM or
SMAJ58A

R(ILIM)
~ + UCC3813
CLASS
~ RTN
VSS

Option 3 R (CLASS)
For Option 2,
The Capacitor Must Be
Auxiliary Option 2 Right At The Output
Power To Control The
Input Transients.
Use only Option 1 Optional
one option
Regulator

A Full Wave Bridge See TI Document SLVR030 For A Typical

Gives Flexibility To Application Circuit.
Use Supply With Either
Polarity

Figure 21. Auxiliary Power ORing

14 Submit Documentation Feedback Copyright 20042008, Texas Instruments Incorporated

Product Folder Link(s): TPS2375 TPS2376 TPS2377

 data sheet
TPS2375
TPS2376
TPS2377
www.ti.com............................................................................................................................................................ SLVS525B APRIL 2004 REVISED APRIL 2008

Option 1 consists of ORing power to the output of the PoE dc/dc converter. This option is preferred in cases
where PoE is added to an existing design that uses a low-voltage wall adapter. The relatively large PD
capacitance reduces the potential for harmful transients when the adapter is plugged in. The wall adapter output
may be grounded if the PD incorporates an isolated converter. This solution requires two separate regulators, but
low-voltage adapters are readily available. The PoE power can be given priority by setting its output voltage
above that from the auxiliary source.
Option 2 has the benefits that the adapter voltage may be lower than the TPS2375 UVLO, and that the bulk
capacitor shown can control voltage transients caused by plugging an adapter in. The capacitor size and location
are chosen to control the amount of ringing that can occur on this node, which can be affected by additional
filtering components specific to a dc/dc converter design. The optional diode blocks the adapter voltage from
reverse biasing the input, and allows a PoE source to apply power provided that the PSE output voltage is
greater than the adapter voltage. The penalty of the diode is an additional power loss when running from PSE
power. The PSE may not be able to detect and start powering without the diode. This means that the adapter
may continue to power the PD until removed. Auxiliary voltage sources can be selected to be above or below the
PoE operational voltage range. If automatic PoE precedence is desired when using the low-voltage auxiliary
source option, make sure that the TPS2375 inrush program limit is set higher than the maximum converter input
current at its lowest operating voltage. It is difficult to use PG with the low-voltage auxiliary source because the
converter must operate during a condition when the TPS2375 would normally disable it. Circuits may be
designed to force operation from one source or the other depending on the desired operation and the auxiliary
source voltage chosen. However, they are not recommended because they increase complexity and thus cost.
Option 3 inserts the power before the TPS2375. It is necessary for the adapter to meet the TPS2375 UVLO
turnon requirement and to limit the maximum voltage to 57 V. This option provides a valid power-good signal and
simplifies power priority issues. The disadvantage of this method is that it is the most likely to cause transient
voltage problems. Plugging a powered adapter in applies a step input voltage to a node that has little
capacitance to control the dv/dt and voltage ringing. If the wall mount supply applies power to the PD before the
PSE, it prevents the PSE from detecting the PD. If the PSE is already powering the PD when the auxiliary source
is plugged in, priority is given to the higher supply voltage.

ESD
The TPS2375 has been tested using the surge of EN61000-4-2 in an evaluation module (EVM) using the circuit
in Figure 1. The levels used were 8-kV contact discharge and 15-kV air discharge. Surges were applied between
the RJ-45 and the dc EVM outputs, and between an auxiliary power input jack and the dc outputs. No failures
were observed.
ESD requirements for a unit that incorporates the TPS2375 have much broader scope and operational
implications than those used in TIs testing. Unit level requirements should not be confused with EVM testing that
only validated the TPS2375.

EXTERNAL COMPONENTS

Transformer
Nodes on an Ethernet network commonly interface to the outside world via an isolation transformer per IEEE
802.3 requirements, see Figure 1. For powered devices, the isolation transformer must include a center tap on
the media (cable) side. Proper termination is required around the transformer to provide correct impedance
matching and to avoid radiated and conducted emissions. Transformers must be specifically rated to work with
the Ethernet chipset, and the IEEE 802.3af standard.

Input Diodes or Diode Bridges

The IEEE 802.3af requires the PD to accept power on either set of input pairs in either polarity. This requirement
is satisfied by using two full-wave input bridge rectifiers as shown in Figure 1. Silicon p-n diodes with a 1-A or
1.5-A rating and a minimum breakdown of 100 V are recommended. Diodes exhibit large dynamic resistance
under low-current operating conditions such as in detection. The diodes should be tested for their behavior under
this condition. The diode forward drops must be less than 1.5 V at 500 A and at the lowest operating
temperature.

Copyright 20042008, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Link(s): TPS2375 TPS2376 TPS2377
 data sheet
TPS2375
TPS2376
TPS2377
SLVS525B APRIL 2004 REVISED APRIL 2008............................................................................................................................................................ www.ti.com

Input Capacitor
The IEEE 802.3af requires a PD input capacitance between 0.05 F and 0.12 F during detection. This capacitor
should be located directly adjacent to the TPS2375 as shown in Figure 1. A 100-V, 10%, X7R ceramic capacitor
meets the specification over a wide temperature range.

Load Capacitor
The IEEE 802.3af specification requires that the PD maintain a minimum load capacitance of 5 F. It is
permissible to have a much larger load capacitor, and the TPS2375 can charge in excess of 470 F before
thermal issues become a problem. However, if the load capacitor is too large, the PD design may violate IEEE
802.3af requirements.
If the load capacitor is too large, there can be a problem with inadvertent power shutdown by the PSE caused by
failure to meet the MPS. This is caused by having a long input current dropout due to a drop in input voltage with
a large capacitance-to-load ratio. The standard gives Equation 2:
I 180
(PD)
C v
10 mA (2)
where C is the bulk capacitance in F and I(PD) is the PD load current in mA.
A particular design may have a tendency to cause ringing at the RTN pin during startup, inadvertent hot-plugs of
the PoE input, or plugging in a wall adapter. It is recommended that a minimum value of 1 F be used at the
output of the TPS2375 if downstream filtering prevents placing the larger bulk capacitor right on the output. When
using ORing option 2, it is recommended that a large capacitor such as a 22 F be placed across the TPS2375
output.

Transient Suppressor
Voltage transients on the TPS2375 can be caused by connecting or disconnecting the PD, or by other
environmental conditions like ESD. The TPS2375 is specified to operate with absolute maximum voltages
V(VDD-VSS) and V(RTN-VSS) of 100 V. A transient voltage suppressor, such as the SMAJ58A, should be installed
after the bridge and across the TPS2375 input as shown in Figure 1. Various configurations of output filters and
the insertion of local power sources across either the TPS2375 input or output have the potential to cause
stresses outside the absolute maximum ratings of the device. Designers should be aware of this possibility and
account for it in their circuit designs. For example, use adequate capacitance across the output to limit the
magnitude of voltage ringing caused by downstream filters. Plugging an external power source across the output
may cause ESD-like events. Some form of protection should be considered based on a study of the specific
waveforms seen in an application circuit.

Layout
The layout of the PoE front end must use good practices for power and EMI/ESD. A basic set of
recommendations include:
1. The parts placement must be driven by the power flow in a point-to-point manner such as RJ-45 Ethernet
transformer diode bridges TVS and 0.1-F capacitor TPS2375 output capacitor.
2. There should not be any crossovers of signals from one part of the flow to another.
3. All leads should be as short as possible with wide power traces and paired signal and return.
4. Spacing consistent with safety standards like IEC60950 must be observed between the 48-V input voltage
rails and between the input and an isolated converter output.
5. The TPS2375 should be over a local ground plane or fill area referenced to VSS to aid high-speed operation.
6. Large SMT component pads should be used on power dissipating devices such as the diodes and the
TPS2375.
Use of added copper on local power and ground to help the PCB spread and dissipate the heat is recommended.
Pin 4 of the TPS2375 has the lowest thermal resistance to the die.

16 Submit Documentation Feedback Copyright 20042008, Texas Instruments Incorporated

Product Folder Link(s): TPS2375 TPS2376 TPS2377

 PACKAGE OPTION ADDENDUM

www.ti.com 10-Jun-2014

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

TPS2375D ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 2375

& no Sb/Br)
TPS2375DG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 2375
& no Sb/Br)
TPS2375DR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 2375
& no Sb/Br)
TPS2375DRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 2375
& no Sb/Br)
TPS2375PW ACTIVE TSSOP PW 8 150 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 2375
& no Sb/Br)
TPS2375PWG4 ACTIVE TSSOP PW 8 150 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 2375
& no Sb/Br)
TPS2375PWR ACTIVE TSSOP PW 8 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 2375
& no Sb/Br)
TPS2375PWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 2375
& no Sb/Br)
TPS2376D ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 2376
& no Sb/Br)
TPS2376DG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 2376
& no Sb/Br)
TPS2376DR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 2376
& no Sb/Br)
TPS2376DRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 2376
& no Sb/Br)
TPS2376PW ACTIVE TSSOP PW 8 150 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 2376
& no Sb/Br)
TPS2376PWG4 ACTIVE TSSOP PW 8 150 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 2376
& no Sb/Br)
TPS2376PWR ACTIVE TSSOP PW 8 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 2376
& no Sb/Br)
TPS2376PWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 2376
& no Sb/Br)
TPS2377D ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 2377
& no Sb/Br)

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Jun-2014

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

TPS2377DG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 2377

& no Sb/Br)
TPS2377DR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 2377
& no Sb/Br)
TPS2377DRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 2377
& no Sb/Br)
TPS2377PW ACTIVE TSSOP PW 8 150 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 2377
& no Sb/Br)
TPS2377PWR ACTIVE TSSOP PW 8 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 2377
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Jun-2014

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 13-Feb-2016

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS2375DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2375PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TPS2376DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2376PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TPS2377DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2377PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 13-Feb-2016

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2375DR SOIC D 8 2500 340.5 338.1 20.6
TPS2375PWR TSSOP PW 8 2000 367.0 367.0 35.0
TPS2376DR SOIC D 8 2500 367.0 367.0 38.0
TPS2376PWR TSSOP PW 8 2000 367.0 367.0 35.0
TPS2377DR SOIC D 8 2500 367.0 367.0 38.0
TPS2377PWR TSSOP PW 8 2000 367.0 367.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
PW0008A SCALE 2.800
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

C
6.6 SEATING PLANE
TYP
6.2

A PIN 1 ID 0.1 C
AREA
6X 0.65
8
1

3.1 2X
2.9
NOTE 3 1.95

4
5
0.30
8X
0.19
4.5 1.2 MAX
B 0.1 C A B
4.3
NOTE 4

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE

0.75 0.15
0 -8 0.05
0.50

DETAIL A
TYPICAL

4221848/A 02/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
PW0008A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

8X (1.5)
8X (0.45) SYMM
(R0.05)
1 TYP
8

SYMM

6X (0.65)
5
4

(5.8)

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4221848/A 02/2015
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PW0008A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

8X (1.5)
SYMM (R0.05) TYP
8X (0.45)
1
8

SYMM

6X (0.65)
5
4

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:10X

4221848/A 02/2015
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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