This repo contains a collection of Verilog+System Verilog+RTL+UVM+Protocols Projects

Chez Scheme

An open-source static random access memory (SRAM) compiler.

Semiconductor device modeling and simulation in Synopsys Sentaurus TCAD Tool

the MiKTeX source code

PicoRV32 - A Size-Optimized RISC-V CPU

RISC-V CPU for OpenFPGAs, in Icestudio

Semiconductor Packaging Fundamentals

Implementation of 8-Bit CPU based on Von-Neumann Architechture in HDL

SystemVerilog frontend for Yosys

Verilog to Routing -- Open Source CAD Flow for FPGA Research

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using…

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

An open source GPU based off of the AMD Southern Islands ISA.

A minimal GPU design in Verilog to learn how GPUs work from the ground up

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).

UVM Book Examples - A Practical Guide to Adopting the Universal Verification Methodology (UVM) Second Edition

Blender GDSII Importer with PDK Support

Python Productivity for ZYNQ

Quantum simulator of qudits

Yosys Open SYnthesis Suite

An Open-source FPGA IP Generator

Linux Commands and examples

This is the main repository for all the examples for the book Practical UVM