Claude Code skills for JITX hardware design automation. These skills help Claude work effectively with JITX Python projects for PCB design, circuit creation, and component modeling.

Inside Claude Code, run these slash commands:

/plugin marketplace add JITx-Inc/jitx-skills
/plugin install jitx-skills@jitx

To pull the latest version of the plugin:

/plugin marketplace update jitx
claude plugin update jitx-skills@jitx

The first command refreshes the marketplace listing from the GitHub repository. The second command updates the installed plugin to the latest version. Restart Claude Code after updating to load the new version.

By default, auto-update is disabled for third-party marketplaces. To enable it:

1. Run /plugin to open the interactive plugin manager
2. Select the Marketplaces tab
3. Choose jitx
4. Select Enable auto-update

When enabled, Claude Code checks for updates at startup and notifies you to restart if updates were applied.

claude plugin uninstall jitx-skills@jitx

Base workflow skill for JITX projects. Triggers on any JITX-related task and provides:

• Automatic environment setup (venv creation, dependency installation)
• Build commands for designs
• Project structure guidance
• Navigation to specialized subskills

Example triggers:

• "Build my JITX design"
• "Set up JITX environment"
• "Create a circuit for..."

Generate JITX Python component code from datasheets. Supports:

• Package types: BGA, QFN, SOIC, SON, SOT
• Features: Multi-unit symbols, thermal pads, complex pin mappings
• Batch creation: Organized component folder structure

Example triggers:

• "Create a JITX component from this datasheet"
• "Model the RP2040 for my project"
• "Add an LDO component from the TI datasheet"

Build JITX circuits with wiring, passives, providers, and geometry. Covers:

• Circuit class: Net wiring, passive insertion, component instantiation
• Provider/require: Pin assignment patterns for flexible designs
• Geometry: Pours, copper shapes, placement
• Solvers: Voltage divider, query refinement

Example triggers:

• "Wire up a buck converter circuit"
• "Connect the MCU to sensors over I2C"
• "Add decoupling caps to all power pins"

Model JITX substrates — stackups, materials, vias, routing structures, and fabrication constraints. Covers:

• Stackups: Symmetric and explicit layer definitions, material properties
• Vias: All types — through-hole, laser micro, stacked, blind, buried, backdrilled
• Routing structures: Single-ended and differential with NeckDown, via fencing, geometry, reference planes
• Fabrication constraints: Manufacturing rules for any fab house
• Design rules: Tag-based rules — clearance, trace width, via stitching/fencing, thermal relief, pour feature size, routing structures

Example triggers:

• "Create a 4-layer JLCPCB substrate"
• "Define a 14-layer RF stackup with via fencing"
• "Set up 100-ohm differential routing structure"
• "Add laser microvias to the substrate"

Author PCB physical layout from code — the layer between schematic wiring and stackup definition. Covers:

• Copper: Copper vs OverlappableCopper vs Pour (antennas, filters, net-ties)
• Custom shapes: shapely CSG feeding any feature (copper, keepouts, board outline, pads)
• Pad features: Soldermask/paste openings, thermal pads with vias
• Placement: Explicit placement; net-membership vias for stitching, PortAttachment for signal topologies (control points, escape vias)
• Layout-intent tags: Fanout/escape, direct-connect selection for design rules
• Code-based routing: Route + control points (RoutePoint, PairInsertion, PairPoint) for escape lanes and deskew

Example triggers:

• "Draw an IFA antenna from code"
• "Create a net tie between AGND and DGND"
• "Route the BGA escape lanes from code"

Apply signal integrity constraints to JITX designs. Covers:

• Topology: >> operator for SI-aware signal routing vs + for nets
• Constraints: Insertion loss, timing, routing structure assignment
• Differential pairs: ConstrainDiffPair, DiffPairConstraint reusable helper
• Bus matching: ConstrainReferenceDifference for clock-to-data skew
• Pin models: TerminatingPinModel, BridgingPinModel for SI analysis
• Protocols: PCIe, SATA, SFP, Ethernet, RGMII, DDR4, LPDDR4/5, GDDR7

Example triggers:

• "Constrain this differential pair with 5ps skew"
• "Add insertion loss limits to the data bus"
• "Match data signals to the clock within 20ps"
• "Set up PCIe Gen4 constraints"

Flexible pin mapping with provide/require patterns. Covers:

• Decorators: @provide.one_of / @provide.subset_of, programmatic Provide
• Pin muxing: MCU peripherals on shared pins, FPGA bank assignment
• Protocol flexibility: DiffPair P/N swapping, PCIe lane ordering, DDR byte/bit swapping
• Composition: Hierarchical providers, topology and SI constraints on assigned ports

Example triggers:

• "Let the tool pick which UART maps to these pins"
• "Allow P/N swap on the LVDS pairs"
• "Set up DDR4 byte swapping"

Same-model self-critique pass on JITX Python code just written in the current workspace. Catches the architectural failure modes that grep gates and static linters miss — parallel string-keyed models, sibling-attribute reflection, substrate-shaped tables duplicated in designs, build-spec-then-iterate, name-construction at module-import time. Produces severity-tagged findings (CRITICAL / WARNING / NOTE) that fold into the task acceptance block.

• Mandatory for complete-board tier (folds into the Think Twice step at task acceptance, before codex outside-voice).
• User-invoked for single-task work.

Example triggers:

• "Review my JITX code"
• "Check this for string-hacking"
• "Self-critique what I just wrote"
• "Audit before merge"

Mechanical CAD interface for JITX designs. Covers:

• Import: DXF, EMN, IDF, IDX, BDF via jitx-mechanical inspect / import (board outline, keepouts, holes with --hole-policy)
• Export: JITX board XML to DXF via jitx-mechanical export-dxf
• 3D: Attach STEP models with jitx.model3d.Model3D; export board STEP

Example triggers:

• "Import this EMN as the board outline"
• "Export my board to DXF for the ME team"
• "Attach a STEP model to this connector"

jitx-skills/
├── jitx/                      # Base JITX workflow skill
│   ├── SKILL.md
│   └── references/
│       └── docs-index.md      # JITX documentation URL index
├── jitx-component-modeler/    # Component generation skill
│   ├── SKILL.md
│   ├── references/
│   │   └── package-examples.md  # Package-specific code examples
│   └── scripts/
│       └── extract_pages.py   # PDF extraction utility
├── jitx-circuit-builder/      # Circuit building skill
│   ├── SKILL.md
│   └── references/
│       └── advanced-patterns.md  # Provider, pour, placement patterns
├── jitx-substrate-modeler/    # Substrate modeling skill
│   └── SKILL.md
├── jitx-physical-layout/      # Layout-from-code skill
│   ├── SKILL.md
│   └── references/
│       ├── control-points.md    # Route / control-point API (4.2)
│       └── layout-examples.md   # Worked thermal-pad / antenna examples
├── jitx-interconnect-constraints/  # SI constraints skill
│   ├── SKILL.md
│   └── references/
│       └── protocol-standards.md  # Protocol timing parameters
├── jitx-pin-assignment/       # Provide/require pin-mapping skill
│   ├── SKILL.md
│   └── references/
│       └── protocol-pin-flexibility.md  # Per-protocol swap rules
├── jitx-code-review/             # Same-model self-critique skill
│   ├── SKILL.md
│   └── references/
│       └── checklist.md            # Pattern index over the architecture doctrine
├── jitx-mechanical/           # Mechanical CAD import/export skill
│   └── SKILL.md
└── .claude-plugin/
    └── marketplace.json

• A JITX Python project (with pyproject.toml containing jitx dependency)
• Python 3.12+
• For datasheet processing: pip install pymupdf

User: Create a JITX component for the NE555 timer from this datasheet
Claude: [Uses jitx-component-modeler skill to generate component code]

User: Build my power supply design
Claude: [Uses jitx skill to set up environment and run build]

The extract_pages.py script helps extract relevant pages from large datasheets:

# Find pages with package info
python scripts/extract_pages.py datasheet.pdf --find "pinout" "dimension" "package"

# Extract specific pages
python scripts/extract_pages.py datasheet.pdf --pages 10 11 12 -o extract.pdf

Skills follow the Claude Code skill format with:

• SKILL.md containing frontmatter (name, description) and instructions
• Optional scripts/ for executable utilities
• Optional references/ for documentation loaded on demand
• Optional assets/ for templates and resources