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RALF Public
Reinforcement learning assisted analog layout design flow.
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caravel_user_project Public
Forked from efabless/caravel_user_projecthttps://caravel-user-project.readthedocs.io
Verilog Apache License 2.0 UpdatedFeb 11, 2022 -
OpenLane Public
Forked from The-OpenROAD-Project/OpenLaneOpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
Verilog Apache License 2.0 UpdatedFeb 3, 2022
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