Löwe is an open-source FPGA development board for the Cologne Chip GateMate CCGM1A1.
This repo contains PCB layouts, schematics, pinouts and example gateware.
Find more information on the Löwe product page.
In order to build the examples, first edit rtl/config.mk and set the paths to the location of your toolchain. You can download the toolchain from Cologne Chip.
You can build each example with:
$ make && make impl
You can then use openFPGALoader to write the gateware to SRAM or flash, using a Raspberry Pi Pico or Werkzeug (loaded with pico-dirtyJtag) in this example:
$ openFPGALoader -c dirtyJtag count_00.cfg.bit
The board has 4 DIP switches that select the configuration mode:
| Switches | Mode |
|---|---|
| 0000 | SPI Active Mode (CPOL=0 CPHA=0) |
| 0001 | SPI Active Mode (CPOL=0 CPHA=1) |
| 0010 | SPI Active Mode (CPOL=1 CPHA=0) |
| 0011 | SPI Active Mode (CPOL=1 CPHA=1) |
| 0100 | SPI Passive Mode (CPOL=0 CPHA=0) |
| 0101 | SPI Passive Mode (CPOL=0 CPHA=1) |
| 0110 | SPI Passive Mode (CPOL=1 CPHA=0) |
| 0111 | SPI Passive Mode (CPOL=1 CPHA=1) |
| 1100 | JTAG |
See the MMOD repo for details.
The 3.3V JTAG header can be used to program the FPGA SRAM as well as the MMOD flash memory.
5 3 1
6 4 2
| Pin | Signal |
|---|---|
| 1 | TCK |
| 2 | TDI |
| 3 | TDO |
| 4 | TMS |
| 5 | 5V01 |
| 6 | GND |
This project was partially funded through the NGI0 Entrust Fund, a fund established by NLnet with financial support from the European Commission's Next Generation Internet programme.
This project is released under the CERN-OHL-P license.
Footnotes
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This pin can be used to power the board with an external regulated 5V power supply, instead of USB power. ↩