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Commits on Feb 1, 2026

• Fixed BTC flag calculation (#79)

  Garfield1002

  authored
  0495ed6

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Commits on Sep 29, 2025

• riscv64: fix shift amount for shift and shiftw (#77)

  Cskorpion

  authored
  61f2373

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Commits on Feb 18, 2025

• x86: Catch remaining 'int imm8' with Ijk_Sys_int (#73)

  mborgerson

  authored
  421bf0d

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Commits on Dec 7, 2024

• amd64: Remap `int imm8` Ijk_Sys_syscall -> Ijk_Sys_int (#72)

  mborgerson

  authored
  e12bd8c

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Commits on Dec 6, 2024

• amd64: Remap `int imm8` Ijk_{NoDecode,Sys_int*}->Ijk_Sys_syscall (#70)

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  mborgerson

  authored
  390c476

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Commits on Sep 12, 2024

• amd64: Support lods rep prefixes (#66)

  mborgerson

  authored
  c0bace1

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• amd64: Support cmps repnz prefix and non-repeating cases (#65)

  mborgerson

  authored
  e7438bb

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Commits on Sep 10, 2024

• amd64: Use Intel behavior for 16b sh[lr]d when count>16 (#64)

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  mborgerson

  authored
  1ac1f89

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• amd64: Fix 32b cmpxchg unmodified register writeback (#63)

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  mborgerson

  authored
  0b97b66

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Commits on Sep 9, 2024

• codegen_xchg_rAX_Reg: Preserve RAX[63:16] in `xchg AX, r16` (#62)

  mborgerson

  authored
  54fca3e

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Commits on Nov 12, 2023

• guest_amd64_spechelper: Fix size inconsistency for ADDL CondZ. (#59)

  ltfish

  authored
  3e4d96a

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Commits on Aug 10, 2023

• Pr/draper riscv patch2 (#57)

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  EvelynVusky

  authored
  8c3b99e

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Commits on Aug 8, 2023

• VEX IR generator added for RISCV WFI instruction (#56)

  EvelynVusky

  authored
  441d2f1

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Commits on May 13, 2023

• add ctzll shim for msvc

  rhelmot

  committed
  b96e9ff

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• MSVC compat for risc-v

  rhelmot

  committed
  2d26e0e

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• riscv: fix instructions that use the unsupported Ity_1 data type

  

  alikates

  authored and

  rhelmot

  committed
  7576d04

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• add RISC-V to supported list in ir_opt

  

  alikates

  authored and

  rhelmot

  committed
  fd65310

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• riscv: fix vassert symbol not found by reordering/adding some includes

  

  alikates

  authored and

  rhelmot

  committed
  b2f5d64

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• riscv: remove unsupported Iops

  

  alikates

  authored and

  rhelmot

  committed
  7c43969

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• fix disInstr_RISCV64 function signature

  

  alikates

  authored and

  rhelmot

  committed
  5e8d1c4

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• Add RISCV64 support

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  petrpavlu

  authored and

  rhelmot

  committed
  02ae513

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Commits on Jan 12, 2023

• Implement fnop; closes angr/pyvex#290

  rhelmot

  committed
  e75200b

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Commits on Dec 1, 2022

• Feat/amd64 retf (#53)

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  dannyp303

  and

  Dan Pesce

  authored
  e8a5589

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Commits on Oct 12, 2022

• amd64: support read/write segment registers as if they were general-purpose (#51)

  rhelmot

  authored
  064b3fd

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Commits on Jul 5, 2022

• AMD64: Support rdsspd/rdsspq. (#49)

  ltfish

  authored
  6ec2c3f

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Commits on Mar 16, 2022

• Truncate ADDL args to 32bit

  rhelmot

  committed
  5e416aa

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Commits on Dec 23, 2021

• AMD64: Add a spechelper for ADDL and CondZ. (#47)

  ltfish

  authored
  9bcfa42

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Commits on Dec 17, 2021

• ARM: Add spechelpers for ADD-EQ/NE. (#45)

  ltfish

  authored
  5b3cab1

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• ARM: Support sub.w reg, reg, reg, lsl #0-4. (#46)

  ltfish

  authored
  375924d

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Commits on Sep 21, 2021

• Opt: Do not disable optimizations of VEX-specific registers. (#44)

  ltfish

  authored
  3440a56

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Commits on Sep 18, 2021

• Support lifting ARM syscalls under OABI. (#43)

  Show description for a6576a1
  

  degrigis

  and

  rhelmot

  authored
  a6576a1

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Commits on Aug 19, 2021

• Don't truncate 64-bit segment base in 32-bit addressing mode. (#42)

  edmcman

  authored
  85259cb

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Commits on Jun 20, 2021

• Provide explicit amount of lookback information to vex (#40)

  rhelmot

  authored
  0feb7ff

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Commits on May 20, 2021

• Fix ldrsw rX, [literal]; closes angr/pyvex#222

  rhelmot

  committed
  dfb44e7

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Commits on Apr 29, 2021

• Add flag to disable handling valgrind-special NOPs

  rhelmot

  committed
  efdd6c3

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