XLS: Accelerated HW Synthesis

Common SystemVerilog components

VeeR EL2 Core

RTL, Cmodel, and testbench for NVDLA

Verilator open-source SystemVerilog simulator and lint system

HW Design Collateral for Caliptra RoT IP

An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders

Implement a ChatGPT-like LLM in PyTorch from scratch, step by step

UVM Verification Environment for the CVFPU

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Official code repo for the O'Reilly Book - "Hands-On Large Language Models"

State-of-the-Art Deep Learning scripts organized by models - easy to train and deploy with reproducible accuracy and performance on enterprise-grade infrastructure.

55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.

A machine learning accelerator core designed for energy-efficient AI at the edge.

Textbook for advanced students and engineers on modern SoC design using Arm Cortex-A: architecture, interconnects, validation, and fabrication (educational)

A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

SonicBOOM: The Berkeley Out-of-Order Machine

Berkeley's Spatial Array Generator

130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design. Documentation is here:

Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.

4 stage, in-order, compute RISC-V core based on the CV32E40P

RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions