[bug] Fixed EVEX encoder accepting {k1} on unsupported insns#520
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es3n1n wants to merge 3 commits into
Open
[bug] Fixed EVEX encoder accepting {k1} on unsupported insns#520es3n1n wants to merge 3 commits into
es3n1n wants to merge 3 commits into
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The x86 test file already defines this macro for the commented-out failure block; mirror it on the x64 side so future PRs can add FAIL_INSTRUCTION(...) cases inline without reintroducing the macro each time.
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based on #513
the validator at
x86instapi.cpp:721already rejectsextra_reg=kNon instructions withouthas_avx512_k(), but the encoder'sEmitVexEvexR/EmitVexEvexMpath just ORs_extra_reg.id() << 16into the EVEXaaafield and emits. so in the default path (kValidateAssembleroff),setExtraReg(k1); emit(vpextrb, ...)produces EVEX bytes withaaa != 0on an instruction whereaaamust be 000 -#UDat runtimeisa_x86.jsonhad wrong{kz}markers onvpinsrb/vpinsrw/vpinsrd/vpinsrqEVEX rows and on thevmovw W:xmm {kz}, r32/m16row. intel sdm shows these with plain operand syntax - no{k1}{z}in the instruction reference. soinfoById().hasAvx512K()returned a lie and the encoder gate would fall through for those mnemonics even after fix 1https://revers.engineering/x86/pextrb.pdf
https://revers.engineering/x86/pinsrb.pdf
https://revers.engineering/x86/movw.pdf