Skip to content

Pull requests: diffblue/hw-cbmc

New pull request New
57 Open 1,751 Closed
57 Open 1,751 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Reviews
Filter by reviews
No reviews Review required Approved review Changes requested
Assignee
Filter by who’s assigned
Assigned to nobody Loading
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Pull requests list

Verilog: based_unsized_literal_exprt
#1882 opened Jun 13, 2026 by kroening Collaborator Loading…
1
Verilog: $root module does not need ports cleanup Verilog
#1875 opened Jun 4, 2026 by kroening Collaborator • Draft
module types now contain the symbol set Verilog
#1869 opened May 24, 2026 by kroening Collaborator • Draft
annotate enum types with their identifier cleanup Verilog
#1863 opened May 22, 2026 by kroening Collaborator • Draft
use existing verilog_ebmc_languaget::typecheck_module for $root cleanup Verilog
#1855 opened May 17, 2026 by kroening Collaborator • Draft
RFC: pyebmc Python bindings design
#1848 opened May 10, 2026 by kroening Collaborator Loading…
19
Verilog: grammar for classes Verilog
#1842 opened May 4, 2026 by kroening Collaborator • Draft
bump cbmc dependency dependencies Pull requests that update a dependency file
#1839 opened Apr 30, 2026 by kroening Collaborator • Draft
move logic for SVA cover into the property encoding Verilog
#1827 opened Apr 24, 2026 by kroening Collaborator • Draft
New IC3/PDR engine
#1817 opened Apr 21, 2026 by kroening Collaborator • Draft
Verilog: grammar for programs Verilog
#1811 opened Apr 18, 2026 by kroening Collaborator • Draft
Verilog: multiple top-level modules Verilog
#1807 opened Apr 17, 2026 by kroening Collaborator Loading…
netlist conversion: split up vector equality constraints engines
#1802 opened Apr 12, 2026 by kroening Collaborator • Draft
BDD model checker: early variable quantification
#1801 opened Apr 9, 2026 by kroening Collaborator • Draft
Verilog: $root Verilog
#1797 opened Apr 8, 2026 by kroening Collaborator • Draft
SystemVerilog: property-typed ports for checkers Verilog
#1739 opened Mar 18, 2026 by kroening Collaborator • Draft
class interface for flex
#1695 opened Mar 4, 2026 by kroening Collaborator • Draft
2
SystemVerilog: detect import conflicts Verilog
#1693 opened Mar 3, 2026 by kroening Collaborator • Draft
2
BDD engine: project away inputs engines
#1687 opened Mar 1, 2026 by kroening Collaborator • Draft
SystemVerilog queue benchmarks Tests Verilog
#1634 opened Feb 10, 2026 by kroening Collaborator • Draft
nondet elimination for AIGs engines
#1612 opened Feb 1, 2026 by kroening Collaborator • Draft
AIG simplifier using equivalences
#1605 opened Jan 26, 2026 by kroening Collaborator • Draft
1
bv_varidt now has next member engines
#1586 opened Jan 12, 2026 by kroening Collaborator • Draft
1
Verilog: use instance_array for width of primitive gates cleanup Verilog
#1501 opened Dec 20, 2025 by kroening Collaborator Loading…
1
SystemVerilog: sequence and property ports Verilog
#1436 opened Nov 24, 2025 by kroening Collaborator • Draft
ProTip! Type g p on any issue or pull request to go back to the pull request listing page.