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Is it disallowed to have a System without memory?

Status: Open.

#3225 In gem5/gem5;

· hchsiao opened on Jun 13, 2026

[SE mode] ldMin/ldMax never updated in ElfObject::handleLoadableSegment, causing mmap_end not to advance for dynamic linker

sim-segem5's Syscall Emulation Modegem5's Syscall Emulation Mode

Status: Open.

#3217 In gem5/gem5;

· nahj135 opened on Jun 12, 2026

sim/power: ThermalModel intermediate nodes initialized to 0 K (absolute zero), causing unphysical junction cooling

bug

simGeneral gem5 Simulation ComponentsGeneral gem5 Simulation Components

Status: Open.

#3192 In gem5/gem5;

· rtester1111-tech opened on May 21, 2026

BUG: O3 CPU inter-stage unblock signal causes 1-cycle bubble due to propagation delay

bug

cpu-o3gem5's Out-Of-Order CPUgem5's Out-Of-Order CPU

Status: Open.

#3190 In gem5/gem5;

· zhongchengyong opened on May 21, 2026

malloc(): bad size (unsorted) when BTB too large

bug

cpu-o3gem5's Out-Of-Order CPUgem5's Out-Of-Order CPU

Status: Open.

#3188 In gem5/gem5;

· muke101 opened on May 20, 2026

Crash when restoring from checkpoint with Ruby caches (Assertion `when >= getCurTick()' failed)

bug

mem-rubyRuby caches, structures, and protocolsRuby caches, structures, and protocols

Status: Open.

#3185 In gem5/gem5;

· derchr opened on May 19, 2026

BUG: ArmO3 SE can fault during early AArch64 TLS startup because misc-reg dependencies are released before commit

arch-armThe ARM ISAThe ARM ISA

bug

cpu-o3gem5's Out-Of-Order CPUgem5's Out-Of-Order CPU

sim-segem5's Syscall Emulation Modegem5's Syscall Emulation Mode

Status: Open.

#3157 In gem5/gem5;

· tsyw opened on May 9, 2026

O3 data prefetch unnecessarily holds LQ/ROB and cannot retire until memory response

bug

cpu-o3gem5's Out-Of-Order CPUgem5's Out-Of-Order CPU

Status: Open.

#3132 In gem5/gem5;

· pxk27 opened on Apr 29, 2026

No ROCm-capable device is detected (can't open /dev/gem5_bridge: No such file or directory)

arch-vegaThe VEGA ISAThe VEGA ISA

bug

Status: Open.

#3129 In gem5/gem5;

· Irfanuet191 opened on Apr 28, 2026

riscv: writes to minstret/mcycle CSR are incorrectly ignored

arch-riscvThe RISC-V ISAThe RISC-V ISA

bug

Status: Open.

#3098 In gem5/gem5;

· zhihaoxu1325 opened on Apr 20, 2026

O3: TimeBuffer assertion failure in IEW::instToCommit during massive LSQ wakeups.

bug

cpu-o3gem5's Out-Of-Order CPUgem5's Out-Of-Order CPU

Status: Open.

#3096 In gem5/gem5;

· tommyp6 opened on Apr 19, 2026

Bug: Incorrect latency calculation in SerialLink when system clock frequency is not 1GHz

bug

memGeneral Memory Systems (e.g., XBar, Packet)General Memory Systems (e.g., XBar, Packet)

Status: Open.

#3092 In gem5/gem5;

· pxk27 opened on Apr 17, 2026