The PL masters can also snoop APU caches through the APU’s accelerator coherency port(ACP). The ACP accesses can be used to (read or write) allocate into L2 cache. However, the ACP only supports aligned 64-byte and 16-byte accesses. All other accesses get a SLVERR response.

The ZynqMP-ACP-Adapter is an adapter to connect AXI Master to ZynqMP Accelerator Coherency Port(ACP).

The ACP supports only aligned 64-byte and 16-byte accesses.
The ZynqMP-ACP-Adapter splits a transaction of any burst length from the AXI Master into multiple 64-byte or 16-byte transactions.

The ZynqMP-ACP-Adapter will generate ACP_AxCache signals in place of the master if the master does not.
See parameter ARCACHE_OVERLAY or AWCACHE_OVERLAY for details.

The ZynqMP-ACP-Adapter will generate ACP_AxProt signals in place of the master if the master does not.
See parameter ARPROT_OVERLAY or AWPROT_OVERLAY for details.

The ZynqMP-ACP-Adapter will generate ACP_AxUser signals in place of the master if the master does not.
See parameter ARSHARE_TYPE or AWSHARE_TYPE for details.

The ZynqMP-ACP-Adapter is written in synthesizable VHDL.

shell$ wget https://github.com/ikwzm/ZynqMP-ACP-Adapter/archive/refs/tags/v1.1.tar.gz
shell$ tar xfz v1.1.tar.gz
shell$ cd ZynqMP-ACP-Adapter-1.1

Vivado > Settigns > IP > Repository > add ZynqMP-ACP-Adapter-1.1/ip

Vivado > Open Block Design > Add IP > select ZYNQMP_ACP_ADAPTER

These parameters specify the bit widths of various signals on the AXI side.

The bit width of the ACP ID is fixed at 5 bits.
AXI_ID_WIDTH(bit width of the ID on the AXI Master side) must be between 1 and 5.

The bit width of DATA in ACP is fixed at 128 bits.
AXI_DATA_WIDTH(bit width of RDATA/WDATA on AXI Master side) must be 128.

The bit width of ADDRESS in ACP is fixed at 40 bits.
AXI_ADDR_WIDTH(bit width of RDATA/WDATA on AXI Master side) must be greater than or equal to 1.

The bit width of AxUSER in ACP is fixed at 2 bits. ACP transactions can cause coherent requests to the system. Therefore, the ACP request must pass the inner and outer shareable attributes to the L2. To pass the shareable attributes, use AxUSER; the encoding of AxUSER is shown in the following table.

The conversion from AXI_AxUSER to ACP_AxUSER is based on ARSHARE_TYPE or AWSHRE_TYPE.
The valid AXI_AUSER_WDITH(bit width of the AxUSER on the AXI Master side) for this conversion is different.
See ARSHARE_TYPE or AWSHARE_TYPE for details.

These parameters control the generation of the ACP_ARCACHE signal.
To use ACP for cache coherency transfers, ACP_ARCACHE should output “1111” or “1110”.

These parameters are output with ACP_ARCACHE encoded as follows.

     constant cache_mask  :  std_logic_vector(3 downto 0) 
                          := std_logic_vector(to_unsigned(ARCACHE_OVERLAY, 4));
     constant cache_value :  std_logic_vector(3 downto 0) 
                          := std_logic_vector(to_unsigned(ARCACHE_VALUE  , 4));
    
     ACP_ARCACHE(0) <= cache_value(0) when (cache_mask(0) = '1') else AXI_ARCACHE(0);
     ACP_ARCACHE(1) <= cache_value(1) when (cache_mask(1) = '1') else AXI_ARCACHE(1);
     ACP_ARCACHE(2) <= cache_value(2) when (cache_mask(2) = '1') else AXI_ARCACHE(2);
     ACP_ARCACHE(3) <= cache_value(3) when (cache_mask(3) = '1') else AXI_ARCACHE(3);

If ARCACHE_OVERLAY is 0, the AXI_ARCACHE signal is output directly to ACP_ARCACHE.
If ARCACHE_OVERLAY is 15, the AXI_ARCACHE signal is not used and the value of ARCACHE_VALUE is output.

These parameters control the generation of the ACP_ARPROT signal.
To use ACP for cache coherency transfers, ACP_ARPROT should output “010”.

These parameters are output with ACP_ARPROT encoded as follows.

     constant prot_mask  :  std_logic_vector(2 downto 0) 
                         := std_logic_vector(to_unsigned(ARPROT_OVERLAY, 3));
     constant prot_value :  std_logic_vector(2 downto 0) 
                         := std_logic_vector(to_unsigned(ARPROT_VALUE  , 3));
    
     ACP_ARPROT(0) <= prot_value(0) when (prot_mask(0) = '1') else AXI_ARPROT(0);
     ACP_ARPROT(1) <= prot_value(1) when (prot_mask(1) = '1') else AXI_ARPROT(1);
     ACP_ARPROT(2) <= prot_value(2) when (prot_mask(2) = '1') else AXI_ARPROT(2);

If ARPROT_OVERLAY is 0, the AXI_ARPROT signal is output directly to ACP_ARPROT.
If ARPROT_OVERLAY is 7, the AXI_ARPROT signal is not used and the value of ARPROT_VALUE is output.

These parameters control the generation of the ACP_ARUSER signal.

These parameters are output with ACP_ARUSER encoded as follows.

These parameters set the internal register availability.
See source code for details.

These parameters control the generation of the ACP_AWCACHE signal.
To use ACP for cache coherency transfers, ACP_AWCACHE should output “1111” or “1110”.

These parameters are output with ACP_AWCACHE encoded as follows.

     constant cache_mask  :  std_logic_vector(3 downto 0) 
                          := std_logic_vector(to_unsigned(AWCACHE_OVERLAY, 4));
     constant cache_value :  std_logic_vector(3 downto 0) 
                          := std_logic_vector(to_unsigned(AWCACHE_VALUE  , 4));
    
     ACP_AWCACHE(0) <= cache_value(0) when (cache_mask(0) = '1') else AXI_AWCACHE(0);
     ACP_AWCACHE(1) <= cache_value(1) when (cache_mask(1) = '1') else AXI_AWCACHE(1);
     ACP_AWCACHE(2) <= cache_value(2) when (cache_mask(2) = '1') else AXI_AWCACHE(2);
     ACP_AWCACHE(3) <= cache_value(3) when (cache_mask(3) = '1') else AXI_AWCACHE(3);

If AWCACHE_OVERLAY is 0, the AXI_AWCACHE signal is output directly to ACP_AWCACHE.
If AWCACHE_OVERLAY is 15, the AXI_AWCACHE signal is not used and the value of AWCACHE_VALUE is output.

These parameters control the generation of the ACP_AWPROT signal.
To use ACP for cache coherency transfers, ACP_AWPROT should output “010”.

These parameters are output with ACP_AWPROT encoded as follows.

     constant prot_mask  :  std_logic_vector(2 downto 0) 
                         := std_logic_vector(to_unsigned(AWPROT_OVERLAY, 3));
     constant prot_value :  std_logic_vector(2 downto 0) 
                         := std_logic_vector(to_unsigned(AWPROT_VALUE  , 3));
    
     ACP_AWPROT(0) <= prot_value(0) when (prot_mask(0) = '1') else AXI_AWPROT(0);
     ACP_AWPROT(1) <= prot_value(1) when (prot_mask(1) = '1') else AXI_AWPROT(1);
     ACP_AWPROT(2) <= prot_value(2) when (prot_mask(2) = '1') else AXI_AWPROT(2);

If AWPROT_OVERLAY is 0, the AXI_AWPROT signal is output directly to ACP_AWPROT.
If AWPROT_OVERLAY is 7, the AXI_AWPROT signal is not used and the value of AWPROT_VALUE is output.

These parameters control the generation of the ACP_AWUSER signal.

These parameters are output with ACP_AWUSER encoded as follows.

These parameters set the internal register availability.
See source code for details.

Distributed under the BSD 2-Clause License.