PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers

A flexible Python 2/3 Kconfig implementation and library

PolarFire SoC Documentation

A simple script to build a PMU firmware for Xilinx ZynqMP

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

An implementation of a small TCP/IP protocol stack for learning.

Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL

SystemVerilog to Verilog conversion

Raspberry Pi v2 camera (IMX219) to DisplayPort of Ultra96-V2 board through PL

The PoC Library has been forked to github.com/VHDL/PoC. See new address below

Universal utility for programming FPGA

XLS: Accelerated HW Synthesis

Original FPGA platform

🤖 SoCFPGA: Open-Source Embedded Linux Distribution with a highly flexible build system, developed for Intel (ALTERA) SoC-FPGAs (Cyclone V & Arria 10)

VHDL library 4 FPGAs

Accelerating a Classic 3D Video Game (The DOOM) on Heterogeneous Reconfigurable MPSoCs

Verilator open-source SystemVerilog simulator and lint system

Send video/audio over HDMI on an FPGA

NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network

This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).

HOG + SVM on FPGA

Python like C++ Argument parser

Verilog AXI components for FPGA implementation

Fletcher: A framework to integrate FPGA accelerators with Apache Arrow

A fast VHDL language server and analysis library written in Rust

A minimal Linux kernel module written in rust.

Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)