GitHub - joshysav/MicroMips: MicroMips CPU core in VHDL

Name		Name	Last commit message	Last commit date
Latest commit History 16 Commits
db		db
incremental_db		incremental_db
output_files		output_files
simulation/modelsim		simulation/modelsim
alu.vhd		alu.vhd
chip_selector.vhd		chip_selector.vhd
chip_selector.vhd~		chip_selector.vhd~
clock_unit.vhd		clock_unit.vhd
clock_unit.vhd.bak		clock_unit.vhd.bak
clock_unit.vhd~		clock_unit.vhd~
control_unit.vhd		control_unit.vhd
core.vhd		core.vhd
core.vhd~		core.vhd~
datapath.vhd		datapath.vhd
datapath_multi.vhd		datapath_multi.vhd
datapath_multi.vhd~		datapath_multi.vhd~
decode_unit.vhd		decode_unit.vhd
decode_unit.vhd~		decode_unit.vhd~
execute_unit.vhd		execute_unit.vhd
execute_unit.vhd~		execute_unit.vhd~
fetch_unit.vhd		fetch_unit.vhd
fetch_unit.vhd~		fetch_unit.vhd~
mem_256x8.vhd		mem_256x8.vhd
mem_256x8.vhd~		mem_256x8.vhd~
micro_mips.ipinfo		micro_mips.ipinfo
micro_mips.qpf		micro_mips.qpf
micro_mips.qsf		micro_mips.qsf
micro_mips.qws		micro_mips.qws
micro_mips_assignment_defaults.qdf		micro_mips_assignment_defaults.qdf
micro_mips_nativelink_simulation.rpt		micro_mips_nativelink_simulation.rpt
mux2_32.vhd		mux2_32.vhd
mux3_32.vhd		mux3_32.vhd
mux3_5.vhd		mux3_5.vhd
mux4_5.vhd		mux4_5.vhd
ram.vhd		ram.vhd
register_file.vhd		register_file.vhd
rom.vhd		rom.vhd
soc.vhd		soc.vhd
soc.vhd~		soc.vhd~
writeback_unit.vhd		writeback_unit.vhd
writeback_unit.vhd~		writeback_unit.vhd~