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ML Researcher at Gdańsk University of Technology and NASK Research Institute
- Gdańsk, Poland
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18:46
(UTC +02:00) - https://orcid.org/0009-0005-8430-3248
- in/dominik-lau
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written in Verilog
Clear filter
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Verilog AXI components for FPGA implementation
Hardware accelerator for convolutional neural networks