A set of Python/Rust tools to aid routing in KiCad

CoreScore

pedal

FPGA based usb stick true random number generator (TRNG)

KiCAD MCP is a Model Context Protocol (MCP) implementation that enables Large Language Models (LLMs) like Claude to directly interact with KiCAD for printed circuit board design.

Example project for the BRS-100-GW1NR9 FPGA development board.

Qrisc cpu based on mine qrisc32, in different languages

Open-source Ethernet MAC with AXI4-Stream, AXI4-Lite CSR, MDIO, MII to RGMII support, jumbo frames, and stats.

SpaceWire Light

An agent skill that turns an HDL / RTL / SoC architecture description into a clean SVG block diagram

1GigE UDP uplink of the live, real-time camera video stream. Think of it as Webcam-over-Ethernet, or RemoteCam. Great for security apps, this is a component of our 'openeye-CamSI' project that may …

A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open …

Open Source LTE platform - Aims to be an Open Source Software Defined Radio (SDR) Erlang and C++ implementation of the 3GPP release 10 LTE spec

An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. This is fork extends its functionality

Real-time drone detection @ blazing fast 30 FPS on RV1106 | Zero-copy DMA + hardware RGA acceleration | YOLOv5 RKNN | MAVLink telemetry streaming | Picoclaw integration

fcapz: Open-source, vendor-agnostic full-featured FPGA debug cores. Embedded Logic analyzer, Embedded I/O and Embedded JTAG-AXI

Open-source, low-cost 10.5 GHz PLFM phased array RADAR system

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

An open-source Model Context Protocol server that gives AI assistants a complete FPGA toolchain — lint, simulate, synthesize, place-and-route, and a live IP core registry backed by GitHub.

SERV - The SErial RISC-V CPU

Open source AXI4 / AXI4-Lite interconnect generator. Describe your bus topology in YAML, get you Verilog back

Open source synthesizable MJPEG encoder written in behavioral Verilog 2001 with AXI interfaces, up to 1080p30 on low end AMD/Xilinx 7-Series FPGAs. Two operating modes: Full encodes with runtime qu…

Build your hardware, easily!

An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码器，可实现高压缩率的无损/近无损图像压缩。

An FPGA-based Ultra-High Throughput JPEG-LS encoder, which provides lossless image compression. 一个超高性能的FPGA JPEG-LS编码器，用来进行无损图像压缩。

AI agents running research on single-GPU nanochat training automatically

Generates synthesizable VHDL & Verilog, parallel CRC modules from a built-in catalog of 80+ named algorithms, or from user-supplied polynomial parameters. Optional AXI4-S wrappers, Self-checking te…