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firtool-1.149.0

30 May 02:17
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firtool-1.149.0 Latest
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What's Changed

  • [LowerToHW] Add support for lower-to-core in firrtl.fprintf by @nanjo712 in #10452
  • [ESI][Runtime] Codegen: emit structs with accessors by @teqdruid in #10538
  • [SimToSV] Fix an error occurred when a sim.pause is nested in a scf.if by @nanjo712 in #10535
  • [ESI][Runtime] Support for integrals >64 bits by @teqdruid in #10548
  • Bump LLVM by @uenoku in #10542
  • [SimToSV] Lower sim.flush to sv.fflush by @nanjo712 in #10546
  • [Sim] Add convert-to-hw for SquashSimTriggered by @nanjo712 in #10534
  • [FIRRTLToHW] Print to stderr in lower-to-core path by @nanjo712 in #10544
  • Add BMCTrace runtime support and unit tests for text counterexample formatting by @5iri in #10537
  • [CI] Include the Runner Image Version in the sccahe key as a string by @okekayode in #10547
  • [ESI][Runtime] Cosim: remove MtiPli target and resolve svDpi at runtime by @teqdruid in #10553
  • [Synth] Fix NPN input permutation mapping by @uenoku in #10543
  • [circt-lec] Lower truth tables before SMT conversion by @uenoku in #10491
  • [OM] Use FlatSymbolRefAttr for object class names by @uenoku in #10554
  • [Moore][ImportVerilog][MooreToCore][Sim] Add $fdisplay and $fwrite by @VecoMr in #10520
  • [ESI][Runtime] Make esi-cosim work on Windows by @teqdruid in #10558
  • [SV] Add pass to hide non-synthesizable ops by @teqdruid in #10479

Full Changelog: firtool-1.148.0...firtool-1.149.0

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teqdruid, uenoku, and 4 other contributors
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firtool-1.148.0

25 May 12:51
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Full Changelog: firtool-1.147.0...firtool-1.148.0

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rocallahan, jpienaar, and 11 other contributors
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firtool-1.147.0

16 May 05:35
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firtool-1.147.0

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jmolloy, rocallahan, and 17 other contributors
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firtool-1.146.0

01 May 21:41
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What's Changed

  • [ci] Use old (macOS) bash-compatible lowercase by @seldridge in #10306
  • [circt-test] Print empty JSON array when listing tests on empty input by @ankit-cybertron in #10295
  • [AGENTs] Fix ESI/PyCDE directions and add a style rule by @teqdruid in #10307
  • [ESI][Runtime] Switch ReadChannelPort to segmented by @teqdruid in #10308
  • [ci] Exclude z3 from macOS tests by @seldridge in #10309
  • [CI] Add extra_cmake_args option to UBTI and enable LLVM_ENABLE_REVERSE_ITERATION by @uenoku in #10300
  • [lldh] Revert Recent Mem2Reg Changes by @seldridge in #10318
  • [Synth][FunctionalReduction] Add a newVar interface to SATSolver and use it in FR by @okekayode in #10316
  • [Synth] Add dot gate by @uenoku in #10277
  • Bump LLVM by @uenoku in #10320
  • [CI] Enable Reverse iteration by @uenoku in #10312
  • [Synth][FunctionalReduction] Improve choice materialization with reachability of choice by @okekayode in #10319
  • [SimToSV] support lowering stdout/stderr by @nanjo712 in #10283
  • [OM] Switch to IntegerBinaryInterface by @seldridge in #10328
  • [Synth][FunctionalReduction] Remove redundant reachable values from choice classes by @okekayode in #10325
  • [Support][SATSolver] Add at-most-one / exactly-one clause helpers by @uenoku in #10324
  • [FIRRTL][OM] Add Bool/Integer And/Or/Xor by @seldridge in #10322
  • [LowerToHW] Extract the logic related to file descriptor acquisition as a common utility function by @nanjo712 in #10288
  • [FSM] Canonicalize away no-op updates by @TaoBi22 in #10336
  • Prioritize in-tree MLIR headers in unified builds by @gipsyh in #10331
  • [Synth] Clean up boolean logic interface, NFC by @uenoku in #10333
  • [OM] Add ElaboratedObjectOp by @uenoku in #10334
  • [ESI][Runtime] Fix race condition in port disconnects by @teqdruid in #10342
  • [ESI][Runtime] Refactor promise fulfill logic in ReadChannelPort by @teqdruid in #10343
  • [ESI][Runtime] TypeDeserializer handles complex messages by @teqdruid in #10310
  • Bump LLVM to 90c90a41bed5ba2e4c7b724ecfd533f6f3f7d204 by @TaoBi22 in #10345
  • [CoreToFSM] Avoid violating pattern invariants in getReachableStates by @TaoBi22 in #10347
  • [MSFT] Fix Python DeviceDB test by @teqdruid in #10351
  • [OM] Clean up ObjectOfieldOp: Move away from symbols, remove a field path and VerifyObjectFields pass by @uenoku in #10303
  • [OM] Drop memory effects from Class, Object by @seldridge in #10352
  • [FSMToSMT] Allow fsm.machines with no outputs/vars by @TaoBi22 in #10354
  • [FIRRTL] InferDomains: On error, print more diagnostic information by @rwy7 in #10337
  • [CoreToFSM] Move topological sorts to avoid pattern invariant violation by @TaoBi22 in #10355
  • [ExportVerilog] Drop 'reg' for unpacked arrays too by @teqdruid in #10361
  • [FIRRTL] Add "hasProperties" to InstanceInfo by @seldridge in #10359
  • [NFC][FSMToSMT] Make error test names more informative by @TaoBi22 in #10364
  • [CellIFT] Add CellIFT instrumentation pass for HW/Comb/Seq IR by @flaviens in #10250
  • [SimToSV] lower sim.get_file to i32 fd by @nanjo712 in #10335
  • [FIRRTL] Include "public" in hasProperties logic by @seldridge in #10365
  • [LLHD] Run Mem2Reg per slot to fix cubic scaling by @fabianschuiki in #10321
  • [LLHD][Deseq] Lower reset-only async reset processes as register holds by @gipsyh in #10344
  • [Moore][ImportVerilog] Implement static $cast via materializeConversion by @sunhailong2001 in #10156
  • [CI] Run integration tests in Clang as well by @uenoku in #10366
  • [ESI][Runtime] Update AGENTS.md with debuging tips by @teqdruid in #10367
  • [ESI][Runtime] Message translation: check for support by @teqdruid in #10368
  • [PyCDE] Modules to convert parallel <--> serial lists by @teqdruid in #10360
  • [PyCDE] Add AGENTS.md with hardware dev tips by @teqdruid in #10369
  • [FIRRTL] Create classes for transitive properties by @seldridge in #10362

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Full Changelog: firtool-1.145.0...firtool-1.146.0

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fabianschuiki, seldridge, and 10 other contributors
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firtool-1.145.1

24 Apr 21:50
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firtool-1.145.0

23 Apr 16:06
@seldridge seldridge
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jmolloy, fabianschuiki, and 26 other contributors
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firtool-1.144.0

01 Apr 01:20
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firtool-1.144.0

firtool 1.144.0 Release Notes

Changes between firtool-1.143.0 and firtool-1.144.0.

FIRRTL

  • Erase wire domain operands during lowering (ca2e93f)
  • Infer wires w/ domain associations (c4283b2)
  • Add parser/printer for wire w/ domains (2301d8e)
  • Extend WireOp verifier for domains (b6db749)
  • Add variadic domain operands to WireOp (0d36a8c)
  • Make wording for optional intrinsic args/params consistent; NFC (#10092)
  • Add ltl.past intrinsic (#10091)
  • [LowerToHW] Change InstanceChoice ABI from header files to defines (#10042)
  • Fix LowerClasses Objects not InstanceLike (#10081)
  • reduction test: find utilities via /usr/bin/env. (#10079)
  • Remove convention verification for InstanceChoice (#10066)
  • Don't use matching connect for bundles w/ analog (#10054)
  • Move InferDomains pass after ExpandWhens (#10043)
  • Remove getPortNames from FInstanceLike (#10039)
  • parser: support rwprobe of open-agg instance results. (#10018)
  • Extend emitConnect to open aggregates. (#10017)
  • Fix use-before-def in InferDomains (#10029)
  • Add type lowering support for InstanceChoiceOp (#9970)
  • [LOA] Fix bug dropping inner symbol within mapped type. (#10026)
  • [NFC] Use OpRewritePattern in FIRRTLFolds (#10023)
  • [OM] Add string.concat canonicalization (#9997)
  • Utils: fix getValueByFieldID for open aggregates. (#10016)
  • [InferResets] Add InstanceChoice support (#9955)
  • Remove FInstanceLike from ObjectOp and add interface methods to FInstanceLike, NFCI (#9975)
  • Fix a failure when the number of operands are missing on format string (#10044)

OM

  • Evaluator: fix type mismatch for unknown object fields (#10085)

SV

  • Add SymbolUserOpInterface to VerbatimOp and friends (#10088)

HW

  • Verify port_locs length in module verifier (#10013)
  • Fix crash on self-referential hw.wire canonicalize (b59eca8)

Arc

  • [StripSV] Replace i1 macro references with true constants (#10086)
  • Fix trace-instrumentation test to use supported directives. (#10027)
  • Fix aliases in FST trace files (#10076)
  • Add optional support for FST tracing. (#9979)

ImportVerilog

  • Handle $monitor([boh]?|on|off) statements (#10057)
  • Emit coroutines for tasks (#10070)
  • Fix signal captures in timing controls (#10067)
  • Add initial virtual interface lowering (#10035)
  • Add initial virtual interface lowering (#9904)
  • Fix crash on instance with unconvertible port values (1625085)
  • Fix crash on array new with unsupported size expr (9445def)
  • Fix crash on continuous assign with rise/fall delay (#9994)
  • Fix crash on repeat loop with real count (#9992)
  • Fix crash on enum traversal methods (#9988)
  • Use FileLineColRange for source ranges. (#10014)

Moore

  • Unify random builtins into urandom_range, add lowering (#10071)
  • Add coroutine, call_coroutine ops; lower to LLHD (#10069)
  • Fix crash on self-referential AssignedVariableOp canonicalize (72acea9)

MooreToCore

  • [HW] Fix a few compiler warnings, NFC (f2ee27b)
  • Fix queue pop conversions bypassing rewriter (b190784)
  • Fix crash on class new with unsupported member types (#10001)
  • Fix crash on dynamic array variable conversion (#9996)

LLHD

  • Add coroutine, call_coroutine, return ops (#10068)
  • Don't promote signals with projections and mixed drive delays (#10004)
  • Don't promote signals with cross-block nested projections (#10003)
  • Skip slots without drive sets in HoistSignals (#10000)
  • Handle float types in HoistSignals, skip unsupported types (#9999)
  • Handle union types in Mem2Reg signal promotion (#9995)
  • Don't promote signals with non-integer types in Mem2Reg (#9989)

Synth

  • [ResourceUsage] Fix misuse of InstanceGraphNode::getModule, report truth table total count (#10078)
  • [CutRewriter] Add stats (#10077)
  • Extend functional reduction SAT support to OR/XOR/MIG (#10009)
  • Add canonicalization for synth.choice (#10019)
  • [SynthToComb] Support n-input MIG to comb lowering (#10008)
  • Add basic SAT construction for functional reduction (#9939)
  • [Synth] Implement operation reuse for LowerVariadic (#9964)

CombToSynth

  • Lower majority-inverter to and-inverter (#9947)

Support

  • Add CaDiCaL SAT solver backend (#10032)
  • [SATSolver] Add an utility for assume, split decl and def, NFC (#10011)
  • [SATSolver] Add indexed max heap utility (#9945)

CoreToFSM

  • Require that all registers have the same reset signal (#10064)
  • Error out on multiple reg clocks (#10061)
  • Error out when clocks are used outside regs (#10060)

ESI

  • [Runtime] Add ChannelService for raw to_host/from_host channels (#10072)
  • [Runtime] Stop publishing weekly and upload debug (#10002)
  • [Runtime] Include "verilated_random.cpp" if available (#9991)

circt-reduce

  • Add reset disconnect reduction (#10059)
  • Add convention attribute remover (#10058)
  • Fix connect-forwarder crash (#10052)
  • Fix module-port-pruner crash on ports with uses (#10040)
  • Add IMDCE as a FIRRTL reduction (#10046)

Sim

  • Fix null dereference in StringConcatOp::fold (#9990)

FlattenMemRefs

  • Remove global static variables (#10024)

InstanceGraph

  • Relax assertion failure condition (#10005)

HWToSystemC

  • Fix illegal Op creation (#10012)

Release

  • Add macOS AARCH64 (macos-15) runner to release artifacts (#10082)

New Contributors

Full Changelog: firtool-1.143.0...firtool-1....

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Contributors

AmurG, nanjo712, and AayushMainali-Github
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firtool-1.143.0

23 Mar 00:59
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firtool-1.143.0

CIRCT Release Notes: firtool-1.143.0

FIRRTL Dialect

String Properties

This release adds comprehensive support for string concatenation in FIRRTL
properties:

  • New firrtl.string.concat operation ([15f44a9], [32d7d87], [ae00359]):
    Concatenate multiple string property values with full support in parsing,
    emission, and lowering to OM. This enables building complex string properties
    from multiple components.

    Example:

    %result = firrtl.string.concat %prefix, %name, %suffix

  • The operation lowers cleanly through LowerClasses to OM's om.string.concat
    ([2f9b5c9]) and includes evaluator support ([34e5533]) for runtime string
    concatenation.

Domain System Overhaul

The domain system has undergone a major redesign to align with FIRRTL's
class-based property system:

  • Domains are now similar to classes ([#9871]): Domain types now include
    symbol references and field name/type tuples, making them structurally similar
    to FIRRTL classes. This unification simplifies the type system and enables
    better tooling support.

  • Field value support ([#9902]): DomainCreateOp now accepts variadic field
    values as operands, allowing domains to be instantiated with specific field
    values directly. This eliminates the need for separate assignment operations.

    Example:

    %domain = firrtl.domain.create @ClockDomain(%clk, %reset)

  • New DomainSubfieldOp ([#9910]): Extract field values from domain
    instances using firrtl.domain.subfield, similar to how object fields are
    accessed.

  • Improved domain inference ([#9958]): The InferDomains pass now properly
    handles DomainCreateOp and DomainCreateAnonOp, preventing spurious domain
    inference on modules containing these operations. Error messages for domain
    unification conflicts are now more user-friendly.

  • Simplified storage ([#9896]): Domain information is now stored exclusively
    in types rather than duplicated in the domainInfo attribute, reducing
    redundancy and potential inconsistencies.

  • Domain stripping improvements ([#9931]): The domain stripping mode now
    properly handles DomainSubfieldOp by replacing uses with UnknownValueOp
    before erasure.

Intrinsics

  • All intrinsics migrated to TableGen ([#9847]): The remaining 34
    manually-registered FIRRTL intrinsics have been moved to the
    FIRRTLIntrinsics.td TableGen file. This enables automatic generation of both
    registration code and documentation. Previously undocumented intrinsics (LTL
    ops, clock_inv, clock_div, mux cells, has_been_reset, fpga_probe) now have
    proper descriptions with argument/result tables.

Instance Choice Support

  • ExpandWhens support ([#9956]): The ExpandWhens pass now properly handles
    InstanceChoiceOp, treating it the same as regular InstanceOp for
    when-block expansion.

  • InstanceInfo tracking ([#9811]): The InstanceInfo analysis now tracks
    modules instantiated within instance choice operations, following the same
    pattern as other module attributes like inDesign and inEffectiveDesign.

Cross-Module References (XMR)

  • Cleaner port references ([#9954]): When a RefSendOp references a port,
    the LowerXMR pass now adds an inner symbol directly to the port instead of
    creating an intermediate node. This produces cleaner Verilog output and works
    around issues with certain formal tools that treat output ports assigned from
    probe nodes as "uncovered".

Layer Improvements

  • Capture naming ([#9957]): Changed the namehint for layer-captured
    expressions from _layer_probe to _layerCapture to avoid conflicts with
    protocols that use "probe" terminology.

Other Improvements

  • Circuit linking ([#9928]): The firld tool now allows private extmodules
    in circuit linking, providing more flexibility in modular compilation
    workflows.

OM Dialect

New Features

  • String concatenation ([2f9b5c9], [34e5533]): Added om.string.concat
    operation with full evaluator support for runtime string concatenation.

  • Python bindings ([#9868]): Added Python bindings for OM unknown value
    operations.

HW Dialect

New Optimization Pass

  • Inter-Module Dead Code Elimination (IMDCE) ([#9609]): A new aggressive
    optimization pass that performs inter-module liveness analysis. The pass
    considers a value alive only if it connects to a port of a public module or a
    value with a symbol. This can significantly reduce design size by removing
    unused logic across module boundaries.

Breaking Changes

  • Removed hw.instance_choice ([#9849]): The hw.instance_choice operation
    has been removed from the HW dialect. firrtl.instance_choice now lowers
    directly to implement the FIRRTL ABI in LowerFIRRTLToHW, avoiding the need to
    carry specialized ABI information (macros and headers) into the HW dialect.

Formal Verification and Model Checking

This release significantly expands formal verification capabilities,
particularly for BTOR2-based model checking:

Verification Dialect

  • New FoldAssume pass ([#9968]): Optimizes verification code by folding and
    simplifying assume operations.

  • Named symbolic values ([#9919]): The verif.symbolic_value operation now
    accepts an optional name parameter, improving readability in formal backends
    while preserving original signal names.

  • Improved CombineAssertLike ([#9983]): The pass now supports verif.formal
    operations, enabling better optimization of formal verification constructs.

BTOR2 Backend Enhancements

The HWToBTOR2 conversion has received substantial improvements for formal
verification workflows:

  • Formal operation support ([#9926]): Added basic support for verif.formal
    operations, enabling structured formal verification blocks in BTOR2 output.

  • Symbolic value emission ([#9924]): verif.symbolic_value operations now
    emit as input in BTOR2, properly representing free variables in model
    checking.

  • Initialization assumptions ([#9844]): New --assume-init-reset option
    allows assuming reset initialization in formal proofs, simplifying
    verification of designs with complex reset logic.

  • Clock conversion ([#9837]): Added support for seq.to_clock operation,
    enabling proper handling of clock type conversions in BTOR2 output.

  • Improved register handling ([#9916], [#9838]): The backend now only
    accepts integer-typed registers and avoids generating invalid BTOR2 when
    multiple registers share the same name.

Temporal Logic

  • LTL past operations ([#9845], [#9892]): Added lowering for ltl.past
    operations with clock operands, and integrated these lowerings into the
    firtool BTOR2 pipeline.

  • Clock assumption control ([#9863]): New --assume-first-clock flag for
    LTLToCore enables better control over clock assumptions when ingesting
    SystemVerilog assertions.

Synthesis and Optimization

Synth Dialect

The Synth dialect introduces new abstractions for synthesis choices and
optimizations:

  • New synth.choice operation ([#9857], [#9872], [#9876], [#9940]):
    Represents synthesis alternatives, allowing the compiler to choose between
    different implementations. The operation folds when only a single operand
    remains and is supported throughout the lowering pipeline (LowerWordToBits,
    ConvertSynthToComb).

  • Functional reduction pass ([#9886]): New optimization pass for functional
    reduction (without SAT solving). This enables simplification of synthesis
    choices based on functional equivalence.

  • Majority graph folding ([#9033]): Implements optimization for majority
    gate graphs, a common pattern in certain synthesis flows.

  • Operation reuse in LowerVariadic ([#9850]): The LowerVariadic pass now
    implements operation reuse, reducing redundant operations when lowering
    variadic operations.

Seq Dialect

  • Clock-enable register lowering ([#9890]): Added lowering from
    seq.compreg.ce (clock-enable register) to seq.compreg (standard register),
    expanding the range of register types that can be processed through the
    standard pipeline.

  • Preset value validation ([#6856]): The FirRegOp printer/parser now
    enforces non-negative preset values, catching errors earlier in the
    compilation flow.

  • Memory address type fix ([#9827]): Fixed invalid address type generation
    for single-element memories in the RegOfVecToMem pass.

SystemVerilog Import (ImportVerilog)

This release dramatically expands SystemVerilog import capabilities,
particularly for advanced language features:

Interface Support

  • Full interface support ([#9792]): Added comprehensive support for
    interface definitions, instantiation, and interface port handling. This is a
    major milestone for importing designs that use SystemVerilog interfaces.

  • Unconnected ports ([#9759]): Support for unconnected InOut and Ref
    instance ports, allowing partial port connections.

Dynamic and Associative Arrays

  • Dynamic array creation ([#9679]): Added support for dynamic array creation
    with new size and length operations.

  • Associative array methods ([#9853], [#9901], [#9907]): Implemented
    Size(), Num(), exists(), First(), Last(), Next(), and Prev()
    methods for associative arrays.

  • Queue operations ([#9791], [#9818]): Added support for queue
    concatenations and queue comparisons (equality/inequality).

Concurrency and Timing

  • Wait statements ([#9824]): Added support for wait and wait fork
    statements, enabling import of designs with complex synchronization.

  • Fork-join fixes ([#9951]): Fixed bugs in fork-join statement handling.

Asserti...

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Contributors

joaovam, yuriyKulinchenko, and 2 other contributors
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firtool-1.142.0

06 Mar 05:44
@seldridge seldridge
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firtool-1.142.0

What's Changed

  • [Arc] Fix extraneous semicolons in TraceEncoder; NFC by @fabianschuiki in #9746
  • [circt-bmc] Add LTLToCore to pipeline by @TaoBi22 in #9735
  • [HW][circt-reduce] Add HW name sanitization by @seldridge in #9730
  • Move ESI runtime tests into pytest suite by @teqdruid in #9655
  • [CI] Cancel in-progress PR builds on new push by @Copilot in #9751
  • [ImportVerilog][MooreToCore][Sim] Support queue element/range extractions in ImportVerilog and Sim by @Lauriethefish in #9727
  • [Synth] Add resource usage analysis by @uenoku in #9717
  • [HW] Make sure the index type for arrays is at least i1 by @pscabot in #9733
  • [ImportVerilog] Make sampled value functions' results usable by Moore ops by @Arya-Golkari in #9718
  • [ImportVerilog] Support $ literal within queue indexing expressions by @Lauriethefish in #9719
  • [circt-reduce] Use per-port matching for FIRRTL port pruners by @seldridge in #9755
  • [Arc] Add time operations for LLHD simulation support by @fabianschuiki in #9747
  • [FIRRTL] Allow full reset module instances outside of reset domain by @fabianschuiki in #9754
  • [HWToLLVM] Take the correct data layout alignment for alloca by @pscabot in #9734
  • [FIRRTL][LowerToHW] Add InstanceChoiceOp lowering, Part 1 by @uenoku in #9742
  • [FIRRTL] Fix domain info updates in cloneWithInsertedPorts by @seldridge in #9758
  • [Datapath] Bug Fix for Sign-Extension Logic when Lowering Partial Products to Booth Arrays (#9726) by @cowardsa in #9744
  • [ESI] Update test to exercise new functionality by @teqdruid in #9763
  • [PyRTG] Add String format function by @maerhart in #9762
  • [ESI][Runtime] Support editable installs by @teqdruid in #9764
  • [ESI][Runtime] Improve support for extending pytest.cosim_test by @teqdruid in #9765
  • [FIRRTL] Add instance macro attribute to InstanceChoice for Lowering by @uenoku in #9760
  • [FIRRTL] Lazily construct CircuitNamespace, NFC by @uenoku in #9767
  • [FIRRTL] Support FInstanceLike operations in ModuleInliner by @uenoku in #9688
  • [ESI][Runtime] Don't crash on unsupported type by @teqdruid in #9768
  • [PyCDE] Remove python 3.8, 3.9 and add 3.14 builds by @teqdruid in #9769
  • [PyCDE] Disable cocotb tests by default by @teqdruid in #9770
  • [Arc] Lower llhd.current_time to Arc in LowerState by @fabianschuiki in #9756
  • [FIRRTL] Add domain create op by @seldridge in #9774
  • [FIRRTL] Improve error messages for domain symbol verification by @seldridge in #9776
  • [Moore][ImportVerilog] Add support for fork-join blocks by @tdps2 in #9682
  • [FIRRTL] Add conservative IMDCE handling for InstanceChoiceOp by @uenoku in #9710
  • [Arc] Lower time operations to LLVM IR by @fabianschuiki in #9757
  • [FIRRTL] Support merging layers in LinkCircuits by @unlsycn in #9677
  • [ImportVerilog] Add support for $swrite by @fabianschuiki in #9782
  • [Moore] Add %m/%M hierarchical path format specifier by @fabianschuiki in #9783
  • [Comb] [NFC] Reorder arguments for the consistency in CombOps create* helpers by @uenoku in #9799
  • [RTG] Same seed for all tests & random scopes by @maerhart in #9793
  • [RTG][Elaboration] Fix getUniformInRange by @maerhart in #9806
  • [PyCDE] Fix Struct metaclass for Python 3.14 (PEP 649/749 annotations) and CI disk space by @Copilot in #9773
  • [circt-verilog] Bump slang version requirement to 10.0 by @unlsycn in #9808
  • [ImportVerilog][Sim][MooreToCore] Add support for resizing queues by @Lauriethefish in #9780
  • [Arc] Use simulation time for VCD timestamps by @fabianschuiki in #9785
  • [Moore][MooreToCore][Sim] Support for basic uses of moore.dyn_queue_ref_element by @Lauriethefish in #9778
  • [ImportVerilog][Moore] Add support for queue concatenations by @Lauriethefish in #9777
  • [ESI Runtime] Add statically typed port wrappers by @teqdruid in #9771
  • [ESI] Add ValidOnly channel signaling protocol by @teqdruid in #9787
  • [ESI][Copilot] Add ESI runtime development skills file by @teqdruid in #9812
  • [Comb] Officialize support for zero-width integers by @Moxinilian in #6959
  • [SV] Add an utility function to construct nested ifdefs by @uenoku in #9798
  • [FIRRTL] Allow keywords as identifiers in expressions by @seldridge in #9788
  • [ImportLiberty] Remove unused functions, NFC by @uenoku in #9813
  • [FIRRTL] Add case_macro attribute to OptionCaseOp and refactor PopulateInstanceChoiceSymbols by @uenoku in #9797
  • [FIRRTL][LowerToHW] Require instance_macro before lowering by @uenoku in #9814
  • [FIRRTL] Allow Unknown as an identifier by @seldridge in #9789
  • [RTG][circt-tblgen] Add RegisterAllocationOpInterface methods and decorators by @maerhart in #9801
  • [VerifToSMT] Add meaningful name prefixes to BMC symbolic constants by @5iri in #9794
  • [ImportVerilog] Add support for associative array extractions by @Elijah-Cheesman in #9796
  • [HWToBTOR2][NFC] Fix typo in multi-clock error by @TaoBi22 in #9819
  • [Synth][CutRewriter] Add LogicNetwork flat IR by @uenoku in #9804
  • [Synth][CutRewriter] Migrate CutRewriter to use Flat IR by @uenoku in #9805
  • [ESI][Cosim][Pytest] Increase debug-ability of cosim pytest runs by @teqdruid in #9825
  • [Tools] Set bug report messages to CIRCT by @uenoku in #9826
  • [Synth][CutRewriter] Add a LEC test for mig/xor, NFC by @uenoku in #9828
  • [FSM] Convert FSM to SMT by @luisacicolini in #9379
  • [FIRRTL][Inliner] Fix NLA updates during flattening by @seldridge in #9810
  • [ImportVerilog] Add delete and clear ops for assoc arrays by @Elijah-Cheesman in #9823
  • [FIRRTL][Inliner] Remove flattenPoint, use inlinedSymbols by @seldridge in #9816
  • [RTG][circt-tblgen] Auto-generate instruction assembly and binary emission methods by @maerhart in #9802
  • [ImportVerilog] Support DPI-C extern declarations and open arrays by @pscabot in #9809
  • [FIRRTL] InstanceChoice support for LowerToHW, Part 2(ABI lowering) by @uenoku in #9761
  • [FIRRTL][LowerDomains] Add support for DomainCreateOp by @seldridge in #9781
  • [Synth][CutRewriter] Fix potential non-determinism by @uenoku in #9830
  • [LowerToHW] Use "-" for instance choice header file delimiter by @uenoku in #9832
  • [Synth][SOPBalancing] Fix non-determinism from duplicated value numbering by @uenoku in #9836
  • [FIRRTL] Use hw.hierpath in CreateSiFiveMetadata by @seldridge in #9829
  • [HWToBTOR2] Strengthen multi-clocking detection by @TaoBi22 in #9820
  • Update to avoid arith i0 by @jpienaar in #9835
  • [ImportVerilog] Waive another valgrind test, NFC by @seldridge in #9841
  • [Handshake] Fix deprecated builder.create warnings by @seldridge in #9843
  • [SV] Remove extract-test-code by @rwy7 in #8846

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Full Changelog: firtool-1.141.0...firtool-1.142.0

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fabianschuiki, jpienaar, and 16 other contributors
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firtool-1.141.1

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firtool-1.141.1
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