DeepSeek 4 Flash and PRO local inference engine for Metal, CUDA and ROCm

Python wrapper for the CaDiCaL SAT solver

Cohesix is an open-source high-assurance control-plane operating system built on the formally verified seL4 microkernel, designed to keep the trusted computing base intentionally small while enabli…

Self-contained RTL to GDS flow for simple chip designs

LLM-Assisted Hardware Formal Verification Tool

The HW-CBMC and EBMC Model Checkers for Verilog

LEC - Logic Equivalence Checking - Formal Verification

A simple superscalar out-of-order RISC-V microprocessor

RTLMeter benchmark suite

VHDL compiler and simulator

CAN FD IP Core in VHDL

[WIP] Open-source DFT flow

Attempt to make a go module for fuzzing verilog simulators

CoolRunner-II Bitstream crate

Nix flake for more up-to-date versions of EDA tools

ASIC implementation flow infrastructure, successor to OpenLane

Scots Army Knife for electronics

An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders

[MIGRATED to https://codeberg.org/prjunnamed/prjunnamed] End-to-end synthesis and P&R toolchain

An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.

Experimental flows using nextpnr for Xilinx devices

Netlist API (and more) for EDA flow development

Personal Active Dosimeter (PAD) training model with optional Dosimeter Display Unit (DDU). The system safely simulates radiation exposure without real hazards.

Incremental Model Checking Toolkit

Eclipse Layout Kernel - Automatic layout for Java applications.