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AUTOMATIC VHDL GENERATION FOR CNN MODELS

VHDL 32 13 Updated Nov 16, 2022

基于ZYNQ+AD9363的开源SDR硬件

VHDL 589 165 Updated Sep 13, 2022

FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)

SystemVerilog 142 45 Updated Apr 24, 2026