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fcapz: Open-source, vendor-agnostic full-featured FPGA debug cores. Embedded Logic analyzer, Embedded I/O and Embedded JTAG-AXI
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our d…
An open-source HDL register code generator fast enough to run in real time.
High performance self-hosted photo and video management solution.
An open-source FPGA development board in RaspberryPi Pico form factor.
Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards
Universal utility for programming FPGA
Multi-platform nightly builds of open source digital design and verification tools
VUnit is a unit testing framework for VHDL/SystemVerilog
A Formal Verification Methodology to lower the adoption barriers for Formal Verification of ASIC and FPGA designs in the Space sector (this is a mirror of https://gitlab.com/fvmformal/fvm : you can…
Implementation of hardware cores—including encryption, PRNGs, DSP modules, and accelerators—developed in pure Verilog for reference. Each design is validated against official specifications and sup…
A Self-contained Latex Book/Note Writing Tutorial.
A collection of my latex notes, showcased as templates.
Generate VHDL RTL that implements a register block from compiled SystemRDL input.
AXI, AXI stream, Ethernet, and PCIe components in System Verilog
Verilog AXI components for FPGA implementation
Example how to run HDL unit-tests with Vunit
Observing and optimizing synthesis of common bit manipulation operations for FPGA and ASIC
Style guide enforcement for VHDL
micro version of cocotb, to run on microcontrollers or desktop to get hardware in the loop
Code documentation written as code! How novel and totally my idea!
Package manager and build abstraction tool for FPGA/ASIC development
Files for Hackster project https://www.hackster.io/adam-taylor/fun-with-fusesoc-7b2b1d