Artifact for the CAV'26 paper: A Multi-Width Parametric Bitvector Equivalence Solver

An Open-source FPGA IP Generator

CoreSmith is a Prompt to GDS Agentic Flow

Agile Hardware Design Course

CodeEvolve is an open-source evolutionary coding agent for algorithm discovery and optimization.

Convert Verilog to a Hardcaml design

An MLIR-based toolchain for AMD AI Engine-enabled devices.

Hardware Accelerated FPGA Divide-and-Conquer Page Placement in Milliseconds (FPGA '26)

wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.

Open Source Global Intelligence Platform - Real-Time OSINT Dashboard - A Palantir Alternative

Rocq framework to define the semantics of CPU architectures

HARC: verification language compiler, sister to ARCH

HLS RTL LLM Rewriting

HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond

static symmetry breaking for SAT

An MLIR-based toolchain for AMD AI Engine-enabled devices.

[FCCM 2026] Official repository for LUT-LLM: Efficient Language Model Inference with Memory-based Computation on FPGAs

ReFHE-NTT: Resource-Driven NTT FPGA Architecture for Fully Homomorphic Encryption

A compiler for lowering quantized ML operators to AMD AI Engine (AIE) firmware.

Vitis HLS Library for FINN

Configurable low-precision floating-point and microscaling hardware in Chisel

A SystemVerilog language server based on the Slang library.

Open source high performance IEEE-754 floating unit

A Python-based HDL and framework for silicon-based witchcraft

ARCH hardware description language and compiler

A theoretical reconstruction of the Claude Mythos architecture, built from first principles using the available research literature.

Test suite designed to check compliance with the SystemVerilog standard.

SystemVerilog parser library fully compliant with IEEE 1800-2017

Tile based architecture designed for computing efficiency, scalability and generality

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication