Simple OTDR SOR file parser written in Python

schematics and other files relating to the hardware of our cape for the beaglebone

Laboratory works for digital electronics course in Kyiv Polytechnic Institute, Department of Design of Electronic Digital Equipment, Electronics faculty

Official Docker image for QGIS Server and Desktop

Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or SoC design without using a physical cable.

micro read line library for small and embedded devices

Flashing Pano Logic thin clients without a programmer

Prototype time domain reflectometer/sampling oscilloscope

zx spectrum48 fpga xilinx

Sinclair ZX Spectrum 48k and 128k on an Altera DE1 FPGA board

ESP32/8266 Arduino as (X)SVF JTAG programmer

Simulation of the classic Pacman arcade game on a PanoLogic thin client.

Constraints file and Verilog demo code for the Pano Logic Zero Client G2

A repository for a random collection of stuff pertaining to reverse engineering the Pano Logic G2 "zero" client

Pano Logic G2 Reverse Engineering Project

Information about eeColor Color3 HDMI FPGA board

PanoLogic Zero Client G1 reverse engineering info

Simple OTDR SOR file parser (Perl)

stm32f103c8t6 spectrum emulator

TI TUBS3410 USB cleint Stack + USB Blaster Clone

An OpenSource Boundary Scan Test System (JTAG / IEEE1149.x)

A Grako-based parser for IEEE 1149.1 Boundary-Scan Description Language (BSDL) files

FMCW radar design files

FMCW radar design files

Replica of MK-61 programmable calculator is based on a cycle-accurate model of legacy ICs running on a modern microcontroller.

Android USB host serial driver library for CDC, FTDI, Arduino and other devices.

Android 3.x USB Host Serial Driver

QGIS Plugin for OGC Web Feature Service 2.0.0