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artix7
Here are 21 public repositories matching this topic...
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
python toolchain documentation fpga sphinx primitives verilog synthesis lattice hdl xilinx-fpga ice40 artix7 artix vpr kintex7 architecture-definitions verilog-simulator symbiflow verilog-simulations
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Jun 12, 2026 - Jupyter Notebook
北京邮电大学 2023-2024 春季学期《数字逻辑与数字系统课程设计》——电子钟、药片装瓶系统和贪吃蛇
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Aug 31, 2024 - SystemVerilog
A Verilog based Fractal Set Generator for the Xilinx Artix 7
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Dec 10, 2021 - Verilog
Realtime Audio Processing on Artix-7 FPGA written in VHDL
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Nov 18, 2022 - VHDL
RISC-V pipeline research: RV32IM soft core, branch prediction (SGF), FPGA experiments + paper
cpu fpga riscv rtl verilog xilinx vivado systemverilog computer-architecture hdl microarchitecture open-source-hardware branch-prediction artix7 rv32im cpu-design soft-processor reconfigurable-computing gshare tage
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May 28, 2026 - SystemVerilog
High-speed heterogeneous computing bridge between STM32H7 and Artix-7 FPGA using SPI and FreeRTOS
spi-interface fpga stm32 freertos spi xilinx systemverilog i2c-bus hardware-acceleration cortex-m7 dma memory-mapped embedded-c artix7 stm32h7 heterogeneous-computing stm32cubeide co-processing
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Feb 9, 2026 - C
This project implements a fully functional UART transmitter that divides the Basys 3's 100 MHz system clock down to a 9600 baud timing reference, builds 10-bit UART frames, and continuously transmits an ASCII message over the onboard USB-UART bridge.
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Jun 1, 2026 - VHDL
Implementación hardware VHDL de la Máquina Enigma sobre FPGA Artix-7 (Basys 3). Incluye aritmética modular, lógica de rotores electromecánicos y datapath dedicado.
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Feb 6, 2026 - VHDL
This work presents the design and implementation of high performance and low power 32-bit RISC-V processor 4-stage pipelined for non-load and 5-stage for load operations, also extending its capabilities as system on chip (SoC) design. RV32I with M extension designed for FPGA and ASIC
asic fpga pipeline processor embedded-systems isa cprogramming risc-v cadence genus coremark rv32i artix7 digitaldesign nexys4ddr dhrystone rv32im innovus systemonchip xilinxvivado
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Mar 28, 2026
Deterministic NEMA v0.1 toolchain for connectome simulation on Artix-7: IR validation, bit-exact fixed-point reference, HLS flow, and reproducible artifacts.
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Mar 3, 2026 - Python
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Sep 21, 2024 - Tcl
Comparative study of Mealy vs Moore FSM architectures in Verilog - Multi-item vending machine controller with timing analysis, and power metrics (79-81.5MHz on Artix-7)
fsm fpga state-machine verilog digital-design xilinx-vivado mealy-machine artix7 moore-machine comparative-study vlsi-design rtl-design hardware-design
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Oct 2, 2025 - Verilog
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Sep 14, 2024
FSM-based Smart Traffic Light Controller implemented in Verilog on Artix-7 FPGA with pedestrian crossing, emergency override, and night mode support.
fsm fpga embedded-systems verilog vivado digital-design traffic-light-controller artix7 hardware-design
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May 31, 2026 - Verilog
4-bit Processor designed in Verilog HDL featuring Fetch, Decode, Execute and Write-Back stages with ALU operations, register file implementation, simulation, and FPGA synthesis using Xilinx Vivado.
fpga verilog xilinx vivado computer-architecture alu vlsi verilog-hdl instruction-set digital-design artix7 processor-design rtl-design hardware-design register-fi
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Jun 11, 2026 - Verilog
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